Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)    Driver for the Spase sp887x demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This driver needs external firmware. Please use the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * "<kerneldir>/scripts/get_dvb_firmware sp887x" to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * download/extract it, and then copy it to /usr/lib/hotplug/firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * or /lib/firmware (depending on configuration of firmware hotplug).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define SP887X_DEFAULT_FIRMWARE "dvb-fe-sp887x.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "sp887x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct sp887x_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	const struct sp887x_config* config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	/* demodulator private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u8 initialised:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		if (debug) printk(KERN_DEBUG "sp887x: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static int i2c_writebytes (struct sp887x_state* state, u8 *buf, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = len };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		printk ("%s: i2c write error (addr %02x, err == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			__func__, state->config->demod_address, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static int sp887x_writereg (struct sp887x_state* state, u16 reg, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u8 b0 [] = { reg >> 8 , reg & 0xff, data >> 8, data & 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		 *  in case of soft reset we ignore ACK errors...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		if (!(reg == 0xf1a && data == 0x000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			(ret == -EREMOTEIO || ret == -EFAULT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			printk("%s: writereg error (reg %03x, data %03x, ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			       __func__, reg & 0xffff, data & 0xffff, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static int sp887x_readreg (struct sp887x_state* state, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u8 b0 [] = { reg >> 8 , reg & 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u8 b1 [2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct i2c_msg msg[] = {{ .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 2 }};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		printk("%s: readreg error (ret == %i)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return (((b1[0] << 8) | b1[1]) & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static void sp887x_microcontroller_stop (struct sp887x_state* state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	sp887x_writereg(state, 0xf08, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	sp887x_writereg(state, 0xf09, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* microcontroller STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	sp887x_writereg(state, 0xf00, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void sp887x_microcontroller_start (struct sp887x_state* state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	sp887x_writereg(state, 0xf08, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	sp887x_writereg(state, 0xf09, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/* microcontroller START */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	sp887x_writereg(state, 0xf00, 0x001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void sp887x_setup_agc (struct sp887x_state* state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/* setup AGC parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	sp887x_writereg(state, 0x33c, 0x054);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	sp887x_writereg(state, 0x33b, 0x04c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	sp887x_writereg(state, 0x328, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	sp887x_writereg(state, 0x327, 0x005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	sp887x_writereg(state, 0x326, 0x001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	sp887x_writereg(state, 0x325, 0x001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	sp887x_writereg(state, 0x324, 0x001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	sp887x_writereg(state, 0x318, 0x050);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	sp887x_writereg(state, 0x317, 0x3fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	sp887x_writereg(state, 0x316, 0x001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	sp887x_writereg(state, 0x313, 0x005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	sp887x_writereg(state, 0x312, 0x002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	sp887x_writereg(state, 0x306, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	sp887x_writereg(state, 0x303, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BLOCKSIZE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define FW_SIZE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  *  load firmware and setup MPEG interface...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int sp887x_initial_setup (struct dvb_frontend* fe, const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct sp887x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u8 buf [BLOCKSIZE + 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	int fw_size = fw->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	const unsigned char *mem = fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* ignore the first 10 bytes, then we expect 0x4000 bytes of firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (fw_size < FW_SIZE + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	mem = fw->data + 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	sp887x_writereg(state, 0xf1a, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	sp887x_microcontroller_stop (state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	printk ("%s: firmware upload... ", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* setup write pointer to -1 (end of memory) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* bit 0x8000 in address is set to enable 13bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	sp887x_writereg(state, 0x8f08, 0x1fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/* dummy write (wrap around to start of memory) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	sp887x_writereg(state, 0x8f0a, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	for (i = 0; i < FW_SIZE; i += BLOCKSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		int c = BLOCKSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		if (c > FW_SIZE - i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			c = FW_SIZE - i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		/* bit 0x8000 in address is set to enable 13bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		/* bit 0x4000 enables multibyte read/write transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		/* write register is 0xf0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		buf[0] = 0xcf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		buf[1] = 0x0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		memcpy(&buf[2], mem + i, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		if ((err = i2c_writebytes (state, buf, c+2)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			printk ("failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			printk ("%s: i2c error (err == %i)\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* don't write RS bytes between packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	sp887x_writereg(state, 0xc13, 0x001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* suppress clock if (!data_valid) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	sp887x_writereg(state, 0xc14, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* setup MPEG interface... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	sp887x_writereg(state, 0xc1a, 0x872);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	sp887x_writereg(state, 0xc1b, 0x001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	sp887x_writereg(state, 0xc1c, 0x000); /* parallel mode (serial mode == 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	sp887x_writereg(state, 0xc1a, 0x871);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	/* ADC mode, 2 for MT8872, 3 for SP8870/SP8871 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	sp887x_writereg(state, 0x301, 0x002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	sp887x_setup_agc(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	/* bit 0x010: enable data valid signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	sp887x_writereg(state, 0xd00, 0x010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	sp887x_writereg(state, 0x0d1, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int configure_reg0xc05(struct dtv_frontend_properties *p, u16 *reg0xc05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	int known_parameters = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	*reg0xc05 = 0x000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	switch (p->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case QPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		*reg0xc05 |= (1 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		*reg0xc05 |= (2 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	case QAM_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		known_parameters = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	switch (p->hierarchy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	case HIERARCHY_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	case HIERARCHY_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		*reg0xc05 |= (1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	case HIERARCHY_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		*reg0xc05 |= (2 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	case HIERARCHY_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		*reg0xc05 |= (3 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	case HIERARCHY_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		known_parameters = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	switch (p->code_rate_HP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		*reg0xc05 |= (1 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		*reg0xc05 |= (2 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		*reg0xc05 |= (3 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		*reg0xc05 |= (4 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	case FEC_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		known_parameters = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (known_parameters)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		*reg0xc05 |= (2 << 1);	/* use specified parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		*reg0xc05 |= (1 << 1);	/* enable autoprobing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  *  estimates division of two 24bit numbers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  *  derived from the ves1820/stv0299 driver code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void divide (int n, int d, int *quotient_i, int *quotient_f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	unsigned int q, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	r = (n % d) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	q = (r / d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (quotient_i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		*quotient_i = q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (quotient_f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		r = (r % d) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		q = (q << 8) | (r / d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		r = (r % d) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		*quotient_f = (q << 8) | (r / d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void sp887x_correct_offsets (struct sp887x_state* state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 				    struct dtv_frontend_properties *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 				    int actual_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	static const u32 srate_correction [] = { 1879617, 4544878, 8098561 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	int bw_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	int freq_offset = actual_freq - p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	int sysclock = 61003; //[kHz]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	int ifreq = 36000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int frequency_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	switch (p->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		bw_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		bw_index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		bw_index = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (p->inversion == INVERSION_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		freq = ifreq - freq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		freq = ifreq + freq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	divide(freq / 333, sysclock, NULL, &frequency_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (p->inversion == INVERSION_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		frequency_shift = -frequency_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	/* sample rate correction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	sp887x_writereg(state, 0x319, srate_correction[bw_index] >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	sp887x_writereg(state, 0x31a, srate_correction[bw_index] & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	/* carrier offset correction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	sp887x_writereg(state, 0x309, frequency_shift >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	sp887x_writereg(state, 0x30a, frequency_shift & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int sp887x_setup_frontend_parameters(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	struct sp887x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	unsigned actual_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	u16 val, reg0xc05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (p->bandwidth_hz != 8000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	    p->bandwidth_hz != 7000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	    p->bandwidth_hz != 6000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if ((err = configure_reg0xc05(p, &reg0xc05)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	sp887x_microcontroller_stop(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	/* setup the PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (fe->ops.tuner_ops.get_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		fe->ops.tuner_ops.get_frequency(fe, &actual_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		actual_freq = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	/* read status reg in order to clear <pending irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	sp887x_readreg(state, 0x200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	sp887x_correct_offsets(state, p, actual_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	/* filter for 6/7/8 Mhz channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	if (p->bandwidth_hz == 6000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		val = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	else if (p->bandwidth_hz == 7000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	sp887x_writereg(state, 0x311, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	/* scan order: 2k first = 0, 8k first = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	if (p->transmission_mode == TRANSMISSION_MODE_2K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		sp887x_writereg(state, 0x338, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		sp887x_writereg(state, 0x338, 0x001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	sp887x_writereg(state, 0xc05, reg0xc05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	if (p->bandwidth_hz == 6000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		val = 2 << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	else if (p->bandwidth_hz == 7000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		val = 3 << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		val = 0 << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	/* enable OFDM and SAW bits as lock indicators in sync register 0xf17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	 * optimize algorithm for given bandwidth...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	sp887x_writereg(state, 0xf14, 0x160 | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	sp887x_writereg(state, 0xf15, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	sp887x_microcontroller_start(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int sp887x_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	struct sp887x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	u16 snr12 = sp887x_readreg(state, 0xf16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	u16 sync0x200 = sp887x_readreg(state, 0x200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	u16 sync0xf17 = sp887x_readreg(state, 0xf17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	*status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	if (snr12 > 0x00f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		*status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	//if (sync0x200 & 0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	//	*status |= FE_HAS_SYNC | FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	//if (sync0x200 & 0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	//	*status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	if ((sync0xf17 & 0x00f) == 0x002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		*status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		*status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	if (sync0x200 & 0x001) {	/* tuner adjustment requested...*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		int steps = (sync0x200 >> 4) & 0x00f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		if (steps & 0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 			steps = -steps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		dprintk("sp887x: implement tuner adjustment (%+i steps)!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		       steps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int sp887x_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	struct sp887x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	*ber = (sp887x_readreg(state, 0xc08) & 0x3f) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	       (sp887x_readreg(state, 0xc07) << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	sp887x_writereg(state, 0xc08, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	sp887x_writereg(state, 0xc07, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	if (*ber >= 0x3fff0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		*ber = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int sp887x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	struct sp887x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	u16 snr12 = sp887x_readreg(state, 0xf16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	u32 signal = 3 * (snr12 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	*strength = (signal < 0xffff) ? signal : 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int sp887x_read_snr(struct dvb_frontend* fe, u16* snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	struct sp887x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	u16 snr12 = sp887x_readreg(state, 0xf16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	*snr = (snr12 << 4) | (snr12 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int sp887x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	struct sp887x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	*ucblocks = sp887x_readreg(state, 0xc0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	if (*ucblocks == 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		*ucblocks = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static int sp887x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	struct sp887x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		return sp887x_writereg(state, 0x206, 0x001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 		return sp887x_writereg(state, 0x206, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int sp887x_sleep(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	struct sp887x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	/* tristate TS output and disable interface pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	sp887x_writereg(state, 0xc18, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int sp887x_init(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	struct sp887x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	const struct firmware *fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	if (!state->initialised) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 		/* request the firmware, this will block until someone uploads it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 		printk("sp887x: waiting for firmware upload (%s)...\n", SP887X_DEFAULT_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 		ret = state->config->request_firmware(fe, &fw, SP887X_DEFAULT_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 			printk("sp887x: no firmware upload (timeout or file not found?)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 		ret = sp887x_initial_setup(fe, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 		release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 			printk("sp887x: writing firmware to device failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 		printk("sp887x: firmware upload complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 		state->initialised = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	/* enable TS output and interface pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	sp887x_writereg(state, 0xc18, 0x00d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int sp887x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	fesettings->min_delay_ms = 350;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	fesettings->step_size = 166666*2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	fesettings->max_drift = (166666*2)+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static void sp887x_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	struct sp887x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const struct dvb_frontend_ops sp887x_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct dvb_frontend* sp887x_attach(const struct sp887x_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 				   struct i2c_adapter* i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	struct sp887x_state* state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	/* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	state = kzalloc(sizeof(struct sp887x_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	if (state == NULL) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	/* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	state->initialised = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	/* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	if (sp887x_readreg(state, 0x0200) < 0) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	/* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	memcpy(&state->frontend.ops, &sp887x_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const struct dvb_frontend_ops sp887x_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	.delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 		.name = "Spase SP887x DVB-T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 		.frequency_min_hz =  50500 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 		.frequency_max_hz = 858000 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 		.frequency_stepsize_hz = 166666,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 		.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 			FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 			FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 			FE_CAN_RECOVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	.release = sp887x_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	.init = sp887x_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	.sleep = sp887x_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	.i2c_gate_ctrl = sp887x_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	.set_frontend = sp887x_setup_frontend_parameters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	.get_tune_settings = sp887x_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	.read_status = sp887x_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	.read_ber = sp887x_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	.read_signal_strength = sp887x_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	.read_snr = sp887x_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	.read_ucblocks = sp887x_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) MODULE_DESCRIPTION("Spase sp887x DVB-T demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) EXPORT_SYMBOL(sp887x_attach);