Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * CIMaX SP2/HF CI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2014 Olli Salonen <olli.salonen@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef SP2_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define SP2_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "sp2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* state struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct sp2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	struct dvb_adapter *dvb_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	struct dvb_ca_en50221 ca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	int module_access_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	unsigned long next_status_checked_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	void *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	void *ci_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SP2_CI_ATTR_ACS		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SP2_CI_IO_ACS		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SP2_CI_WR		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SP2_CI_RD		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Module control register (0x00 module A, 0x09 module B) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SP2_MOD_CTL_DET		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SP2_MOD_CTL_AUTO	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SP2_MOD_CTL_ACS0	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SP2_MOD_CTL_ACS1	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SP2_MOD_CTL_HAD		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SP2_MOD_CTL_TSIEN	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SP2_MOD_CTL_TSOEN	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SP2_MOD_CTL_RST		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif