Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * CIMaX SP2/HF CI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2014 Olli Salonen <olli.salonen@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef SP2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define SP2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <media/dvb_ca_en50221.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * I2C address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * 0x40 (port 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * 0x41 (port 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct sp2_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	/* dvb_adapter to attach the ci to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	struct dvb_adapter *dvb_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	/* function ci_control handles the device specific ci ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	void *ci_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	/* priv is passed back to function ci_control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	void *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) extern int sp2_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 					int slot, int addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) extern int sp2_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 					int slot, int addr, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) extern int sp2_ci_read_cam_control(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 					int slot, u8 addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) extern int sp2_ci_write_cam_control(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 					int slot, u8 addr, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) extern int sp2_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern int sp2_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) extern int sp2_ci_slot_ts_enable(struct dvb_ca_en50221 *en50221, int slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) extern int sp2_ci_poll_slot_status(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 					int slot, int open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #endif