Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * CIMaX SP2/SP2HF (Atmel T90FJR) CI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 Olli Salonen <olli.salonen@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Heavily based on CIMax2(R) SP2 driver in conjunction with NetUp Dual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * DVB-S2 CI card (cimax2) with following copyrights:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  Copyright (C) 2009 NetUP Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  Copyright (C) 2009 Abylay Ospan <aospan@netup.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "sp2_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) static int sp2_read_i2c(struct sp2 *s, u8 reg, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	struct i2c_client *client = s->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	struct i2c_adapter *adap = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 			.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 			.flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 			.buf = &reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 			.len = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 			.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 			.flags	= I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 			.buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 			.len = len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	ret = i2c_transfer(adap, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		dev_err(&client->dev, "i2c read error, reg = 0x%02x, status = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 				reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	dev_dbg(&s->client->dev, "addr=0x%04x, reg = 0x%02x, data = %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 				client->addr, reg, buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static int sp2_write_i2c(struct sp2 *s, u8 reg, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u8 buffer[35];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct i2c_client *client = s->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct i2c_adapter *adap = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.buf = &buffer[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.len = len + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if ((len + 1) > sizeof(buffer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		dev_err(&client->dev, "i2c wr reg=%02x: len=%d is too big!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 				reg, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	buffer[0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	memcpy(&buffer[1], buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	ret = i2c_transfer(adap, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		dev_err(&client->dev, "i2c write error, reg = 0x%02x, status = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 				reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	dev_dbg(&s->client->dev, "addr=0x%04x, reg = 0x%02x, data = %*ph\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 				client->addr, reg, len, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int sp2_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot, u8 acs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			u8 read, int addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct sp2 *s = en50221->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u8 store;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int mem, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	int (*ci_op_cam)(void*, u8, int, u8, int*) = s->ci_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (slot != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * change module access type between IO space and attribute memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * when needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (s->module_access_type != acs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		ret = sp2_read_i2c(s, 0x00, &store, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		store &= ~(SP2_MOD_CTL_ACS1 | SP2_MOD_CTL_ACS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		store |= acs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		ret = sp2_write_i2c(s, 0x00, &store, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	s->module_access_type = acs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* implementation of ci_op_cam is device specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (ci_op_cam) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		ret = ci_op_cam(s->priv, read, addr, data, &mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		dev_err(&s->client->dev, "callback not defined");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	dev_dbg(&s->client->dev, "%s: slot=%d, addr=0x%04x, %s, data=%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			(read) ? "read" : "write", slot, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			(acs == SP2_CI_ATTR_ACS) ? "attr" : "io",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			(read) ? mem : data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		return mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int sp2_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 				int slot, int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return sp2_ci_op_cam(en50221, slot, SP2_CI_ATTR_ACS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			SP2_CI_RD, addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int sp2_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				int slot, int addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return sp2_ci_op_cam(en50221, slot, SP2_CI_ATTR_ACS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			SP2_CI_WR, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int sp2_ci_read_cam_control(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				int slot, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	return sp2_ci_op_cam(en50221, slot, SP2_CI_IO_ACS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			SP2_CI_RD, addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int sp2_ci_write_cam_control(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				int slot, u8 addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return sp2_ci_op_cam(en50221, slot, SP2_CI_IO_ACS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			SP2_CI_WR, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int sp2_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct sp2 *s = en50221->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	u8 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	dev_dbg(&s->client->dev, "slot: %d\n", slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (slot != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* RST on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	buf = SP2_MOD_CTL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ret = sp2_write_i2c(s, 0x00, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	usleep_range(500, 600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* RST off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	buf = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	ret = sp2_write_i2c(s, 0x00, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int sp2_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct sp2 *s = en50221->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	dev_dbg(&s->client->dev, "slot:%d\n", slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	/* not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int sp2_ci_slot_ts_enable(struct dvb_ca_en50221 *en50221, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct sp2 *s = en50221->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	u8 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	dev_dbg(&s->client->dev, "slot:%d\n", slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (slot != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	sp2_read_i2c(s, 0x00, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* disable bypass and enable TS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	buf |= (SP2_MOD_CTL_TSOEN | SP2_MOD_CTL_TSIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return sp2_write_i2c(s, 0, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int sp2_ci_poll_slot_status(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 				int slot, int open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct sp2 *s = en50221->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	dev_dbg(&s->client->dev, "slot:%d open:%d\n", slot, open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 * CAM module INSERT/REMOVE processing. Slow operation because of i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 * transfers. Throttle read to one per sec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (time_after(jiffies, s->next_status_checked_time)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		ret = sp2_read_i2c(s, 0x00, buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		s->next_status_checked_time = jiffies +	msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		if (buf[0] & SP2_MOD_CTL_DET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			s->status = DVB_CA_EN50221_POLL_CAM_PRESENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 					DVB_CA_EN50221_POLL_CAM_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			s->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return s->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int sp2_init(struct sp2 *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	u8 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	u8 cimax_init[34] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		0x00, /* module A control*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		0x00, /* auto select mask high A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		0x00, /* auto select mask low A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		0x00, /* auto select pattern high A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		0x00, /* auto select pattern low A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		0x44, /* memory access time A, 600 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		0x00, /* invert input A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		0x00, /* RFU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		0x00, /* RFU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		0x00, /* module B control*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		0x00, /* auto select mask high B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		0x00, /* auto select mask low B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		0x00, /* auto select pattern high B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		0x00, /* auto select pattern low B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		0x44, /* memory access time B, 600 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		0x00, /* invert input B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		0x00, /* RFU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		0x00, /* RFU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		0x00, /* auto select mask high Ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		0x00, /* auto select mask low Ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		0x00, /* auto select pattern high Ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		0x00, /* auto select pattern low Ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		0x00, /* RFU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		0x02, /* destination - module A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		0x01, /* power control reg, VCC power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		0x00, /* RFU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		0x00, /* int status read only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		0x00, /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		0x05, /* EXTINT=active-high, INT=push-pull */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		0x00, /* USCG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		0x04, /* ack active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		0x00, /* LOCK = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		0x22, /* unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		0x00, /* synchronization? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	dev_dbg(&s->client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	s->ca.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	s->ca.read_attribute_mem = sp2_ci_read_attribute_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	s->ca.write_attribute_mem = sp2_ci_write_attribute_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	s->ca.read_cam_control = sp2_ci_read_cam_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	s->ca.write_cam_control = sp2_ci_write_cam_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	s->ca.slot_reset = sp2_ci_slot_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	s->ca.slot_shutdown = sp2_ci_slot_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	s->ca.slot_ts_enable = sp2_ci_slot_ts_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	s->ca.poll_slot_status = sp2_ci_poll_slot_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	s->ca.data = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	s->module_access_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	/* initialize all regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	ret = sp2_write_i2c(s, 0x00, &cimax_init[0], 34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	/* lock registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	buf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	ret = sp2_write_i2c(s, 0x1f, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	/* power on slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	ret = sp2_write_i2c(s, 0x18, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	ret = dvb_ca_en50221_init(s->dvb_adap, &s->ca, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	dev_dbg(&s->client->dev, "init failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int sp2_exit(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct sp2 *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (!client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	s = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (!s->ca.data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	dvb_ca_en50221_release(&s->ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int sp2_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	struct sp2_config *cfg = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	struct sp2 *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	s = kzalloc(sizeof(*s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (!s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	s->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	s->dvb_adap = cfg->dvb_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	s->priv = cfg->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	s->ci_control = cfg->ci_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	i2c_set_clientdata(client, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	ret = sp2_init(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	dev_info(&s->client->dev, "CIMaX SP2 successfully attached\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	dev_dbg(&client->dev, "init failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	kfree(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int sp2_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	struct sp2 *s = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	sp2_exit(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	kfree(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const struct i2c_device_id sp2_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	{"sp2", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MODULE_DEVICE_TABLE(i2c, sp2_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static struct i2c_driver sp2_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		.name	= "sp2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	.probe		= sp2_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	.remove		= sp2_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	.id_table	= sp2_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) module_i2c_driver(sp2_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MODULE_DESCRIPTION("CIMaX SP2/HF CI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MODULE_AUTHOR("Olli Salonen <olli.salonen@iki.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MODULE_LICENSE("GPL");