^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Silicon Labs SI2165 DVB-C/-T Demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _DVB_SI2165_PRIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _DVB_SI2165_PRIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SI2165_FIRMWARE_REV_D "dvb-demod-si2165.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct si2165_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* i2c addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * possible values: 0x64,0x65,0x66,0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u8 i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* external clock or XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 chip_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* frequency of external clock or xtal in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * possible values: 4000000, 16000000, 20000000, 240000000, 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 ref_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* invert the spectrum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) bool inversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STATISTICS_PERIOD_PKT_COUNT 30000u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STATISTICS_PERIOD_BIT_COUNT (STATISTICS_PERIOD_PKT_COUNT * 204 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_CHIP_MODE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_CHIP_REVCODE 0x0023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REV_CHIP_TYPE 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_CHIP_INIT 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_INIT_DONE 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_START_INIT 0x0096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_PLL_DIVL 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define REG_RST_ALL 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_LOCK_TIMEOUT 0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REG_AUTO_RESET 0x00cb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_OVERSAMP 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_IF_FREQ_SHIFT 0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_DVB_STANDARD 0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_DSP_CLOCK 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_ADC_RI8 0x0123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_ADC_RI1 0x012a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_ADC_RI2 0x012b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_ADC_RI3 0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_ADC_RI4 0x012d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_ADC_RI5 0x012e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_ADC_RI6 0x012f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_AGC_CRESTF_DBX8 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_AGC_UNFREEZE_THR 0x015b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REG_AGC2_MIN 0x016e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_AGC2_KACQ 0x016c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_AGC2_KLOC 0x016d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_AGC2_OUTPUT 0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_AGC2_CLKDIV 0x0171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_AGC_IF_TRI 0x018b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_AGC_IF_SLR 0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_AAF_CRESTF_DBX8 0x01a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_ACI_CRESTF_DBX8 0x01c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REG_SWEEP_STEP 0x0232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_KP_LOCK 0x023a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_UNKNOWN_24C 0x024c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define REG_CENTRAL_TAP 0x0261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define REG_C_N 0x026c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_EQ_AUTO_CONTROL 0x0278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define REG_UNKNOWN_27C 0x027c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REG_START_SYNCHRO 0x02e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_REQ_CONSTELLATION 0x02f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_T_BANDWIDTH 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_FREQ_SYNC_RANGE 0x030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_IMPULSIVE_NOISE_REM 0x031c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define REG_WDOG_AND_BOOT 0x0341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define REG_PATCH_VERSION 0x0344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define REG_ADDR_JUMP 0x0348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define REG_UNKNOWN_350 0x0350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define REG_EN_RST_ERROR 0x035c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define REG_DCOM_CONTROL_BYTE 0x0364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define REG_DCOM_ADDR 0x0368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define REG_DCOM_DATA 0x036c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define REG_RST_CRC 0x0379
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define REG_GP_REG0_LSB 0x0384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define REG_GP_REG0_MSB 0x0387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define REG_CRC 0x037a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define REG_CHECK_SIGNAL 0x03a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define REG_CBER_RST 0x0424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define REG_CBER_BIT 0x0428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define REG_CBER_ERR 0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define REG_CBER_AVAIL 0x0434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define REG_PS_LOCK 0x0440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define REG_UNCOR_CNT 0x0468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define REG_BER_RST 0x046c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define REG_BER_PKT 0x0470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define REG_BER_BIT 0x0478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define REG_BER_AVAIL 0x047c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define REG_FEC_LOCK 0x04e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define REG_TS_DATA_MODE 0x04e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define REG_TS_CLK_MODE 0x04e5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define REG_TS_TRI 0x04ef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define REG_TS_SLR 0x04f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define REG_RSSI_ENABLE 0x0641
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define REG_RSSI_PAD_CTRL 0x0646
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_TS_PARALLEL_MODE 0x08f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif /* _DVB_SI2165_PRIV */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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