Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Driver for Silicon Labs SI2165 DVB-C/-T Demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * References:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *   http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _DVB_SI2165_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _DVB_SI2165_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	SI2165_MODE_OFF = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	SI2165_MODE_PLL_EXT = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	SI2165_MODE_PLL_XTAL = 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* I2C addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * possible values: 0x64,0x65,0x66,0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct si2165_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	 * frontend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	 * returned by driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	struct dvb_frontend **fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	/* external clock or XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	u8 chip_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	/* frequency of external clock or xtal in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	 * possible values: 4000000, 16000000, 20000000, 240000000, 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	u32 ref_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	/* invert the spectrum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	bool inversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif /* _DVB_SI2165_H */