Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *   Sharp VA3A5JZ921 One Seg Broadcast Module driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *   This device is labeled as just S. 921 at the top of the frontend can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *   Copyright (C) 2009-2010 Mauro Carvalho Chehab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *   Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *   Developed for Leadership SBTVD 1seg device sold in Brazil
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *   Frontend module based on cx24123 driver, getting some info from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *	the old s921 driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *   FIXME: Need to port to DVB v5.2 API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "s921.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static int debug = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define rc(args...)  do {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	printk(KERN_ERR  "s921: " args);				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define dprintk(args...)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	do {								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		if (debug) {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			printk(KERN_DEBUG "s921: %s: ", __func__);	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 			printk(args);					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		}							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) struct s921_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	const struct s921_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	/* The Demod can't easily provide these, we cache them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u32 currentfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * Various tuner defaults need to be established for a given frequency kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * fixme: The bounds on the bands do not match the doc in real life.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * fixme: Some of them have been moved, other might need adjustment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static struct s921_bandselect_val {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u32 freq_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u8  band_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) } s921_bandselect[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{         0, 0x7b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{ 485140000, 0x5b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{ 515140000, 0x3b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{ 545140000, 0x1b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ 599140000, 0xfb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{ 623140000, 0xdb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{ 659140000, 0xbb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{ 713140000, 0x9b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) struct regdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static struct regdata s921_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	{ 0x01, 0x80 },		/* Probably, a reset sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{ 0x01, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{ 0x01, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{ 0x01, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{ 0x02, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{ 0x03, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{ 0x04, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{ 0x05, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{ 0x06, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{ 0x07, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	{ 0x08, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	{ 0x09, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{ 0x0a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{ 0x0b, 0x5a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{ 0x0c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{ 0x0d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{ 0x0f, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	{ 0x13, 0x1b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	{ 0x14, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{ 0x15, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	{ 0x17, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	{ 0x18, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	{ 0x19, 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{ 0x1a, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{ 0x1b, 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{ 0x1c, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{ 0x1d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	{ 0x1e, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	{ 0x1f, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{ 0x20, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{ 0x21, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{ 0x22, 0x4c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{ 0x23, 0x4e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{ 0x24, 0x4c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{ 0x25, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	{ 0x26, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	{ 0x27, 0xf4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	{ 0x28, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{ 0x29, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{ 0x2a, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	{ 0x2b, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	{ 0x2c, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{ 0x2d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	{ 0x2e, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{ 0x2f, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{ 0x30, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{ 0x31, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	{ 0x32, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{ 0x34, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{ 0x37, 0xfe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{ 0x38, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{ 0x39, 0x63 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ 0x3a, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{ 0x3b, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{ 0x47, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{ 0x49, 0xe5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{ 0x4b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{ 0x50, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{ 0x52, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{ 0x54, 0x5a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{ 0x55, 0x5b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	{ 0x56, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	{ 0x57, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	{ 0x5c, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{ 0x5d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	{ 0x62, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	{ 0x63, 0x2f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	{ 0x64, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{ 0x68, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	{ 0x69, 0x89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	{ 0x6a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	{ 0x6b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{ 0x6c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	{ 0x6d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	{ 0x6e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	{ 0x70, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{ 0x71, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{ 0x75, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{ 0x76, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{ 0x77, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	{ 0xaf, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	{ 0xb0, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	{ 0xb2, 0x3d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{ 0xb3, 0x25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	{ 0xb4, 0x8b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	{ 0xb5, 0x4b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	{ 0xb6, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	{ 0xb7, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	{ 0xb8, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	{ 0xb9, 0xfc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	{ 0xba, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	{ 0xbb, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	{ 0xbc, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	{ 0xd0, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{ 0xe4, 0x84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{ 0xf0, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{ 0xf1, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	{ 0xf2, 0x5a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	{ 0xf3, 0x8e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	{ 0xf4, 0x2d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	{ 0xf5, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	{ 0xf6, 0x5a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	{ 0xf7, 0xba },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	{ 0xf8, 0xd7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct regdata s921_prefreq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	{ 0x47, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	{ 0x68, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	{ 0x69, 0x89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	{ 0xf0, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	{ 0xf1, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct regdata s921_postfreq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	{ 0xf5, 0xae },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	{ 0xf6, 0xb7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	{ 0xf7, 0xba },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	{ 0xf8, 0xd7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	{ 0x68, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	{ 0x69, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int s921_i2c_writereg(struct s921_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			     u8 i2c_addr, int reg, int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	u8 buf[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	rc = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (rc != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		printk("%s: writereg rcor(rc == %i, reg == 0x%02x, data == 0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		       __func__, rc, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int s921_i2c_writeregdata(struct s921_state *state, u8 i2c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				 struct regdata *rd, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		rc = s921_i2c_writereg(state, i2c_addr, rd[i].reg, rd[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int s921_i2c_readreg(struct s921_state *state, u8 i2c_addr, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		{ .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		{ .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	rc = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (rc != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		rc("%s: reg=0x%x (rcor=%d)\n", __func__, reg, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define s921_readreg(state, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	s921_i2c_readreg(state, state->config->demod_address, reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define s921_writereg(state, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	s921_i2c_writereg(state, state->config->demod_address, reg, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define s921_writeregdata(state, regdata) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	s921_i2c_writeregdata(state, state->config->demod_address, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	regdata, ARRAY_SIZE(regdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int s921_pll_tune(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct s921_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	int band, rc, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	unsigned long f_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	u8 f_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	dprintk("frequency=%i\n", p->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	for (band = 0; band < ARRAY_SIZE(s921_bandselect); band++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		if (p->frequency < s921_bandselect[band].freq_low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	band--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (band < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		rc("%s: frequency out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	f_switch = s921_bandselect[band].band_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	offset = ((u64)p->frequency) * 258;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	do_div(offset, 6000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	f_offset = ((unsigned long)offset) + 2321;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	rc = s921_writeregdata(state, s921_prefreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	rc = s921_writereg(state, 0xf2, (f_offset >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	rc = s921_writereg(state, 0xf3, f_offset & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	rc = s921_writereg(state, 0xf4, f_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	rc = s921_writeregdata(state, s921_postfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	for (i = 0 ; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		rc = s921_readreg(state, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		dprintk("status 0x80: %02x\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	rc = s921_writereg(state, 0x01, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	rc = s921_readreg(state, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	dprintk("status 0x01: %02x\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	rc = s921_readreg(state, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	dprintk("status 0x80: %02x\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	rc = s921_readreg(state, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	dprintk("status 0x80: %02x\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	rc = s921_readreg(state, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	dprintk("status 0x32: %02x\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	dprintk("pll tune band=%d, pll=%d\n", f_switch, (int)f_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int s921_initfe(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	struct s921_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	dprintk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	rc = s921_writeregdata(state, s921_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int s921_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	struct s921_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	int regstatus, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	*status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	rc = s921_readreg(state, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	regstatus = rc << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	rc = s921_readreg(state, 0x82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	regstatus |= rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	dprintk("status = %04x\n", regstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	/* Full Sync - We don't know what each bit means on regs 0x81/0x82 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	if ((regstatus & 0xff) == 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		*status = FE_HAS_SIGNAL  |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			  FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			  FE_HAS_VITERBI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			  FE_HAS_SYNC    |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			  FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	} else if (regstatus & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		/* This is close to Full Sync, but not enough to get useful info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		*status = FE_HAS_SIGNAL  |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			  FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			  FE_HAS_VITERBI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			  FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int s921_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	enum fe_status	status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	struct s921_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	/* FIXME: Use the proper register for it... 0x80? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	rc = s921_read_status(fe, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	*strength = (status & FE_HAS_LOCK) ? 0xffff : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	dprintk("strength = 0x%04x\n", *strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	rc = s921_readreg(state, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	dprintk("status 0x01: %02x\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	rc = s921_readreg(state, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	dprintk("status 0x80: %02x\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	rc = s921_readreg(state, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	dprintk("status 0x32: %02x\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int s921_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	struct s921_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	dprintk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	/* FIXME: We don't know how to use non-auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	rc = s921_pll_tune(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	state->currentfreq = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int s921_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 			     struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	struct s921_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	/* FIXME: Probably it is possible to get it from regs f1 and f2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	p->frequency = state->currentfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	p->delivery_system = SYS_ISDBT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int s921_tune(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 			bool re_tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 			unsigned int mode_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 			unsigned int *delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 			enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	dprintk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	if (re_tune)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		rc = s921_set_frontend(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		s921_read_status(fe, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static enum dvbfe_algo s921_get_algo(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	return DVBFE_ALGO_HW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static void s921_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	struct s921_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	dprintk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static const struct dvb_frontend_ops s921_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct dvb_frontend *s921_attach(const struct s921_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 				    struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	/* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	struct s921_state *state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		kzalloc(sizeof(struct s921_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	dprintk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	if (!state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		rc("Unable to kzalloc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	/* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	/* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	memcpy(&state->frontend.ops, &s921_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) EXPORT_SYMBOL(s921_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const struct dvb_frontend_ops s921_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	.delsys = { SYS_ISDBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	/* Use dib8000 values per default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		.name = "Sharp S921",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		.frequency_min_hz = 470 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		 * Max should be 770MHz instead, according with Sharp docs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		 * but Leadership doc says it works up to 806 MHz. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		 * required to get channel 69, used in Brazil
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		.frequency_max_hz = 806 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		.caps =  FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 			 FE_CAN_FEC_1_2  | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 			 FE_CAN_FEC_5_6  | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 			 FE_CAN_QPSK     | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 			 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 			 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 			 FE_CAN_HIERARCHY_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	.release = s921_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	.init = s921_initfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	.set_frontend = s921_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	.get_frontend = s921_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	.read_status = s921_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	.read_signal_strength = s921_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	.tune = s921_tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	.get_frontend_algo = s921_get_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MODULE_DESCRIPTION("DVB Frontend module for Sharp S921 hardware");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MODULE_AUTHOR("Mauro Carvalho Chehab");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MODULE_AUTHOR("Douglas Landgraf <dougsland@redhat.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MODULE_LICENSE("GPL");