Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  Samsung s5h1432 VSB/QAM demodulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __S5H1432_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __S5H1432_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define S5H1432_I2C_TOP_ADDR (0x02 >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TAIWAN_HI_IF_FREQ_44_MHZ 44000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define EUROPE_HI_IF_FREQ_36_MHZ 36000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IF_FREQ_6_MHZ             6000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IF_FREQ_3point3_MHZ       3300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IF_FREQ_3point5_MHZ       3500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IF_FREQ_4_MHZ             4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct s5h1432_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	/* serial/parallel output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S5H1432_PARALLEL_OUTPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S5H1432_SERIAL_OUTPUT   1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	u8 output_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	/* GPIO Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S5H1432_GPIO_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S5H1432_GPIO_ON  1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	u8 gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	/* MPEG signal timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S5H1432_MPEGTIMING_CONTINUOUS_INVERTING_CLOCK       0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S5H1432_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK    1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S5H1432_MPEGTIMING_NONCONTINUOUS_INVERTING_CLOCK    2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S5H1432_MPEGTIMING_NONCONTINUOUS_NONINVERTING_CLOCK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	u16 mpeg_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	/* IF Freq for QAM and VSB in KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S5H1432_IF_3250  3250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S5H1432_IF_3500  3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S5H1432_IF_4000  4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S5H1432_IF_5380  5380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S5H1432_IF_44000 44000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S5H1432_VSB_IF_DEFAULT s5h1432_IF_44000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S5H1432_QAM_IF_DEFAULT s5h1432_IF_44000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	u16 qam_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	u16 vsb_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	/* Spectral Inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S5H1432_INVERSION_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S5H1432_INVERSION_ON  1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	u8 inversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	/* Return lock status based on tuner lock, or demod lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define S5H1432_TUNERLOCKING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S5H1432_DEMODLOCKING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	u8 status_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #if IS_REACHABLE(CONFIG_DVB_S5H1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) extern struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 					   struct i2c_adapter *i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline struct dvb_frontend *s5h1432_attach(const struct s5h1432_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 						  *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 						  struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif /* CONFIG_DVB_s5h1432 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif /* __s5h1432_H__ */