^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Samsung s5h1432 DVB-T demodulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "s5h1432.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct s5h1432_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) const struct s5h1432_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum fe_modulation current_modulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned int first_tune:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 current_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 inversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define dprintk(arg...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) printk(arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int s5h1432_writereg(struct s5h1432_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 addr, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 buf[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct i2c_msg msg = {.addr = addr, .flags = 0, .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ret = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __func__, addr, reg, data, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return (ret != 1) ? -1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 b0[] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 b1[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {.addr = addr, .flags = 0, .buf = b0, .len = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {.addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ret = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) printk(KERN_ERR "%s: readreg error (ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int s5h1432_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct s5h1432_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) reg &= ~(0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) switch (bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reg |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reg |= 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct s5h1432_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) switch (ifFreqHz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case TAIWAN_HI_IF_FREQ_44_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case EUROPE_HI_IF_FREQ_36_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case IF_FREQ_6_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case IF_FREQ_3point3_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case IF_FREQ_3point5_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case IF_FREQ_4_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) (u32) 32768) / (48 * 1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "Default IFFreq %d :reg value = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ifFreqHz, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) (u8) value & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) (u8) (value >> 8) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) (u8) (value >> 16) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int s5h1432_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 dvb_bandwidth = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct s5h1432_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (p->frequency == state->current_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*current_frequency = p->frequency; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*state->current_frequency = p->frequency; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) msleep(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) switch (p->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dvb_bandwidth = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dvb_bandwidth = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dvb_bandwidth = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*fe->ops.tuner_ops.set_params(fe); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*Soft Reset chip*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) switch (p->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dvb_bandwidth = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dvb_bandwidth = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dvb_bandwidth = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*fe->ops.tuner_ops.set_params(fe); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*Soft Reset chip*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) state->current_frequency = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int s5h1432_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct s5h1432_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u8 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) state->current_frequency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) printk(KERN_INFO " s5h1432_init().\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*Set VSB mode as default, this also does a soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*Initialize registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*For NXP tuner*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*Set 3.3MHz as default IF frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Set reg 0x1E to get the full dynamic range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Mode setting in demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) reg |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Serial mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Soft Reset chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int s5h1432_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int s5h1432_read_signal_strength(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u16 *signal_strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int s5h1432_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int s5h1432_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int s5h1432_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int s5h1432_get_tune_settings(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct dvb_frontend_tune_settings *tune)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void s5h1432_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct s5h1432_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const struct dvb_frontend_ops s5h1432_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct s5h1432_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) printk(KERN_INFO " Enter s5h1432_attach(). attach success!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) state->current_modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) state->inversion = state->config->inversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) memcpy(&state->frontend.ops, &s5h1432_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) EXPORT_SYMBOL(s5h1432_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct dvb_frontend_ops s5h1432_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .name = "Samsung s5h1432 DVB-T Frontend",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .frequency_min_hz = 177 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .frequency_max_hz = 858 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .frequency_stepsize_hz = 166666,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .init = s5h1432_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .sleep = s5h1432_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .set_frontend = s5h1432_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .get_tune_settings = s5h1432_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .read_status = s5h1432_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .read_ber = s5h1432_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .read_signal_strength = s5h1432_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .read_snr = s5h1432_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .read_ucblocks = s5h1432_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .release = s5h1432_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_PARM_DESC(debug, "Enable verbose debug messages");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MODULE_DESCRIPTION("Samsung s5h1432 DVB-T Demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MODULE_AUTHOR("Bill Liu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags