^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Samsung S5H1420 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * PnpNetwork PN1010 QPSK Demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2005-8 Patrick Boettcher <pb@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "s5h1420.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "s5h1420_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TONE_FREQ 22000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct s5h1420_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) const struct s5h1420_config* config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct i2c_adapter tuner_i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 CON_1_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 postlocked:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 tunedfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum fe_code_rate fec_inner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* FIXME: ugly workaround for flexcop's incapable i2c-controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * it does not support repeated-start, workaround: write addr-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * and then read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 shadow[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct dvb_frontend_tune_settings* fesettings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_PARM_DESC(debug, "enable debugging");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define dprintk(x...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) printk(KERN_DEBUG "S5H1420: " x); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 b[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .addr = state->config->demod_address, .flags = 0, .buf = ®, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) b[0] = (reg - 1) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) b[1] = state->shadow[(reg - 1) & 0xff];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (state->config->repeated_start_workaround) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = i2c_transfer(state->i2c, msg, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (ret != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ret = i2c_transfer(state->i2c, &msg[1], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ret = i2c_transfer(state->i2c, &msg[2], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return b[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 buf[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* dprintk("wr(%02x): %02x %02x\n", state->config->demod_address, reg, data); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) err = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (err != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) state->shadow[reg] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int s5h1420_set_voltage(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum fe_sec_voltage voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dprintk("enter %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) switch(voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case SEC_VOLTAGE_13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) s5h1420_writereg(state, 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case SEC_VOLTAGE_18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case SEC_VOLTAGE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dprintk("leave %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int s5h1420_set_tone(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) enum fe_sec_tone_mode tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dprintk("enter %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) switch(tone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case SEC_TONE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) s5h1420_writereg(state, 0x3b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case SEC_TONE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) s5h1420_writereg(state, 0x3b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dprintk("leave %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct dvb_diseqc_master_cmd* cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dprintk("enter %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (cmd->msg_len > sizeof(cmd->msg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* setup for DISEQC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) val = s5h1420_readreg(state, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) s5h1420_writereg(state, 0x3b, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) msleep(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* write the DISEQC command bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) for(i=0; i< cmd->msg_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* kick off transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ((cmd->msg_len-1) << 4) | 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* wait for transmission to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) timeout = jiffies + ((100*HZ) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) while(time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!(s5h1420_readreg(state, 0x3b) & 0x08))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) result = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* restore original settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) s5h1420_writereg(state, 0x3b, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) msleep(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dprintk("leave %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int s5h1420_recv_slave_reply (struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct dvb_diseqc_slave_reply* reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* setup for DISEQC receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) val = s5h1420_readreg(state, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) msleep(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* wait for reception to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) timeout = jiffies + ((reply->timeout*HZ) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) while(time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) result = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* check error flag - FIXME: not sure what this does - docs do not describe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * beyond "error flag for diseqc receive data :( */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (s5h1420_readreg(state, 0x49)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* check length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (length > sizeof(reply->msg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) result = -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) reply->msg_len = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* extract data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) for(i=0; i< length; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) reply->msg[i] = s5h1420_readreg(state, 0x3d + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* restore original settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) s5h1420_writereg(state, 0x3b, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) msleep(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int s5h1420_send_burst(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) enum fe_sec_mini_cmd minicmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* setup for tone burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) val = s5h1420_readreg(state, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* set value for B position if requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (minicmd == SEC_MINI_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) msleep(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* start transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* wait for transmission to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) timeout = jiffies + ((100*HZ) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) while(time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!(s5h1420_readreg(state, 0x3b) & 0x08))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) result = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* restore original settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) s5h1420_writereg(state, 0x3b, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) msleep(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static enum fe_status s5h1420_get_status_bits(struct s5h1420_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) enum fe_status status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) val = s5h1420_readreg(state, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (val & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (val & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) val = s5h1420_readreg(state, 0x36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (val & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (val & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI|FE_HAS_SYNC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int s5h1420_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dprintk("enter %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (status == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* determine lock state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) *status = s5h1420_get_status_bits(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) the inversion, wait a bit and check again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (*status == (FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) val = s5h1420_readreg(state, Vit10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if ((val & 0x07) == 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (val & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) s5h1420_writereg(state, Vit09, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) s5h1420_writereg(state, Vit09, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* wait a bit then update lock status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mdelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) *status = s5h1420_get_status_bits(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* perform post lock setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if ((*status & FE_HAS_LOCK) && !state->postlocked) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* calculate the data rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 tmp = s5h1420_getsymbolrate(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) switch (s5h1420_readreg(state, Vit10) & 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case 0: tmp = (tmp * 2 * 1) / 2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case 1: tmp = (tmp * 2 * 2) / 3; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case 2: tmp = (tmp * 2 * 3) / 4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case 3: tmp = (tmp * 2 * 5) / 6; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case 4: tmp = (tmp * 2 * 6) / 7; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case 5: tmp = (tmp * 2 * 7) / 8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (tmp == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) printk(KERN_ERR "s5h1420: avoided division by 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) tmp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) tmp = state->fclk / tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* set the MPEG_CLK_INTL for the calculated data rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (tmp < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) val = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) else if (tmp < 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) val = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) else if (tmp < 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) val = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) else if (tmp < 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) val = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) else if (tmp < 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) val = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) else if (tmp < 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) val = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) else if (tmp < 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) val = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) val = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dprintk("for MPEG_CLK_INTL %d %x\n", tmp, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) s5h1420_writereg(state, FEC01, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) s5h1420_writereg(state, FEC01, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) s5h1420_writereg(state, FEC01, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Enable "MPEG_Out" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) val = s5h1420_readreg(state, Mpeg02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) s5h1420_writereg(state, Mpeg02, val | (1 << 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* kicker disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) val = s5h1420_readreg(state, QPSK01) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) s5h1420_writereg(state, QPSK01, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* DC freeze TODO it was never activated by default or it can stay activated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (s5h1420_getsymbolrate(state) >= 20000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) s5h1420_writereg(state, Loop04, 0x8a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) s5h1420_writereg(state, Loop05, 0x6a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) s5h1420_writereg(state, Loop04, 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) s5h1420_writereg(state, Loop05, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* post-lock processing has been done! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) state->postlocked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dprintk("leave %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int s5h1420_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) s5h1420_writereg(state, 0x46, 0x1d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mdelay(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int s5h1420_read_signal_strength(struct dvb_frontend* fe, u16* strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u8 val = s5h1420_readreg(state, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *strength = (u16) ((val << 8) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) s5h1420_writereg(state, 0x46, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mdelay(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void s5h1420_reset(struct s5h1420_state* state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) s5h1420_writereg (state, 0x01, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) s5h1420_writereg (state, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static void s5h1420_setsymbolrate(struct s5h1420_state* state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dprintk("enter %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) val = ((u64) p->symbol_rate / 1000ULL) * (1ULL<<24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (p->symbol_rate < 29000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) val *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) do_div(val, (state->fclk / 1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dprintk("symbol rate register: %06llx\n", (unsigned long long)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) v = s5h1420_readreg(state, Loop01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) s5h1420_writereg(state, Loop01, v & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) s5h1420_writereg(state, Tnco01, val >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) s5h1420_writereg(state, Tnco02, val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) s5h1420_writereg(state, Tnco03, val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) s5h1420_writereg(state, Loop01, v | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dprintk("leave %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return state->symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dprintk("enter %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * divide fclk by 1000000 to get the correct value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dprintk("phase rotator/freqoffset: %d %06x\n", freqoffset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) v = s5h1420_readreg(state, Loop01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) s5h1420_writereg(state, Loop01, v & 0xbf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) s5h1420_writereg(state, Pnco01, val >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) s5h1420_writereg(state, Pnco02, val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) s5h1420_writereg(state, Pnco03, val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) s5h1420_writereg(state, Loop01, v | 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dprintk("leave %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int s5h1420_getfreqoffset(struct s5h1420_state* state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) val = s5h1420_readreg(state, 0x0e) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) val |= s5h1420_readreg(state, 0x0f) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) val |= s5h1420_readreg(state, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (val & 0x800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) val |= 0xff000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * divide fclk by 1000000 to get the correct value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) val = (((-val) * (state->fclk/1000000)) / (1<<24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static void s5h1420_setfec_inversion(struct s5h1420_state* state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u8 inversion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u8 vit08, vit09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dprintk("enter %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (p->inversion == INVERSION_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) inversion = state->config->invert ? 0x08 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) else if (p->inversion == INVERSION_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) inversion = state->config->invert ? 0 : 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if ((p->fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) vit08 = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) vit09 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) switch (p->fec_inner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) vit08 = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) vit09 = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) vit08 = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) vit09 = 0x11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) vit08 = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) vit09 = 0x12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) vit08 = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) vit09 = 0x13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case FEC_6_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) vit08 = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) vit09 = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) vit08 = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) vit09 = 0x15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) vit09 |= inversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dprintk("fec: %02x %02x\n", vit08, vit09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) s5h1420_writereg(state, Vit08, vit08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) s5h1420_writereg(state, Vit09, vit09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dprintk("leave %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static enum fe_code_rate s5h1420_getfec(struct s5h1420_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) switch(s5h1420_readreg(state, 0x32) & 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return FEC_6_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static enum fe_spectral_inversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) s5h1420_getinversion(struct s5h1420_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (s5h1420_readreg(state, 0x32) & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static int s5h1420_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int frequency_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct dvb_frontend_tune_settings fesettings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dprintk("enter %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* check if we should do a fast-tune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) s5h1420_get_tune_settings(fe, &fesettings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) frequency_delta = p->frequency - state->tunedfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if ((frequency_delta > -fesettings.max_drift) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) (frequency_delta < fesettings.max_drift) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) (frequency_delta != 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) (state->fec_inner == p->fec_inner) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) (state->symbol_rate == p->symbol_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (fe->ops.tuner_ops.get_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) fe->ops.tuner_ops.get_frequency(fe, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) s5h1420_setfreqoffset(state, p->frequency - tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) s5h1420_setfreqoffset(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dprintk("simple tune\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dprintk("tuning demod\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* first of all, software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) s5h1420_reset(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* set s5h1420 fclk PLL according to desired symbol rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (p->symbol_rate > 33000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) state->fclk = 80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) else if (p->symbol_rate > 28500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) state->fclk = 59000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) else if (p->symbol_rate > 25000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) state->fclk = 86000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) else if (p->symbol_rate > 1900000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) state->fclk = 88000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) state->fclk = 44000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) s5h1420_writereg(state, PLL02, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* TODO DC offset removal, config parameter ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (p->symbol_rate > 29000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) s5h1420_writereg(state, QPSK01, 0xae | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) s5h1420_writereg(state, QPSK01, 0xac | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* set misc registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) s5h1420_writereg(state, CON_1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) s5h1420_writereg(state, QPSK02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) s5h1420_writereg(state, Pre01, 0xb0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) s5h1420_writereg(state, Loop01, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (p->symbol_rate > 20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) s5h1420_writereg(state, Loop04, 0x79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) s5h1420_writereg(state, Loop04, 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) s5h1420_writereg(state, Loop05, 0x6b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (p->symbol_rate >= 8000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) else if (p->symbol_rate >= 4000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) s5h1420_writereg(state, Sync01, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) s5h1420_writereg(state, DiS03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* set tuner PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) s5h1420_setfreqoffset(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* set the reset of the parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) s5h1420_setsymbolrate(state, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) s5h1420_setfec_inversion(state, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* start QPSK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) state->fec_inner = p->fec_inner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) state->symbol_rate = p->symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) state->postlocked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) state->tunedfreq = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dprintk("leave %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static int s5h1420_get_frontend(struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) p->inversion = s5h1420_getinversion(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) p->symbol_rate = s5h1420_getsymbolrate(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) p->fec_inner = s5h1420_getfec(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct dvb_frontend_tune_settings* fesettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (p->symbol_rate > 20000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) fesettings->min_delay_ms = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) fesettings->step_size = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) fesettings->max_drift = 8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) } else if (p->symbol_rate > 12000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) fesettings->min_delay_ms = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) fesettings->step_size = 1500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) fesettings->max_drift = 9000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) } else if (p->symbol_rate > 8000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) fesettings->min_delay_ms = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) fesettings->step_size = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) fesettings->max_drift = 8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) } else if (p->symbol_rate > 4000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) fesettings->min_delay_ms = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) fesettings->step_size = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) fesettings->max_drift = 7000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) } else if (p->symbol_rate > 2000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) fesettings->min_delay_ms = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) fesettings->step_size = (p->symbol_rate / 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) fesettings->max_drift = 14 * fesettings->step_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) fesettings->min_delay_ms = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) fesettings->step_size = (p->symbol_rate / 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) fesettings->max_drift = 18 * fesettings->step_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int s5h1420_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static int s5h1420_init (struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* disable power down and do reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) state->CON_1_val = state->config->serial_mpeg << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) s5h1420_writereg(state, 0x02, state->CON_1_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) s5h1420_reset(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int s5h1420_sleep(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) state->CON_1_val = 0x12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return s5h1420_writereg(state, 0x02, state->CON_1_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static void s5h1420_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct s5h1420_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) i2c_del_adapter(&state->tuner_i2c_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static u32 s5h1420_tuner_i2c_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return I2C_FUNC_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static int s5h1420_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct s5h1420_state *state = i2c_get_adapdata(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct i2c_msg m[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (1 + num > ARRAY_SIZE(m)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) "%s: i2c xfer: num=%d is too big!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) KBUILD_MODNAME, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) memset(m, 0, sizeof(struct i2c_msg) * (1 + num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) m[0].addr = state->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) m[0].buf = tx_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) m[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return i2c_transfer(state->i2c, m, 1 + num) == 1 + num ? num : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static const struct i2c_algorithm s5h1420_tuner_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .master_xfer = s5h1420_tuner_i2c_tuner_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .functionality = s5h1420_tuner_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct s5h1420_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return &state->tuner_i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) EXPORT_SYMBOL(s5h1420_get_tuner_i2c_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static const struct dvb_frontend_ops s5h1420_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) state->postlocked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) state->fclk = 88000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) state->tunedfreq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) state->fec_inner = FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) state->symbol_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* check if the demod is there + identify it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) i = s5h1420_readreg(state, ID01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (i != 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) memset(state->shadow, 0xff, sizeof(state->shadow));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) for (i = 0; i < 0x50; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) state->shadow[i] = s5h1420_readreg(state, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* create tuner i2c adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) strscpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) sizeof(state->tuner_i2c_adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) state->tuner_i2c_adapter.algo = &s5h1420_tuner_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) state->tuner_i2c_adapter.algo_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) i2c_set_adapdata(&state->tuner_i2c_adapter, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) printk(KERN_ERR "S5H1420/PN1010: tuner i2c bus could not be initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) EXPORT_SYMBOL(s5h1420_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static const struct dvb_frontend_ops s5h1420_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .delsys = { SYS_DVBS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .name = "Samsung S5H1420/PnpNetwork PN1010 DVB-S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .frequency_min_hz = 950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .frequency_stepsize_hz = 125 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .frequency_tolerance_hz = 29500 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .symbol_rate_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .symbol_rate_max = 45000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* .symbol_rate_tolerance = ???,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) FE_CAN_QPSK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .release = s5h1420_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .init = s5h1420_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .sleep = s5h1420_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .i2c_gate_ctrl = s5h1420_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .set_frontend = s5h1420_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .get_frontend = s5h1420_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .get_tune_settings = s5h1420_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .read_status = s5h1420_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .read_ber = s5h1420_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .read_signal_strength = s5h1420_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .read_ucblocks = s5h1420_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .diseqc_send_master_cmd = s5h1420_send_master_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .diseqc_recv_slave_reply = s5h1420_recv_slave_reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .diseqc_send_burst = s5h1420_send_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .set_tone = s5h1420_set_tone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .set_voltage = s5h1420_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) MODULE_DESCRIPTION("Samsung S5H1420/PnpNetwork PN1010 DVB-S Demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) MODULE_AUTHOR("Andrew de Quincey, Patrick Boettcher");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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