^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Realtek RTL2832 DVB-T demodulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "rtl2832_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define REG_MASK(b) (BIT(b + 1) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static const struct rtl2832_reg_entry registers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) [DVBT_SOFT_RST] = {0x101, 2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) [DVBT_IIC_REPEAT] = {0x101, 3, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) [DVBT_TR_WAIT_MIN_8K] = {0x188, 11, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) [DVBT_EN_BK_TRK] = {0x1a6, 7, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) [DVBT_AD_EN_REG] = {0x008, 7, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) [DVBT_AD_EN_REG1] = {0x008, 6, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) [DVBT_EN_BBIN] = {0x1b1, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) [DVBT_MGD_THD0] = {0x195, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) [DVBT_MGD_THD1] = {0x196, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) [DVBT_MGD_THD2] = {0x197, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) [DVBT_MGD_THD3] = {0x198, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) [DVBT_MGD_THD4] = {0x199, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) [DVBT_MGD_THD5] = {0x19a, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) [DVBT_MGD_THD6] = {0x19b, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) [DVBT_MGD_THD7] = {0x19c, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) [DVBT_EN_CACQ_NOTCH] = {0x161, 4, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) [DVBT_AD_AV_REF] = {0x009, 6, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) [DVBT_REG_PI] = {0x00a, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) [DVBT_PIP_ON] = {0x021, 3, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) [DVBT_SCALE1_B92] = {0x292, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) [DVBT_SCALE1_B93] = {0x293, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) [DVBT_SCALE1_BA7] = {0x2a7, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) [DVBT_SCALE1_BA9] = {0x2a9, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [DVBT_SCALE1_BAA] = {0x2aa, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [DVBT_SCALE1_BAB] = {0x2ab, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [DVBT_SCALE1_BAC] = {0x2ac, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [DVBT_SCALE1_BB0] = {0x2b0, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [DVBT_SCALE1_BB1] = {0x2b1, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) [DVBT_KB_P1] = {0x164, 3, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) [DVBT_KB_P2] = {0x164, 6, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) [DVBT_KB_P3] = {0x165, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) [DVBT_OPT_ADC_IQ] = {0x006, 5, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) [DVBT_AD_AVI] = {0x009, 1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) [DVBT_AD_AVQ] = {0x009, 3, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) [DVBT_K1_CR_STEP12] = {0x2ad, 9, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) [DVBT_TRK_KS_P2] = {0x16f, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) [DVBT_TRK_KS_I2] = {0x170, 5, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) [DVBT_TR_THD_SET2] = {0x172, 3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) [DVBT_TRK_KC_P2] = {0x173, 5, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) [DVBT_TRK_KC_I2] = {0x175, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) [DVBT_CR_THD_SET2] = {0x176, 7, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) [DVBT_PSET_IFFREQ] = {0x119, 21, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [DVBT_SPEC_INV] = {0x115, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [DVBT_RSAMP_RATIO] = {0x19f, 27, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) [DVBT_CFREQ_OFF_RATIO] = {0x19d, 23, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [DVBT_FSM_STAGE] = {0x351, 6, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) [DVBT_RX_CONSTEL] = {0x33c, 3, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) [DVBT_RX_HIER] = {0x33c, 6, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) [DVBT_RX_C_RATE_LP] = {0x33d, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [DVBT_RX_C_RATE_HP] = {0x33d, 5, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [DVBT_GI_IDX] = {0x351, 1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [DVBT_FFT_MODE_IDX] = {0x351, 2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [DVBT_RSD_BER_EST] = {0x34e, 15, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [DVBT_CE_EST_EVM] = {0x40c, 15, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [DVBT_RF_AGC_VAL] = {0x35b, 13, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [DVBT_IF_AGC_VAL] = {0x359, 13, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [DVBT_DAGC_VAL] = {0x305, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [DVBT_SFREQ_OFF] = {0x318, 13, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [DVBT_CFREQ_OFF] = {0x35f, 17, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [DVBT_POLAR_RF_AGC] = {0x00e, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [DVBT_POLAR_IF_AGC] = {0x00e, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [DVBT_AAGC_HOLD] = {0x104, 5, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [DVBT_EN_RF_AGC] = {0x104, 6, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) [DVBT_EN_IF_AGC] = {0x104, 7, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [DVBT_IF_AGC_MIN] = {0x108, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [DVBT_IF_AGC_MAX] = {0x109, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [DVBT_RF_AGC_MIN] = {0x10a, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) [DVBT_RF_AGC_MAX] = {0x10b, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [DVBT_IF_AGC_MAN] = {0x10c, 6, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [DVBT_IF_AGC_MAN_VAL] = {0x10c, 13, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [DVBT_RF_AGC_MAN] = {0x10e, 6, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [DVBT_RF_AGC_MAN_VAL] = {0x10e, 13, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [DVBT_DAGC_TRG_VAL] = {0x112, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [DVBT_AGC_TARG_VAL_0] = {0x102, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [DVBT_AGC_TARG_VAL_8_1] = {0x103, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [DVBT_AAGC_LOOP_GAIN] = {0x1c7, 5, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [DVBT_LOOP_GAIN2_3_0] = {0x104, 4, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [DVBT_LOOP_GAIN2_4] = {0x105, 7, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [DVBT_LOOP_GAIN3] = {0x1c8, 4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [DVBT_VTOP1] = {0x106, 5, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [DVBT_VTOP2] = {0x1c9, 5, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [DVBT_VTOP3] = {0x1ca, 5, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [DVBT_KRF1] = {0x1cb, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [DVBT_KRF2] = {0x107, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [DVBT_KRF3] = {0x1cd, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [DVBT_KRF4] = {0x1ce, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [DVBT_EN_GI_PGA] = {0x1e5, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [DVBT_THD_LOCK_UP] = {0x1d9, 8, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [DVBT_THD_LOCK_DW] = {0x1db, 8, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [DVBT_THD_UP1] = {0x1dd, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [DVBT_THD_DW1] = {0x1de, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [DVBT_INTER_CNT_LEN] = {0x1d8, 3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [DVBT_GI_PGA_STATE] = {0x1e6, 3, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [DVBT_EN_AGC_PGA] = {0x1d7, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [DVBT_CKOUTPAR] = {0x17b, 5, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [DVBT_CKOUT_PWR] = {0x17b, 6, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [DVBT_SYNC_DUR] = {0x17b, 7, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [DVBT_ERR_DUR] = {0x17c, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [DVBT_SYNC_LVL] = {0x17c, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [DVBT_ERR_LVL] = {0x17c, 2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [DVBT_VAL_LVL] = {0x17c, 3, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [DVBT_SERIAL] = {0x17c, 4, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [DVBT_SER_LSB] = {0x17c, 5, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [DVBT_CDIV_PH0] = {0x17d, 3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [DVBT_CDIV_PH1] = {0x17d, 7, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [DVBT_MPEG_IO_OPT_2_2] = {0x006, 7, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [DVBT_MPEG_IO_OPT_1_0] = {0x007, 7, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [DVBT_CKOUTPAR_PIP] = {0x0b7, 4, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [DVBT_CKOUT_PWR_PIP] = {0x0b7, 3, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [DVBT_SYNC_LVL_PIP] = {0x0b7, 2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [DVBT_ERR_LVL_PIP] = {0x0b7, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [DVBT_VAL_LVL_PIP] = {0x0b7, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [DVBT_CKOUTPAR_PID] = {0x0b9, 4, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [DVBT_CKOUT_PWR_PID] = {0x0b9, 3, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [DVBT_SYNC_LVL_PID] = {0x0b9, 2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [DVBT_ERR_LVL_PID] = {0x0b9, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [DVBT_VAL_LVL_PID] = {0x0b9, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [DVBT_SM_PASS] = {0x193, 11, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [DVBT_AD7_SETTING] = {0x011, 15, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [DVBT_RSSI_R] = {0x301, 6, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [DVBT_ACI_DET_IND] = {0x312, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [DVBT_REG_MON] = {0x00d, 1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [DVBT_REG_MONSEL] = {0x00d, 2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [DVBT_REG_GPE] = {0x00d, 7, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [DVBT_REG_GPO] = {0x010, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [DVBT_REG_4MSEL] = {0x013, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u16 reg_start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 msb, lsb, reading[4], len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 reading_tmp, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) reg_start_addr = registers[reg].start_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) msb = registers[reg].msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) lsb = registers[reg].lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) len = (msb >> 3) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mask = REG_MASK(msb - lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = regmap_bulk_read(dev->regmap, reg_start_addr, reading, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) reading_tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) reading_tmp |= reading[i] << ((len - 1 - i) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *val = (reading_tmp >> lsb) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u16 reg_start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 msb, lsb, reading[4], writing[4], len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 reading_tmp, writing_tmp, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) reg_start_addr = registers[reg].start_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) msb = registers[reg].msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) lsb = registers[reg].lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) len = (msb >> 3) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mask = REG_MASK(msb - lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = regmap_bulk_read(dev->regmap, reg_start_addr, reading, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) reading_tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) reading_tmp |= reading[i] << ((len - 1 - i) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) writing_tmp = reading_tmp & ~(mask << lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writing_tmp |= ((val & mask) << lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = regmap_bulk_write(dev->regmap, reg_start_addr, writing, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct rtl2832_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u64 pset_iffreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * / CrystalFreqHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pset_iffreq = if_freq % dev->pdata->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pset_iffreq *= 0x400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pset_iffreq = -pset_iffreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pset_iffreq = pset_iffreq & 0x3fffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if_freq, (unsigned)pset_iffreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int rtl2832_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct rtl2832_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) const struct rtl2832_reg_value *init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int i, ret, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* initialization values for the demodulator registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct rtl2832_reg_value rtl2832_initial_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {DVBT_AD_EN_REG, 0x1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {DVBT_AD_EN_REG1, 0x1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {DVBT_RSD_BER_FAIL_VAL, 0x2800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {DVBT_MGD_THD0, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {DVBT_MGD_THD1, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {DVBT_MGD_THD2, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {DVBT_MGD_THD3, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {DVBT_MGD_THD4, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {DVBT_MGD_THD5, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {DVBT_MGD_THD6, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {DVBT_MGD_THD7, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {DVBT_EN_BK_TRK, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {DVBT_EN_CACQ_NOTCH, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {DVBT_AD_AV_REF, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {DVBT_REG_PI, 0x6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {DVBT_PIP_ON, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {DVBT_CDIV_PH0, 0x8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {DVBT_CDIV_PH1, 0x8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {DVBT_SCALE1_B92, 0x4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {DVBT_SCALE1_B93, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {DVBT_SCALE1_BA7, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {DVBT_SCALE1_BA9, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {DVBT_SCALE1_BAA, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {DVBT_SCALE1_BAB, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {DVBT_SCALE1_BAC, 0xd4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {DVBT_SCALE1_BB0, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {DVBT_SCALE1_BB1, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {DVBT_KB_P1, 0x1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {DVBT_KB_P2, 0x4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {DVBT_KB_P3, 0x7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {DVBT_K1_CR_STEP12, 0xa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {DVBT_REG_GPE, 0x1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {DVBT_SERIAL, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {DVBT_CDIV_PH0, 0x9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {DVBT_CDIV_PH1, 0x9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {DVBT_MPEG_IO_OPT_2_2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {DVBT_MPEG_IO_OPT_1_0, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {DVBT_TRK_KS_P2, 0x4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {DVBT_TRK_KS_I2, 0x7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {DVBT_TR_THD_SET2, 0x6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {DVBT_TRK_KC_I2, 0x5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {DVBT_CR_THD_SET2, 0x1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) rtl2832_initial_regs[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* load tuner specific settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_dbg(&client->dev, "load settings for tuner=%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev->pdata->tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) switch (dev->pdata->tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case RTL2832_TUNER_FC2580:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) len = ARRAY_SIZE(rtl2832_tuner_init_fc2580);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) init = rtl2832_tuner_init_fc2580;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case RTL2832_TUNER_FC0012:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case RTL2832_TUNER_FC0013:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) init = rtl2832_tuner_init_fc0012;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case RTL2832_TUNER_TUA9001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) init = rtl2832_tuner_init_tua9001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case RTL2832_TUNER_E4000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) init = rtl2832_tuner_init_e4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case RTL2832_TUNER_R820T:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case RTL2832_TUNER_R828D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) init = rtl2832_tuner_init_r820t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case RTL2832_TUNER_SI2157:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) len = ARRAY_SIZE(rtl2832_tuner_init_si2157);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) init = rtl2832_tuner_init_si2157;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* init stats here in order signal app which stats are supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) c->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) c->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) c->post_bit_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) c->post_bit_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev->sleeping = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int rtl2832_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct rtl2832_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev->sleeping = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev->fe_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct dvb_frontend_tune_settings *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct rtl2832_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) s->min_delay_ms = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int rtl2832_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct rtl2832_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int ret, i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u64 bw_mode, num, num2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 resamp_ratio, cfreq_off_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static u8 bw_params[3][32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* 6 MHz bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0x19, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* 7 MHz bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 0x19, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* 8 MHz bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 0x19, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) c->frequency, c->bandwidth_hz, c->inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* program tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (fe->ops.tuner_ops.set_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* If the frontend has get_if_frequency(), use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (fe->ops.tuner_ops.get_if_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = rtl2832_set_if(fe, if_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) switch (c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) bw_mode = 48000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) i = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) bw_mode = 56000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bw_mode = 64000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_err(&client->dev, "invalid bandwidth_hz %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) c->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) for (j = 0; j < sizeof(bw_params[0]); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = regmap_bulk_write(dev->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 0x11c + j, &bw_params[i][j], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* calculate and set resample ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * / ConstWithBandwidthMode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) num = dev->pdata->clk * 7ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) num *= 0x400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) num = div_u64(num, bw_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) resamp_ratio = num & 0x3ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* calculate and set cfreq off ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * / (CrystalFreqHz * 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) num = bw_mode << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) num2 = dev->pdata->clk * 7ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) num = div_u64(num, num2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) num = -num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) cfreq_off_ratio = num & 0xfffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int rtl2832_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct dtv_frontend_properties *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct rtl2832_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (dev->sleeping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = regmap_bulk_read(dev->regmap, 0x33c, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = regmap_bulk_read(dev->regmap, 0x351, &buf[2], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) switch ((buf[0] >> 2) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) c->modulation = QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) c->modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) c->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) switch ((buf[2] >> 2) & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) c->transmission_mode = TRANSMISSION_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) c->transmission_mode = TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) switch ((buf[2] >> 0) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) c->guard_interval = GUARD_INTERVAL_1_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) c->guard_interval = GUARD_INTERVAL_1_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) c->guard_interval = GUARD_INTERVAL_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) c->guard_interval = GUARD_INTERVAL_1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) switch ((buf[0] >> 4) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) c->hierarchy = HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) c->hierarchy = HIERARCHY_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) c->hierarchy = HIERARCHY_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) c->hierarchy = HIERARCHY_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) switch ((buf[1] >> 3) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) c->code_rate_HP = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) c->code_rate_HP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) c->code_rate_HP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) c->code_rate_HP = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) c->code_rate_HP = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) switch ((buf[1] >> 0) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) c->code_rate_LP = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) c->code_rate_LP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) c->code_rate_LP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) c->code_rate_LP = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) c->code_rate_LP = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int rtl2832_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct rtl2832_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u8 u8tmp, buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u16 u16tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (dev->sleeping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (tmp == 11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) } else if (tmp == 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev->fe_status = *status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* signal strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (dev->fe_status & FE_HAS_SIGNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* read digital AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ret = regmap_bulk_read(dev->regmap, 0x305, &u8tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dev_dbg(&client->dev, "digital agc=%02x", u8tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u8tmp = ~u8tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u16tmp = u8tmp << 8 | u8tmp << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) c->strength.stat[0].scale = FE_SCALE_RELATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) c->strength.stat[0].uvalue = u16tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* CNR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (dev->fe_status & FE_HAS_VITERBI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) unsigned hierarchy, constellation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define CONSTELLATION_NUM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define HIERARCHY_NUM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {85387325, 85387325, 85387325, 85387325},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {86676178, 86676178, 87167949, 87795660},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {87659938, 87659938, 87885178, 88241743},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = regmap_bulk_read(dev->regmap, 0x33c, &u8tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (constellation > CONSTELLATION_NUM - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (hierarchy > HIERARCHY_NUM - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ret = regmap_bulk_read(dev->regmap, 0x40c, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u16tmp = buf[0] << 8 | buf[1] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (u16tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) tmp = (constant[constellation][hierarchy] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) intlog10(u16tmp)) / ((1 << 24) / 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev_dbg(&client->dev, "cnr raw=%u\n", u16tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) c->cnr.stat[0].svalue = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* BER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (dev->fe_status & FE_HAS_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ret = regmap_bulk_read(dev->regmap, 0x34e, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u16tmp = buf[0] << 8 | buf[1] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dev->post_bit_error += u16tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev->post_bit_count += 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_dbg(&client->dev, "ber errors=%u total=1000000\n", u16tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* report SNR in resolution of 0.1 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) *snr = div_s64(c->cnr.stat[0].svalue, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) *snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct rtl2832_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) *ber = (dev->post_bit_error - dev->post_bit_error_prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev->post_bit_error_prev = dev->post_bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * I2C gate/mux/repeater logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * is delayed here a little bit in order to see if there is sequence of I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * messages sent to same I2C bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static void rtl2832_i2c_gate_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* close gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int rtl2832_select(struct i2c_mux_core *muxc, u32 chan_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct rtl2832_dev *dev = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* terminate possible gate closing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) cancel_delayed_work(&dev->i2c_gate_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* open gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static int rtl2832_deselect(struct i2c_mux_core *muxc, u32 chan_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct rtl2832_dev *dev = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static const struct dvb_frontend_ops rtl2832_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .name = "Realtek RTL2832 (DVB-T)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .frequency_min_hz = 174 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .frequency_max_hz = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .frequency_stepsize_hz = 166667,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .caps = FE_CAN_FEC_1_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) FE_CAN_FEC_2_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) FE_CAN_FEC_5_6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) FE_CAN_FEC_7_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) FE_CAN_QPSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) FE_CAN_QAM_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) FE_CAN_TRANSMISSION_MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) FE_CAN_GUARD_INTERVAL_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) FE_CAN_HIERARCHY_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) FE_CAN_RECOVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) FE_CAN_MUTE_TS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .init = rtl2832_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .sleep = rtl2832_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .get_tune_settings = rtl2832_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .set_frontend = rtl2832_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .get_frontend = rtl2832_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .read_status = rtl2832_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .read_snr = rtl2832_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .read_ber = rtl2832_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static bool rtl2832_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) case 0x305:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) case 0x33c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) case 0x34e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) case 0x351:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) case 0x40c ... 0x40d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct rtl2832_dev *dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return &dev->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static struct i2c_adapter *rtl2832_get_i2c_adapter(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct rtl2832_dev *dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return dev->muxc->adapter[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int rtl2832_slave_ts_ctrl(struct i2c_client *client, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct rtl2832_dev *dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev_dbg(&client->dev, "enable=%d\n", enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ret = regmap_bulk_write(dev->regmap, 0x10c, "\x5f\xff", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ret = regmap_bulk_write(dev->regmap, 0x0bc, "\x18", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ret = regmap_bulk_write(dev->regmap, 0x192, "\x7f\xf7\xff", 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ret = regmap_bulk_write(dev->regmap, 0x192, "\x00\x0f\xff", 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) ret = regmap_bulk_write(dev->regmap, 0x0bc, "\x08", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ret = regmap_bulk_write(dev->regmap, 0x10c, "\x00\x00", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) dev->slave_ts = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static int rtl2832_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct rtl2832_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) u8 u8tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dev_dbg(&client->dev, "onoff=%d, slave_ts=%d\n", onoff, dev->slave_ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* enable / disable PID filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) u8tmp = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) u8tmp = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (dev->slave_ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ret = regmap_update_bits(dev->regmap, 0x021, 0xc0, u8tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = regmap_update_bits(dev->regmap, 0x061, 0xc0, u8tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static int rtl2832_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct rtl2832_dev *dev = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d slave_ts=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) index, pid, onoff, dev->slave_ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /* skip invalid PIDs (0x2000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (pid > 0x1fff || index > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) set_bit(index, &dev->filters);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) clear_bit(index, &dev->filters);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* enable / disable PIDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) buf[0] = (dev->filters >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) buf[1] = (dev->filters >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) buf[2] = (dev->filters >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) buf[3] = (dev->filters >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (dev->slave_ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ret = regmap_bulk_write(dev->regmap, 0x022, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ret = regmap_bulk_write(dev->regmap, 0x062, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* add PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) buf[0] = (pid >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) buf[1] = (pid >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (dev->slave_ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ret = regmap_bulk_write(dev->regmap, 0x026 + 2 * index, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ret = regmap_bulk_write(dev->regmap, 0x066 + 2 * index, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int rtl2832_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct rtl2832_platform_data *pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct i2c_adapter *i2c = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct rtl2832_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static const struct regmap_range_cfg regmap_range_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .selector_reg = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .selector_mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .selector_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .window_start = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .window_len = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .range_min = 0 * 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .range_max = 5 * 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) i2c_set_clientdata(client, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dev->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev->pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) dev->sleeping = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* create regmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) dev->regmap_config.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dev->regmap_config.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) dev->regmap_config.volatile_reg = rtl2832_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) dev->regmap_config.max_register = 5 * 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dev->regmap_config.ranges = regmap_range_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dev->regmap_config.num_ranges = ARRAY_SIZE(regmap_range_cfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) dev->regmap_config.cache_type = REGCACHE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) dev->regmap = regmap_init_i2c(client, &dev->regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (IS_ERR(dev->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ret = PTR_ERR(dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ret = regmap_bulk_read(dev->regmap, 0x000, &tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* create muxed i2c adapter for demod tuner bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev->muxc = i2c_mux_alloc(i2c, &i2c->dev, 1, 0, I2C_MUX_LOCKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) rtl2832_select, rtl2832_deselect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!dev->muxc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) dev->muxc->priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) dev->fe.demodulator_priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* setup callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) pdata->get_i2c_adapter = rtl2832_get_i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) pdata->slave_ts_ctrl = rtl2832_slave_ts_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) pdata->pid_filter = rtl2832_pid_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) pdata->pid_filter_ctrl = rtl2832_pid_filter_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) pdata->regmap = dev->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) err_regmap_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) regmap_exit(dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) err_kfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static int rtl2832_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct rtl2832_dev *dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) cancel_delayed_work_sync(&dev->i2c_gate_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) i2c_mux_del_adapters(dev->muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) regmap_exit(dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static const struct i2c_device_id rtl2832_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {"rtl2832", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static struct i2c_driver rtl2832_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .name = "rtl2832",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .probe = rtl2832_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .remove = rtl2832_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .id_table = rtl2832_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) module_i2c_driver(rtl2832_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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