^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support for OR51211 (pcHDTV HD-2000) - VSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005 Kirk Lapray <kirk_lapray@bigfoot.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on code from Jack Kelliher (kelliher@xmission.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2002 & pcHDTV, inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This driver needs external firmware. Please use the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * "<kerneldir>/scripts/get_dvb_firmware or51211" to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * download/extract it, and then copy it to /usr/lib/hotplug/firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * or /lib/firmware (depending on configuration of firmware hotplug).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OR51211_DEFAULT_FIRMWARE "dvb-fe-or51211.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/dvb_math.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "or51211.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) do { if (debug) pr_debug(args); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static u8 run_buf[] = {0x7f,0x01};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static u8 cmd_buf[] = {0x04,0x01,0x50,0x80,0x06}; // ATSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct or51211_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) const struct or51211_config* config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct bt878* bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Demodulator private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 initialized:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 snr; /* Result of last SNR calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Tuner private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 current_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int i2c_writebytes (struct or51211_state* state, u8 reg, const u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) msg.addr = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) msg.len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) msg.buf = (u8 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pr_warn("error (addr %02x, err == %i)\n", reg, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int i2c_readbytes(struct or51211_state *state, u8 reg, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) msg.addr = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) msg.flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) msg.len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pr_warn("error (addr %02x, err == %i)\n", reg, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int or51211_load_firmware (struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct or51211_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 tudata[585];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dprintk("Firmware is %zu bytes\n", fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Get eprom data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tudata[0] = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (i2c_writebytes(state,0x50,tudata,1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pr_warn("error eprom addr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (i2c_readbytes(state,0x50,&tudata[145],192)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_warn("error eprom\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Create firmware buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) for (i = 0; i < 145; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) tudata[i] = fw->data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) for (i = 0; i < 248; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) tudata[i+337] = fw->data[145+i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) state->config->reset(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (i2c_writebytes(state,state->config->demod_address,tudata,585)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pr_warn("error 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (i2c_writebytes(state,state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) &fw->data[393],8125)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pr_warn("error 2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (i2c_writebytes(state,state->config->demod_address,run_buf,2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pr_warn("error 3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Wait at least 5 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (i2c_writebytes(state,state->config->demod_address,run_buf,2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pr_warn("error 4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pr_info("Done.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int or51211_setmode(struct dvb_frontend* fe, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct or51211_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 rec_buf[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) state->config->setmode(fe, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (i2c_writebytes(state,state->config->demod_address,run_buf,2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pr_warn("error 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Wait at least 5 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (i2c_writebytes(state,state->config->demod_address,run_buf,2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pr_warn("error 2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Set operation mode in Receiver 1 register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * type 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * data 0x50h Automatic sets receiver channel conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Automatic NTSC rejection filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Enable MPEG serial data output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * MPEG2tr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * High tuner phase noise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * normal +/-150kHz Carrier acquisition range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (i2c_writebytes(state,state->config->demod_address,cmd_buf,3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pr_warn("error 3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rec_buf[0] = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rec_buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) rec_buf[2] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) rec_buf[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (i2c_writebytes(state,state->config->demod_address,rec_buf,3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pr_warn("error 5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) msleep(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (i2c_readbytes(state,state->config->demod_address,&rec_buf[10],2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pr_warn("error 6\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dprintk("rec status %02x %02x\n", rec_buf[10], rec_buf[11]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int or51211_set_parameters(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct or51211_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Change only if we are actually changing the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (state->current_frequency != p->frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Set to ATSC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) or51211_setmode(fe,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Update current frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) state->current_frequency = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int or51211_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct or51211_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned char rec_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned char snd_buf[] = {0x04,0x00,0x03,0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Receiver Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (i2c_writebytes(state,state->config->demod_address,snd_buf,3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pr_warn("write error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) msleep(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (i2c_readbytes(state,state->config->demod_address,rec_buf,2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pr_warn("read error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dprintk("%x %x\n", rec_buf[0], rec_buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (rec_buf[0] & 0x01) { /* Receiver Lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) *status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Calculate SNR estimation (scaled by 2^24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 8-VSB SNR equation from Oren datasheets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) For 8-VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) SNR[dB] = 10 * log10(219037.9454 / MSE^2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) We re-write the snr equation as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SNR * 2^24 = 10*(c - 2*intlog10(MSE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) Where for 8-VSB, c = log10(219037.9454) * 2^24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static u32 calculate_snr(u32 mse, u32 c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (mse == 0) /* No signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) mse = 2*intlog10(mse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (mse > c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Negative SNR, which is possible, but realisticly the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) demod will lose lock before the signal gets this bad. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) API only allows for unsigned values, so just return 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 10*(c - mse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int or51211_read_snr(struct dvb_frontend* fe, u16* snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct or51211_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u8 rec_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 snd_buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* SNR after Equalizer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) snd_buf[0] = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) snd_buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) snd_buf[2] = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (i2c_writebytes(state,state->config->demod_address,snd_buf,3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pr_warn("error writing snr reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (i2c_readbytes(state,state->config->demod_address,rec_buf,2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pr_warn("read_status read error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) state->snr = calculate_snr(rec_buf[0], 89599047);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *snr = (state->snr) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dprintk("noise = 0x%02x, snr = %d.%02d dB\n", rec_buf[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) state->snr >> 24, (((state->snr>>8) & 0xffff) * 100) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int or51211_read_signal_strength(struct dvb_frontend* fe, u16* strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Calculate Strength from SNR up to 35dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Even though the SNR can go higher than 35dB, there is some comfort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* factor in having a range of strong signals that can show at 100% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct or51211_state* state = (struct or51211_state*)fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u16 snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = fe->ops.read_snr(fe, &snr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* scale the range 0 - 35*2^24 into 0 - 65535 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (state->snr >= 8960 * 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *strength = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *strength = state->snr / 8960;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int or51211_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) *ber = -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int or51211_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *ucblocks = -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int or51211_sleep(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int or51211_init(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct or51211_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) const struct or51211_config* config = state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) const struct firmware* fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned char get_ver_buf[] = {0x04,0x00,0x30,0x00,0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned char rec_buf[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int ret,i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!state->initialized) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Request the firmware, this will block until it uploads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pr_info("Waiting for firmware upload (%s)...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) OR51211_DEFAULT_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = config->request_firmware(fe, &fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) OR51211_DEFAULT_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pr_info("Got Hotplug firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pr_warn("No firmware uploaded (timeout or file not found?)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = or51211_load_firmware(fe, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pr_warn("Writing firmware to device failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) pr_info("Firmware upload complete.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Set operation mode in Receiver 1 register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * type 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * data 0x50h Automatic sets receiver channel conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * Automatic NTSC rejection filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * Enable MPEG serial data output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * MPEG2tr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * High tuner phase noise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * normal +/-150kHz Carrier acquisition range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (i2c_writebytes(state,state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) cmd_buf,3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pr_warn("Load DVR Error 5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Read back ucode version to besure we loaded correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* and are really up and running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) rec_buf[0] = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) rec_buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) rec_buf[2] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) rec_buf[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (i2c_writebytes(state,state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) rec_buf,3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pr_warn("Load DVR Error A\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) msleep(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (i2c_readbytes(state,state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) &rec_buf[10],2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pr_warn("Load DVR Error B\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) rec_buf[0] = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) rec_buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) rec_buf[2] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) rec_buf[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (i2c_writebytes(state,state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) rec_buf,3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pr_warn("Load DVR Error C\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) msleep(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (i2c_readbytes(state,state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) &rec_buf[12],2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pr_warn("Load DVR Error D\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) rec_buf[i]=0xed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) get_ver_buf[4] = i+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (i2c_writebytes(state,state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) get_ver_buf,5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pr_warn("Load DVR Error 6 - %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) msleep(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (i2c_readbytes(state,state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) &rec_buf[i*2],2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pr_warn("Load DVR Error 7 - %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* If we didn't receive the right index, try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if ((int)rec_buf[i*2+1]!=i+1){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) i--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dprintk("read_fwbits %10ph\n", rec_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pr_info("ver TU%02x%02x%02x VSB mode %02x Status %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) rec_buf[2], rec_buf[4], rec_buf[6], rec_buf[12],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) rec_buf[10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) rec_buf[0] = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) rec_buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) rec_buf[2] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) rec_buf[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (i2c_writebytes(state,state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) rec_buf,3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pr_warn("Load DVR Error 8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (i2c_readbytes(state,state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) &rec_buf[8],2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pr_warn("Load DVR Error 9\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) state->initialized = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int or51211_get_tune_settings(struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct dvb_frontend_tune_settings* fesettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) fesettings->min_delay_ms = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) fesettings->step_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) fesettings->max_drift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static void or51211_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct or51211_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) state->config->sleep(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const struct dvb_frontend_ops or51211_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct dvb_frontend* or51211_attach(const struct or51211_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct i2c_adapter* i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct or51211_state* state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) state = kzalloc(sizeof(struct or51211_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) state->initialized = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) state->current_frequency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) memcpy(&state->frontend.ops, &or51211_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const struct dvb_frontend_ops or51211_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .name = "Oren OR51211 VSB Frontend",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .frequency_min_hz = 44 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .frequency_max_hz = 958 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .frequency_stepsize_hz = 166666,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) FE_CAN_8VSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .release = or51211_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .init = or51211_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .sleep = or51211_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .set_frontend = or51211_set_parameters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .get_tune_settings = or51211_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .read_status = or51211_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .read_ber = or51211_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .read_signal_strength = or51211_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .read_snr = or51211_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .read_ucblocks = or51211_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MODULE_DESCRIPTION("Oren OR51211 VSB [pcHDTV HD-2000] Demodulator Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MODULE_AUTHOR("Kirk Lapray");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) EXPORT_SYMBOL(or51211_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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