Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *    Support for OR51132 (pcHDTV HD-3000) - VSB/QAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *    Copyright (C) 2007 Trent Piepho <xyzzy@speakeasy.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *    Copyright (C) 2005 Kirk Lapray <kirk_lapray@bigfoot.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *    Based on code from Jack Kelliher (kelliher@xmission.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *                           Copyright (C) 2002 & pcHDTV, inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * This driver needs two external firmware files. Please copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * "dvb-fe-or51132-vsb.fw" and "dvb-fe-or51132-qam.fw" to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * /usr/lib/hotplug/firmware/ or /lib/firmware/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * (depending on configuration of firmware hotplug).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define OR51132_VSB_FIRMWARE "dvb-fe-or51132-vsb.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define OR51132_QAM_FIRMWARE "dvb-fe-or51132-qam.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <media/dvb_math.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include "or51132.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		if (debug) printk(KERN_DEBUG "or51132: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) struct or51132_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	/* Configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	const struct or51132_config* config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/* Demodulator private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	enum fe_modulation current_modulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u32 snr; /* Result of last SNR calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	/* Tuner private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u32 current_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* Write buffer to demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static int or51132_writebuf(struct or51132_state *state, const u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct i2c_msg msg = { .addr = state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			       .flags = 0, .buf = (u8*)buf, .len = len };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	/* msleep(20); */ /* doesn't appear to be necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		printk(KERN_WARNING "or51132: I2C write (addr 0x%02x len %d) error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		       msg.addr, msg.len, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* Write constant bytes, e.g. or51132_writebytes(state, 0x04, 0x42, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)    Less code and more efficient that loading a buffer on the stack with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)    the bytes to send and then calling or51132_writebuf() on that. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define or51132_writebytes(state, data...)  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	({ static const u8 _data[] = {data}; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	or51132_writebuf(state, _data, sizeof(_data)); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /* Read data from demod into buffer.  Returns 0 on success. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static int or51132_readbuf(struct or51132_state *state, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct i2c_msg msg = { .addr = state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			       .flags = I2C_M_RD, .buf = buf, .len = len };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/* msleep(20); */ /* doesn't appear to be necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		printk(KERN_WARNING "or51132: I2C read (addr 0x%02x len %d) error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		       msg.addr, msg.len, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /* Reads a 16-bit demod register.  Returns <0 on error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static int or51132_readreg(struct or51132_state *state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u8 buf[2] = { 0x04, reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		{.addr = state->config->demod_address, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		 .buf = buf, .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		{.addr = state->config->demod_address, .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		 .buf = buf, .len = 2 }};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if ((err = i2c_transfer(state->i2c, msg, 2)) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		printk(KERN_WARNING "or51132: I2C error reading register %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		       reg, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	return buf[0] | (buf[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int or51132_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct or51132_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	static const u8 run_buf[] = {0x7F,0x01};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u8 rec_buf[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u32 firmwareAsize, firmwareBsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int i,ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	dprintk("Firmware is %zd bytes\n",fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/* Get size of firmware A and B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	firmwareAsize = le32_to_cpu(*((__le32*)fw->data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	dprintk("FirmwareA is %i bytes\n",firmwareAsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	firmwareBsize = le32_to_cpu(*((__le32*)(fw->data+4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	dprintk("FirmwareB is %i bytes\n",firmwareBsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* Upload firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if ((ret = or51132_writebuf(state, &fw->data[8], firmwareAsize))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		printk(KERN_WARNING "or51132: load_firmware error 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if ((ret = or51132_writebuf(state, &fw->data[8+firmwareAsize],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 				    firmwareBsize))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		printk(KERN_WARNING "or51132: load_firmware error 2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if ((ret = or51132_writebuf(state, run_buf, 2))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		printk(KERN_WARNING "or51132: load_firmware error 3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if ((ret = or51132_writebuf(state, run_buf, 2))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		printk(KERN_WARNING "or51132: load_firmware error 4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* 50ms for operation to begin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* Read back ucode version to besure we loaded correctly and are really up and running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* Get uCode version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if ((ret = or51132_writebytes(state, 0x10, 0x10, 0x00))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		printk(KERN_WARNING "or51132: load_firmware error a\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if ((ret = or51132_writebytes(state, 0x04, 0x17))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		printk(KERN_WARNING "or51132: load_firmware error b\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if ((ret = or51132_writebytes(state, 0x00, 0x00))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		printk(KERN_WARNING "or51132: load_firmware error c\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	for (i=0;i<4;i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		/* Once upon a time, this command might have had something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		   to do with getting the firmware version, but it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		   not used anymore:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		   {0x04,0x00,0x30,0x00,i+1} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		/* Read 8 bytes, two bytes at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		if ((ret = or51132_readbuf(state, &rec_buf[i*2], 2))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			       "or51132: load_firmware error d - %d\n",i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	       "or51132: Version: %02X%02X%02X%02X-%02X%02X%02X%02X (%02X%01X-%01X-%02X%01X-%01X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	       rec_buf[1],rec_buf[0],rec_buf[3],rec_buf[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	       rec_buf[5],rec_buf[4],rec_buf[7],rec_buf[6],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	       rec_buf[3],rec_buf[2]>>4,rec_buf[2]&0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	       rec_buf[5],rec_buf[4]>>4,rec_buf[4]&0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if ((ret = or51132_writebytes(state, 0x10, 0x00, 0x00))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		printk(KERN_WARNING "or51132: load_firmware error e\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int or51132_init(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int or51132_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	*ber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int or51132_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	*ucblocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int or51132_sleep(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int or51132_setmode(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct or51132_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	u8 cmd_buf1[3] = {0x04, 0x01, 0x5f};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	u8 cmd_buf2[3] = {0x1c, 0x00, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	dprintk("setmode %d\n",(int)state->current_modulation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	switch (state->current_modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	case VSB_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		/* Auto CH, Auto NTSC rej, MPEGser, MPEG2tr, phase noise-high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		cmd_buf1[2] = 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		/* REC MODE inv IF spectrum, Normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		cmd_buf2[1] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		/* Channel MODE ATSC/VSB8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		cmd_buf2[2] = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* All QAM modes are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	   Auto-deinterleave; MPEGser, MPEG2tr, phase noise-high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	   REC MODE Normal Carrier Lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	case QAM_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		/* Channel MODE Auto QAM64/256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		cmd_buf2[2] = 0x4f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		/* Channel MODE QAM256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		cmd_buf2[2] = 0x45;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		/* Channel MODE QAM64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		cmd_buf2[2] = 0x43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		       "or51132: setmode: Modulation set to unsupported value (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		       state->current_modulation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	/* Set Receiver 1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (or51132_writebuf(state, cmd_buf1, 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		printk(KERN_WARNING "or51132: set_mode error 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	dprintk("set #1 to %02x\n", cmd_buf1[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* Set operation mode in Receiver 6 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (or51132_writebuf(state, cmd_buf2, 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		printk(KERN_WARNING "or51132: set_mode error 2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	dprintk("set #6 to 0x%02x%02x\n", cmd_buf2[1], cmd_buf2[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Some modulations use the same firmware.  This classifies modulations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)    by the firmware they use. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MOD_FWCLASS_UNKNOWN	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MOD_FWCLASS_VSB		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define MOD_FWCLASS_QAM		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int modulation_fw_class(enum fe_modulation modulation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	switch(modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	case VSB_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return MOD_FWCLASS_VSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	case QAM_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return MOD_FWCLASS_QAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return MOD_FWCLASS_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int or51132_set_parameters(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct or51132_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	const char *fwname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	int clock_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	/* Upload new firmware only if we need a different one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (modulation_fw_class(state->current_modulation) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	    modulation_fw_class(p->modulation)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		switch (modulation_fw_class(p->modulation)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		case MOD_FWCLASS_VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			dprintk("set_parameters VSB MODE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			fwname = OR51132_VSB_FIRMWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			/* Set non-punctured clock for VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			clock_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		case MOD_FWCLASS_QAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			dprintk("set_parameters QAM MODE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			fwname = OR51132_QAM_FIRMWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			/* Set punctured clock for QAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			clock_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			printk("or51132: Modulation type(%d) UNSUPPORTED\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			       p->modulation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		printk("or51132: Waiting for firmware upload(%s)...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		       fwname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		ret = request_firmware(&fw, fwname, state->i2c->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			printk(KERN_WARNING "or51132: No firmware uploaded(timeout or file not found?)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		ret = or51132_load_firmware(fe, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			printk(KERN_WARNING "or51132: Writing firmware to device failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		printk("or51132: Firmware upload complete.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		state->config->set_ts_params(fe, clock_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	/* Change only if we are actually changing the modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (state->current_modulation != p->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		state->current_modulation = p->modulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		or51132_setmode(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	/* Set to current mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	or51132_setmode(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	/* Update current frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	state->current_frequency = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int or51132_get_parameters(struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 				  struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	struct or51132_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	int retry = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	/* Receiver Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	if ((status = or51132_readreg(state, 0x00)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		printk(KERN_WARNING "or51132: get_parameters: error reading receiver status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	switch(status&0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	case 0x06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		p->modulation = VSB_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	case 0x43:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		p->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	case 0x45:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		p->modulation = QAM_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		if (retry--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			goto start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		printk(KERN_WARNING "or51132: unknown status 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		       status&0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	/* FIXME: Read frequency from frontend, take AFC into account */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	p->frequency = state->current_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	/* FIXME: How to read inversion setting? Receiver 6 register? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	p->inversion = INVERSION_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int or51132_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	struct or51132_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	/* Receiver Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	if ((reg = or51132_readreg(state, 0x00)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		printk(KERN_WARNING "or51132: read_status: error reading receiver status: %d\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		*status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	dprintk("%s: read_status %04x\n", __func__, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	if (reg & 0x0100) /* Receiver Lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		*status = FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 			  FE_HAS_SYNC|FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		*status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Calculate SNR estimation (scaled by 2^24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)    8-VSB SNR and QAM equations from Oren datasheets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)    For 8-VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)      SNR[dB] = 10 * log10(897152044.8282 / MSE^2 ) - K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)      Where K = 0 if NTSC rejection filter is OFF; and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	   K = 3 if NTSC rejection filter is ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)    For QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)      SNR[dB] = 10 * log10(897152044.8282 / MSE^2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)    For QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)      SNR[dB] = 10 * log10(907832426.314266  / MSE^2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)    We re-write the snr equation as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)      SNR * 2^24 = 10*(c - 2*intlog10(MSE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)    Where for QAM256, c = log10(907832426.314266) * 2^24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)    and for 8-VSB and QAM64, c = log10(897152044.8282) * 2^24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static u32 calculate_snr(u32 mse, u32 c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	if (mse == 0) /* No signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	mse = 2*intlog10(mse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	if (mse > c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		/* Negative SNR, which is possible, but realisticly the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		demod will lose lock before the signal gets this bad.  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		API only allows for unsigned values, so just return 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	return 10*(c - mse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int or51132_read_snr(struct dvb_frontend* fe, u16* snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	struct or51132_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	int noise, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	u32 c, usK = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	int retry = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	/* SNR after Equalizer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	noise = or51132_readreg(state, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	if (noise < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		printk(KERN_WARNING "or51132: read_snr: error reading equalizer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	dprintk("read_snr noise (%d)\n", noise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	/* Read status, contains modulation type for QAM_AUTO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	   NTSC filter for VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	reg = or51132_readreg(state, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	if (reg < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		printk(KERN_WARNING "or51132: read_snr: error reading receiver status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	switch (reg&0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	case 0x06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		if (reg & 0x1000) usK = 3 << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	case 0x43: /* QAM64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		c = 150204167;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	case 0x45:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		c = 150290396;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		printk(KERN_WARNING "or51132: unknown status 0x%02x\n", reg&0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		if (retry--) goto start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	dprintk("%s: modulation %02x, NTSC rej O%s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		reg&0xff, reg&0x1000?"n":"ff");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	/* Calculate SNR using noise, c, and NTSC rejection correction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	state->snr = calculate_snr(noise, c) - usK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	*snr = (state->snr) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __func__, noise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		state->snr >> 24, (((state->snr>>8) & 0xffff) * 100) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int or51132_read_signal_strength(struct dvb_frontend* fe, u16* strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	/* Calculate Strength from SNR up to 35dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	/* Even though the SNR can go higher than 35dB, there is some comfort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	/* factor in having a range of strong signals that can show at 100%   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	struct or51132_state* state = (struct or51132_state*) fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	u16 snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	ret = fe->ops.read_snr(fe, &snr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	/* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	/* scale the range 0 - 35*2^24 into 0 - 65535 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	if (state->snr >= 8960 * 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		*strength = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 		*strength = state->snr / 8960;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int or51132_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	fe_tune_settings->min_delay_ms = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	fe_tune_settings->step_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	fe_tune_settings->max_drift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void or51132_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	struct or51132_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const struct dvb_frontend_ops or51132_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct dvb_frontend* or51132_attach(const struct or51132_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 				    struct i2c_adapter* i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	struct or51132_state* state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	/* Allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	state = kzalloc(sizeof(struct or51132_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	/* Setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	state->current_frequency = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	state->current_modulation = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	/* Create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	memcpy(&state->frontend.ops, &or51132_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static const struct dvb_frontend_ops or51132_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 		.name			= "Oren OR51132 VSB/QAM Frontend",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 		.frequency_min_hz	=  44 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 		.frequency_max_hz	= 958 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 		.frequency_stepsize_hz	= 166666,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 		.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 			FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 			FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 			FE_CAN_8VSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	.release = or51132_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	.init = or51132_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	.sleep = or51132_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	.set_frontend = or51132_set_parameters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	.get_frontend = or51132_get_parameters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	.get_tune_settings = or51132_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	.read_status = or51132_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	.read_ber = or51132_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	.read_signal_strength = or51132_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	.read_snr = or51132_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	.read_ucblocks = or51132_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MODULE_DESCRIPTION("OR51132 ATSC [pcHDTV HD-3000] (8VSB & ITU J83 AnnexB FEC QAM64/256) Demodulator Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MODULE_AUTHOR("Kirk Lapray");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MODULE_AUTHOR("Trent Piepho");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) EXPORT_SYMBOL(or51132_attach);