^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License type: GPLv2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or modify it under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the terms of the GNU General Public License as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is distributed in the hope that it will be useful, but WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This program may alternatively be licensed under a proprietary license from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * MaxLinear, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifndef __MXL58X_REGISTERS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define __MXL58X_REGISTERS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HYDRA_INTR_STATUS_REG 0x80030008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HYDRA_INTR_MASK_REG 0x8003000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HYDRA_CPU_RESET_REG 0x8003003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HYDRA_CPU_RESET_DATA 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HYDRA_RESET_BBAND_REG 0x80030024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HYDRA_RESET_BBAND_DATA 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HYDRA_RESET_XBAR_REG 0x80030020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HYDRA_RESET_XBAR_DATA 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HYDRA_MODULES_CLK_1_REG 0x80030014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HYDRA_DISABLE_CLK_1 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HYDRA_MODULES_CLK_2_REG 0x8003001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HYDRA_DISABLE_CLK_2 0x0000000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HYDRA_PRCM_ROOT_CLK_REG 0x80030018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HYDRA_PRCM_ROOT_CLK_DISABLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HYDRA_CPU_RESET_CHECK_REG 0x80030008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HYDRA_CPU_RESET_CHECK_OFFSET 0x40000000 /* <bit 30> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HYDRA_SKU_ID_REG 0x90000190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FW_DL_SIGN_ADDR 0x3FFFEAE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Register to check if FW is running or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HYDRA_HEAR_BEAT 0x3FFFEDDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HYDRA_FIRMWARE_VERSION 0x3FFFEDB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HYDRA_FW_RC_VERSION 0x3FFFCFAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Firmware patch version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HYDRA_FIRMWARE_PATCH_VERSION 0x3FFFEDC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* SOC operating temperature in C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HYDRA_TEMPARATURE 0x3FFFEDB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Demod & Tuner status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Demod 0 status base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HYDRA_DEMOD_0_BASE_ADDR 0x3FFFC64C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Tuner 0 status base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HYDRA_TUNER_0_BASE_ADDR 0x3FFFCE4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define POWER_FROM_ADCRSSI_READBACK 0x3FFFEB6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Macros to determine base address of respective demod or tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HYDRA_DMD_STATUS_OFFSET(demodID) ((demodID) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HYDRA_TUNER_STATUS_OFFSET(tunerID) ((tunerID) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Demod status address offset from respective demod's base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HYDRA_DMD_AGC_DIG_LEVEL_ADDR_OFFSET 0x3FFFC64C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET 0x3FFFC650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HYDRA_DMD_ACQ_STATUS_ADDR_OFFSET 0x3FFFC654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HYDRA_DMD_STANDARD_ADDR_OFFSET 0x3FFFC658
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HYDRA_DMD_SPECTRUM_INVERSION_ADDR_OFFSET 0x3FFFC65C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HYDRA_DMD_SPECTRUM_ROLL_OFF_ADDR_OFFSET 0x3FFFC660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HYDRA_DMD_SYMBOL_RATE_ADDR_OFFSET 0x3FFFC664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HYDRA_DMD_MODULATION_SCHEME_ADDR_OFFSET 0x3FFFC668
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HYDRA_DMD_FEC_CODE_RATE_ADDR_OFFSET 0x3FFFC66C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HYDRA_DMD_SNR_ADDR_OFFSET 0x3FFFC670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HYDRA_DMD_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HYDRA_DMD_CTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HYDRA_DMD_STR_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC67C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HYDRA_DMD_FTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HYDRA_DMD_STR_NBC_SYNC_LOCK_ADDR_OFFSET 0x3FFFC684
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HYDRA_DMD_CYCLE_SLIP_COUNT_ADDR_OFFSET 0x3FFFC688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HYDRA_DMD_DISPLAY_I_ADDR_OFFSET 0x3FFFC68C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HYDRA_DMD_DISPLAY_Q_ADDR_OFFSET 0x3FFFC68E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET 0x3FFFC690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HYDRA_DMD_DVBS2_PER_COUNT_ADDR_OFFSET 0x3FFFC694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HYDRA_DMD_DVBS2_PER_WINDOW_ADDR_OFFSET 0x3FFFC698
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HYDRA_DMD_DVBS_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC69C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HYDRA_DMD_DVBS_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HYDRA_DMD_DVBS_BER_COUNT_ADDR_OFFSET 0x3FFFC6A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HYDRA_DMD_DVBS_BER_WINDOW_ADDR_OFFSET 0x3FFFC6A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Debug-purpose DVB-S DMD 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6C8 /* corrected RS Errors: 1st iteration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HYDRA_DMD_DVBS_1ST_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6CC /* uncorrected RS Errors: 1st iteration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HYDRA_DMD_DVBS_BER_COUNT_1ST_ADDR_OFFSET 0x3FFFC6D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HYDRA_DMD_DVBS_BER_WINDOW_1ST_ADDR_OFFSET 0x3FFFC6D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HYDRA_DMD_TUNER_ID_ADDR_OFFSET 0x3FFFC6AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HYDRA_DMD_DVBS2_PILOT_ON_OFF_ADDR_OFFSET 0x3FFFC6B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HYDRA_DMD_FREQ_SEARCH_RANGE_KHZ_ADDR_OFFSET 0x3FFFC6B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET 0x3FFFC6B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR 0x3FFFC704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HYDRA_DMD_STATUS_INPUT_POWER_ADDR 0x3FFFC708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* DVB-S new scaled_BER_count for a new BER API, see HYDRA-1343 "DVB-S post viterbi information" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DMD0_STATUS_DVBS_1ST_SCALED_BER_COUNT_ADDR 0x3FFFC710 /* DMD 0: 1st iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DMD0_STATUS_DVBS_SCALED_BER_COUNT_ADDR 0x3FFFC714 /* DMD 0: 2nd iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DMD0_SPECTRUM_MIN_GAIN_STATUS 0x3FFFC73C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DMD0_SPECTRUM_MIN_GAIN_WB_SAGC_VALUE 0x3FFFC740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DMD0_SPECTRUM_MIN_GAIN_NB_SAGC_VALUE 0x3FFFC744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HYDRA_DMD_STATUS_END_ADDR_OFFSET 0x3FFFC748
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Tuner status address offset from respective tuners's base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HYDRA_TUNER_DEMOD_ID_ADDR_OFFSET 0x3FFFCE4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HYDRA_TUNER_AGC_LOCK_OFFSET 0x3FFFCE50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HYDRA_TUNER_SPECTRUM_STATUS_OFFSET 0x3FFFCE54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HYDRA_TUNER_SPECTRUM_BIN_SIZE_OFFSET 0x3FFFCE58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HYDRA_TUNER_SPECTRUM_ADDRESS_OFFSET 0x3FFFCE5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HYDRA_TUNER_ENABLE_COMPLETE 0x3FFFEB78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HYDRA_DEMOD_STATUS_LOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_YES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HYDRA_DEMOD_STATUS_UNLOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_NO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HYDRA_VERSION 0x3FFFEDB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HYDRA_DEMOD0_VERSION 0x3FFFEDBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HYDRA_DEMOD1_VERSION 0x3FFFEDC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HYDRA_DEMOD2_VERSION 0x3FFFEDC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HYDRA_DEMOD3_VERSION 0x3FFFEDC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HYDRA_DEMOD4_VERSION 0x3FFFEDCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HYDRA_DEMOD5_VERSION 0x3FFFEDD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HYDRA_DEMOD6_VERSION 0x3FFFEDD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HYDRA_DEMOD7_VERSION 0x3FFFEDD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HYDRA_HEAR_BEAT 0x3FFFEDDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HYDRA_SKU_MGMT 0x3FFFEBC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MXL_HYDRA_FPGA_A_ADDRESS 0x91C00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MXL_HYDRA_FPGA_B_ADDRESS 0x91D00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* TS control base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HYDRA_TS_CTRL_BASE_ADDR 0x90700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MPEG_MUX_MODE_SLICE0_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MPEG_MUX_MODE_SLICE1_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PID_BANK_SEL_SLICE0_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PID_BANK_SEL_SLICE1_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MPEG_CLK_GATED_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MPEG_CLK_ALWAYS_ON_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1D4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HYDRA_REGULAR_PID_BANK_A_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define HYDRA_FIXED_PID_BANK_A_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HYDRA_REGULAR_PID_BANK_B_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define HYDRA_FIXED_PID_BANK_B_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define FIXED_PID_TBL_REG_ADDRESS_0 (HYDRA_TS_CTRL_BASE_ADDR + 0x9000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define FIXED_PID_TBL_REG_ADDRESS_1 (HYDRA_TS_CTRL_BASE_ADDR + 0x9100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define FIXED_PID_TBL_REG_ADDRESS_2 (HYDRA_TS_CTRL_BASE_ADDR + 0x9200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define FIXED_PID_TBL_REG_ADDRESS_3 (HYDRA_TS_CTRL_BASE_ADDR + 0x9300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define FIXED_PID_TBL_REG_ADDRESS_4 (HYDRA_TS_CTRL_BASE_ADDR + 0xB000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define FIXED_PID_TBL_REG_ADDRESS_5 (HYDRA_TS_CTRL_BASE_ADDR + 0xB100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define FIXED_PID_TBL_REG_ADDRESS_6 (HYDRA_TS_CTRL_BASE_ADDR + 0xB200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define FIXED_PID_TBL_REG_ADDRESS_7 (HYDRA_TS_CTRL_BASE_ADDR + 0xB300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define REGULAR_PID_TBL_REG_ADDRESS_0 (HYDRA_TS_CTRL_BASE_ADDR + 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define REGULAR_PID_TBL_REG_ADDRESS_1 (HYDRA_TS_CTRL_BASE_ADDR + 0x8200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define REGULAR_PID_TBL_REG_ADDRESS_2 (HYDRA_TS_CTRL_BASE_ADDR + 0x8400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define REGULAR_PID_TBL_REG_ADDRESS_3 (HYDRA_TS_CTRL_BASE_ADDR + 0x8600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define REGULAR_PID_TBL_REG_ADDRESS_4 (HYDRA_TS_CTRL_BASE_ADDR + 0xA000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define REGULAR_PID_TBL_REG_ADDRESS_5 (HYDRA_TS_CTRL_BASE_ADDR + 0xA200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define REGULAR_PID_TBL_REG_ADDRESS_6 (HYDRA_TS_CTRL_BASE_ADDR + 0xA400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define REGULAR_PID_TBL_REG_ADDRESS_7 (HYDRA_TS_CTRL_BASE_ADDR + 0xA600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PAD_MUX_GPIO_00_SYNC_BASEADDR 0x90000188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PAD_MUX_UART_RX_C_PINMUX_BASEADDR 0x9000001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define XPT_PACKET_GAP_MIN_BASEADDR 0x90700044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define XPT_NCO_COUNT_BASEADDR 0x90700238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define XPT_NCO_COUNT_BASEADDR1 0x9070023C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* V2 DigRF status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define XPT_PID_BASEADDR 0x90708000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define XPT_PID_REMAP_BASEADDR 0x90708004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define XPT_KNOWN_PID_BASEADDR 0x90709000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define XPT_PID_BASEADDR1 0x9070A000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define XPT_PID_REMAP_BASEADDR1 0x9070A004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define XPT_KNOWN_PID_BASEADDR1 0x9070B000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define XPT_BERT_LOCK_BASEADDR 0x907000B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define XPT_BERT_BASEADDR 0x907000BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define XPT_BERT_INVERT_BASEADDR 0x907000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define XPT_BERT_HEADER_BASEADDR 0x907000C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define XPT_BERT_BASEADDR1 0x907000C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define XPT_BERT_BIT_COUNT0_BASEADDR 0x907000CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define XPT_BERT_BIT_COUNT0_BASEADDR1 0x907000D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define XPT_BERT_BIT_COUNT1_BASEADDR 0x907000D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define XPT_BERT_BIT_COUNT1_BASEADDR1 0x907000D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define XPT_BERT_BIT_COUNT2_BASEADDR 0x907000DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define XPT_BERT_BIT_COUNT2_BASEADDR1 0x907000E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define XPT_BERT_BIT_COUNT3_BASEADDR 0x907000E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define XPT_BERT_BIT_COUNT3_BASEADDR1 0x907000E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define XPT_BERT_BIT_COUNT4_BASEADDR 0x907000EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define XPT_BERT_BIT_COUNT4_BASEADDR1 0x907000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define XPT_BERT_BIT_COUNT5_BASEADDR 0x907000F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define XPT_BERT_BIT_COUNT5_BASEADDR1 0x907000F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define XPT_BERT_BIT_COUNT6_BASEADDR 0x907000FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define XPT_BERT_BIT_COUNT6_BASEADDR1 0x90700100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define XPT_BERT_BIT_COUNT7_BASEADDR 0x90700104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define XPT_BERT_BIT_COUNT7_BASEADDR1 0x90700108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define XPT_BERT_ERR_COUNT0_BASEADDR 0x9070010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define XPT_BERT_ERR_COUNT0_BASEADDR1 0x90700110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define XPT_BERT_ERR_COUNT1_BASEADDR 0x90700114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define XPT_BERT_ERR_COUNT1_BASEADDR1 0x90700118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define XPT_BERT_ERR_COUNT2_BASEADDR 0x9070011C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define XPT_BERT_ERR_COUNT2_BASEADDR1 0x90700120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define XPT_BERT_ERR_COUNT3_BASEADDR 0x90700124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define XPT_BERT_ERR_COUNT3_BASEADDR1 0x90700128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define XPT_BERT_ERR_COUNT4_BASEADDR 0x9070012C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define XPT_BERT_ERR_COUNT4_BASEADDR1 0x90700130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define XPT_BERT_ERR_COUNT5_BASEADDR 0x90700134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define XPT_BERT_ERR_COUNT5_BASEADDR1 0x90700138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define XPT_BERT_ERR_COUNT6_BASEADDR 0x9070013C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define XPT_BERT_ERR_COUNT6_BASEADDR1 0x90700140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define XPT_BERT_ERR_COUNT7_BASEADDR 0x90700144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define XPT_BERT_ERR_COUNT7_BASEADDR1 0x90700148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define XPT_BERT_ERROR_BASEADDR 0x9070014C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define XPT_BERT_ANALYZER_BASEADDR 0x90700150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define XPT_BERT_ANALYZER_BASEADDR1 0x90700154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define XPT_BERT_ANALYZER_BASEADDR2 0x90700158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define XPT_BERT_ANALYZER_BASEADDR3 0x9070015C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define XPT_BERT_ANALYZER_BASEADDR4 0x90700160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define XPT_BERT_ANALYZER_BASEADDR5 0x90700164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define XPT_BERT_ANALYZER_BASEADDR6 0x90700168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define XPT_BERT_ANALYZER_BASEADDR7 0x9070016C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define XPT_BERT_ANALYZER_BASEADDR8 0x90700170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define XPT_BERT_ANALYZER_BASEADDR9 0x90700174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define XPT_DMD0_BASEADDR 0x9070024C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* V2 AGC Gain Freeze & step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DBG_ENABLE_DISABLE_AGC (0x3FFFCF60) /* 1: DISABLE, 0:ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define WB_DFE0_DFE_FB_RF1_BASEADDR 0x903004A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define WB_DFE1_DFE_FB_RF1_BASEADDR 0x904004A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define WB_DFE2_DFE_FB_RF1_BASEADDR 0x905004A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define WB_DFE3_DFE_FB_RF1_BASEADDR 0x906004A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR 0x90200104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define AFE_REG_AFE_REG_SPARE_BASEADDR 0x902000A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define AFE_REG_AFE_REG_SPARE_BASEADDR1 0x902000B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define AFE_REG_AFE_REG_SPARE_BASEADDR2 0x902000C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define AFE_REG_AFE_REG_SPARE_BASEADDR3 0x902000D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define WB_DFE0_DFE_FB_AGC_BASEADDR 0x90300498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define WB_DFE1_DFE_FB_AGC_BASEADDR 0x90400498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define WB_DFE2_DFE_FB_AGC_BASEADDR 0x90500498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define WB_DFE3_DFE_FB_AGC_BASEADDR 0x90600498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define WDT_WD_INT_BASEADDR 0x8002000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define FSK_TX_FTM_BASEADDR 0x80090000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define FSK_TX_FTM_TX_CNT_BASEADDR 0x80090018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define AFE_REG_D2A_FSK_BIAS_BASEADDR 0x90200040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DMD_TEI_BASEADDR 0x3FFFEBE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #endif /* __MXL58X_REGISTERS_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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