^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Defines for the Maxlinear MX58x family of tuners/demods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Digital Devices GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * based on code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * which was released under GPL V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * modify it under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * version 2, as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum MXL_BOOL_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) MXL_DISABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MXL_ENABLE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MXL_FALSE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MXL_TRUE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MXL_INVALID = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MXL_VALID = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MXL_NO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MXL_YES = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MXL_OFF = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MXL_ON = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Firmware-Host Command IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum MXL_HYDRA_HOST_CMD_ID_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* --Device command IDs-- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MXL_HYDRA_DEV_NO_OP_CMD = 0, /* No OP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MXL_HYDRA_DEV_SET_POWER_MODE_CMD = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MXL_HYDRA_DEV_SET_OVERWRITE_DEF_CMD = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Host-used CMD, not used by firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MXL_HYDRA_DEV_FIRMWARE_DOWNLOAD_CMD = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Additional CONTROL types from DTV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MXL_HYDRA_DEV_SET_BROADCAST_PID_STB_ID_CMD = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MXL_HYDRA_DEV_GET_PMM_SLEEP_CMD = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* --Tuner command IDs-- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MXL_HYDRA_TUNER_TUNE_CMD = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MXL_HYDRA_TUNER_GET_STATUS_CMD = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* --Demod command IDs-- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MXL_HYDRA_DEMOD_SET_PARAM_CMD = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MXL_HYDRA_DEMOD_GET_STATUS_CMD = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MXL_HYDRA_DEMOD_RESET_FEC_COUNTER_CMD = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MXL_HYDRA_DEMOD_SET_PKT_NUM_CMD = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MXL_HYDRA_DEMOD_SET_IQ_SOURCE_CMD = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MXL_HYDRA_DEMOD_GET_IQ_DATA_CMD = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MXL_HYDRA_DEMOD_GET_M68HC05_VER_CMD = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MXL_HYDRA_DEMOD_SET_ERROR_COUNTER_MODE_CMD = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* --- ABORT channel tune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MXL_HYDRA_ABORT_TUNE_CMD = 16, /* Abort current tune command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* --SWM/FSK command IDs-- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MXL_HYDRA_FSK_RESET_CMD = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MXL_HYDRA_FSK_MSG_CMD = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MXL_HYDRA_FSK_SET_OP_MODE_CMD = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* --DiSeqC command IDs-- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MXL_HYDRA_DISEQC_MSG_CMD = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MXL_HYDRA_DISEQC_COPY_MSG_TO_MAILBOX = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MXL_HYDRA_DISEQC_CFG_MSG_CMD = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* --- FFT Debug Command IDs-- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MXL_HYDRA_REQ_FFT_SPECTRUM_CMD = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* -- Demod scramblle code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MXL_HYDRA_DEMOD_SCRAMBLE_CODE_CMD = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* ---For host to know how many commands in total */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MXL_HYDRA_LAST_HOST_CMD = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MXL_HYDRA_DEMOD_INTR_TYPE_CMD = 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MXL_HYDRA_DEV_INTR_CLEAR_CMD = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MXL_HYDRA_TUNER_SPECTRUM_REQ_CMD = 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MXL_HYDRA_TUNER_ACTIVATE_CMD = 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MXL_HYDRA_DEV_CFG_POWER_MODE_CMD = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MXL_HYDRA_DEV_XTAL_CAP_CMD = 57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MXL_HYDRA_DEV_CFG_SKU_CMD = 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MXL_HYDRA_TUNER_SPECTRUM_MIN_GAIN_CMD = 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MXL_HYDRA_DISEQC_CONT_TONE_CFG = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MXL_HYDRA_DEV_RF_WAKE_UP_CMD = 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MXL_HYDRA_DEMOD_CFG_EQ_CTRL_PARAM_CMD = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MXL_HYDRA_DEMOD_FREQ_OFFSET_SEARCH_RANGE_CMD = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MXL_HYDRA_DEV_REQ_PWR_FROM_ADCRSSI_CMD = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MXL_XCPU_PID_FLT_CFG_CMD = 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MXL_XCPU_SHMEM_TEST_CMD = 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MXL_XCPU_ABORT_TUNE_CMD = 67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MXL_XCPU_CHAN_TUNE_CMD = 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MXL_XCPU_FLT_BOND_HDRS_CMD = 69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MXL_HYDRA_DEV_BROADCAST_WAKE_UP_CMD = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MXL_HYDRA_FSK_CFG_FSK_FREQ_CMD = 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MXL_HYDRA_FSK_POWER_DOWN_CMD = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MXL_XCPU_CLEAR_CB_STATS_CMD = 73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MXL_XCPU_CHAN_BOND_RESTART_CMD = 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MXL_ENABLE_BIG_ENDIAN (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN (248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MXL_HYDRA_CAP_MIN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MXL_HYDRA_CAP_MAX 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MXL_HYDRA_PLID_REG_READ 0xFB /* Read register PLID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MXL_HYDRA_PLID_REG_WRITE 0xFC /* Write register PLID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MXL_HYDRA_PLID_CMD_READ 0xFD /* Command Read PLID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MXL_HYDRA_PLID_CMD_WRITE 0xFE /* Command Write PLID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MXL_HYDRA_REG_SIZE_IN_BYTES 4 /* Hydra register size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MXL_HYDRA_I2C_HDR_SIZE (2 * sizeof(u8)) /* PLID + LEN(0xFF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MXL_HYDRA_CMD_HEADER_SIZE (MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MXL_HYDRA_SKU_ID_581 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MXL_HYDRA_SKU_ID_584 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MXL_HYDRA_SKU_ID_585 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MXL_HYDRA_SKU_ID_544 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MXL_HYDRA_SKU_ID_561 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MXL_HYDRA_SKU_ID_582 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MXL_HYDRA_SKU_ID_568 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* macro for register write data buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * (PLID + LEN (0xFF) + RegAddr + RegData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MXL_HYDRA_REG_WRITE_LEN (MXL_HYDRA_I2C_HDR_SIZE + (2 * MXL_HYDRA_REG_SIZE_IN_BYTES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* macro to extract a single byte from 4-byte(32-bit) data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GET_BYTE(x, n) (((x) >> (8*(n))) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MAX_CMD_DATA 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MXL_GET_REG_MASK_32(lsb_loc, num_of_bits) ((0xFFFFFFFF >> (32 - (num_of_bits))) << (lsb_loc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define FW_DL_SIGN (0xDEADBEEF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MBIN_FORMAT_VERSION '1'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MBIN_FILE_HEADER_ID 'M'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MBIN_SEGMENT_HEADER_ID 'S'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MBIN_MAX_FILE_LENGTH (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct MBIN_FILE_HEADER_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 fmt_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 header_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 num_segments;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u8 entry_address[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u8 image_size24[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 image_checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct MBIN_FILE_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct MBIN_FILE_HEADER_T header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct MBIN_SEGMENT_HEADER_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 len24[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 address[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct MBIN_SEGMENT_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct MBIN_SEGMENT_HEADER_T header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) enum MXL_CMD_TYPE_E { MXL_CMD_WRITE = 0, MXL_CMD_READ };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define BUILD_HYDRA_CMD(cmd_id, req_type, size, data_ptr, cmd_buff) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) cmd_buff[0] = ((req_type == MXL_CMD_WRITE) ? MXL_HYDRA_PLID_CMD_WRITE : MXL_HYDRA_PLID_CMD_READ); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) cmd_buff[1] = (size > 251) ? 0xff : (u8) (size + 4); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) cmd_buff[2] = size; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cmd_buff[3] = cmd_id; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cmd_buff[4] = 0x00; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) cmd_buff[5] = 0x00; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) convert_endian(MXL_ENABLE_BIG_ENDIAN, size, (u8 *)data_ptr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) memcpy((void *)&cmd_buff[6], data_ptr, size); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct MXL_REG_FIELD_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 lsb_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 num_of_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct MXL_DEV_CMD_DATA_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 data[MAX_CMD_DATA];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) enum MXL_HYDRA_SKU_TYPE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MXL_HYDRA_SKU_TYPE_MIN = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MXL_HYDRA_SKU_TYPE_581 = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MXL_HYDRA_SKU_TYPE_584 = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MXL_HYDRA_SKU_TYPE_585 = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MXL_HYDRA_SKU_TYPE_544 = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MXL_HYDRA_SKU_TYPE_561 = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MXL_HYDRA_SKU_TYPE_5XX = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MXL_HYDRA_SKU_TYPE_5YY = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MXL_HYDRA_SKU_TYPE_511 = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MXL_HYDRA_SKU_TYPE_561_DE = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MXL_HYDRA_SKU_TYPE_582 = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MXL_HYDRA_SKU_TYPE_541 = 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MXL_HYDRA_SKU_TYPE_568 = 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MXL_HYDRA_SKU_TYPE_542 = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MXL_HYDRA_SKU_TYPE_MAX = 0x0D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct MXL_HYDRA_SKU_COMMAND_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) enum MXL_HYDRA_SKU_TYPE_E sku_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) enum MXL_HYDRA_DEMOD_ID_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MXL_HYDRA_DEMOD_ID_0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MXL_HYDRA_DEMOD_ID_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MXL_HYDRA_DEMOD_ID_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MXL_HYDRA_DEMOD_ID_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MXL_HYDRA_DEMOD_ID_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MXL_HYDRA_DEMOD_ID_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MXL_HYDRA_DEMOD_ID_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MXL_HYDRA_DEMOD_ID_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MXL_HYDRA_DEMOD_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MXL_DEMOD_SCRAMBLE_SEQ_LEN 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MAX_STEP_SIZE_24_XTAL_102_05_KHZ 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MAX_STEP_SIZE_24_XTAL_204_10_KHZ 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MAX_STEP_SIZE_24_XTAL_306_15_KHZ 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MAX_STEP_SIZE_24_XTAL_408_20_KHZ 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MAX_STEP_SIZE_27_XTAL_102_05_KHZ 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MAX_STEP_SIZE_27_XTAL_204_10_KHZ 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MAX_STEP_SIZE_27_XTAL_306_15_KHZ 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MAX_STEP_SIZE_27_XTAL_408_20_KHZ 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MXL_HYDRA_SPECTRUM_MIN_FREQ_KHZ 300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MXL_HYDRA_SPECTRUM_MAX_FREQ_KHZ 2350000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) enum MXL_DEMOD_CHAN_PARAMS_OFFSET_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) DMD_STANDARD_ADDR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) DMD_SPECTRUM_INVERSION_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DMD_SPECTRUM_ROLL_OFF_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) DMD_SYMBOL_RATE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DMD_MODULATION_SCHEME_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DMD_FEC_CODE_RATE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DMD_SNR_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DMD_FREQ_OFFSET_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) DMD_CTL_FREQ_OFFSET_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DMD_STR_FREQ_OFFSET_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) DMD_FTL_FREQ_OFFSET_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) DMD_STR_NBC_SYNC_LOCK_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DMD_CYCLE_SLIP_COUNT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DMD_DISPLAY_IQ_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DMD_DVBS2_CRC_ERRORS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) DMD_DVBS2_PER_COUNT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DMD_DVBS2_PER_WINDOW_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DMD_DVBS_CORR_RS_ERRORS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DMD_DVBS_UNCORR_RS_ERRORS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DMD_DVBS_BER_COUNT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) DMD_DVBS_BER_WINDOW_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DMD_TUNER_ID_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DMD_DVBS2_PILOT_ON_OFF_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) enum MXL_HYDRA_TUNER_ID_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MXL_HYDRA_TUNER_ID_0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MXL_HYDRA_TUNER_ID_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MXL_HYDRA_TUNER_ID_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MXL_HYDRA_TUNER_ID_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MXL_HYDRA_TUNER_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) enum MXL_HYDRA_BCAST_STD_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MXL_HYDRA_DSS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MXL_HYDRA_DVBS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MXL_HYDRA_DVBS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) enum MXL_HYDRA_FEC_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MXL_HYDRA_FEC_AUTO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MXL_HYDRA_FEC_1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MXL_HYDRA_FEC_3_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MXL_HYDRA_FEC_2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MXL_HYDRA_FEC_3_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MXL_HYDRA_FEC_4_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MXL_HYDRA_FEC_5_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MXL_HYDRA_FEC_6_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MXL_HYDRA_FEC_7_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MXL_HYDRA_FEC_8_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MXL_HYDRA_FEC_9_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) enum MXL_HYDRA_MODULATION_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MXL_HYDRA_MOD_AUTO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MXL_HYDRA_MOD_QPSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MXL_HYDRA_MOD_8PSK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) enum MXL_HYDRA_SPECTRUM_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) MXL_HYDRA_SPECTRUM_AUTO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MXL_HYDRA_SPECTRUM_INVERTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MXL_HYDRA_SPECTRUM_NON_INVERTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) enum MXL_HYDRA_ROLLOFF_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MXL_HYDRA_ROLLOFF_AUTO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MXL_HYDRA_ROLLOFF_0_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MXL_HYDRA_ROLLOFF_0_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MXL_HYDRA_ROLLOFF_0_35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) enum MXL_HYDRA_PILOTS_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MXL_HYDRA_PILOTS_OFF = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MXL_HYDRA_PILOTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MXL_HYDRA_PILOTS_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) enum MXL_HYDRA_CONSTELLATION_SRC_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MXL_HYDRA_FORMATTER = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MXL_HYDRA_LEGACY_FEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MXL_HYDRA_FREQ_RECOVERY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MXL_HYDRA_NBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MXL_HYDRA_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MXL_HYDRA_EQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct MXL_HYDRA_DEMOD_LOCK_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int agc_lock; /* AGC lock info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int fec_lock; /* Demod FEC block lock info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct MXL_HYDRA_DEMOD_STATUS_DVBS_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 rs_errors; /* RS decoder err counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 ber_window; /* Ber Windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 ber_count; /* BER count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 ber_window_iter1; /* Ber Windows - post viterbi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 ber_count_iter1; /* BER count - post viterbi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct MXL_HYDRA_DEMOD_STATUS_DSS_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 rs_errors; /* RS decoder err counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 ber_window; /* Ber Windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 ber_count; /* BER count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct MXL_HYDRA_DEMOD_STATUS_DVBS2_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u32 crc_errors; /* CRC error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u32 packet_error_count; /* Number of packet errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u32 total_packets; /* Total packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct MXL_HYDRA_DEMOD_STATUS_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) enum MXL_HYDRA_BCAST_STD_E standard_mask; /* Standard DVB-S, DVB-S2 or DSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct MXL_HYDRA_DEMOD_STATUS_DVBS_T demod_status_dvbs; /* DVB-S demod status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct MXL_HYDRA_DEMOD_STATUS_DVBS2_T demod_status_dvbs2; /* DVB-S2 demod status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct MXL_HYDRA_DEMOD_STATUS_DSS_T demod_status_dss; /* DSS demod status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct MXL_HYDRA_DEMOD_SIG_OFFSET_INFO_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) s32 carrier_offset_in_hz; /* CRL offset info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) s32 symbol_offset_in_symbol; /* SRL offset info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct MXL_HYDRA_DEMOD_SCRAMBLE_INFO_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 scramble_sequence[MXL_DEMOD_SCRAMBLE_SEQ_LEN]; /* scramble sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 scramble_code; /* scramble gold code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) enum MXL_HYDRA_SPECTRUM_STEP_SIZE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) enum MXL_HYDRA_SPECTRUM_RESOLUTION_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MXL_HYDRA_SPECTRUM_RESOLUTION_00_1_DB, /* 0.1 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MXL_HYDRA_SPECTRUM_RESOLUTION_01_0_DB, /* 1.0 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MXL_HYDRA_SPECTRUM_RESOLUTION_05_0_DB, /* 5.0 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MXL_HYDRA_SPECTRUM_RESOLUTION_10_0_DB, /* 10 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) enum MXL_HYDRA_SPECTRUM_ERROR_CODE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MXL_SPECTRUM_NO_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MXL_SPECTRUM_INVALID_PARAMETER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MXL_SPECTRUM_INVALID_STEP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MXL_SPECTRUM_BW_CANNOT_BE_COVERED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MXL_SPECTRUM_DEMOD_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MXL_SPECTRUM_TUNER_NOT_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct MXL_HYDRA_SPECTRUM_REQ_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 tuner_index; /* TUNER Ctrl: one of MXL58x_TUNER_ID_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 demod_index; /* DEMOD Ctrl: one of MXL58x_DEMOD_ID_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) enum MXL_HYDRA_SPECTRUM_STEP_SIZE_E step_size_in_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 starting_freq_ink_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 total_steps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) enum MXL_HYDRA_SPECTRUM_RESOLUTION_E spectrum_division;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) enum MXL_HYDRA_SEARCH_FREQ_OFFSET_TYPE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MXL_HYDRA_SEARCH_MAX_OFFSET = 0, /* DMD searches for max freq offset (i.e. 5MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MXL_HYDRA_SEARCH_BW_PLUS_ROLLOFF, /* DMD searches for BW + ROLLOFF/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct MXL58X_CFG_FREQ_OFF_SEARCH_RANGE_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 demod_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) enum MXL_HYDRA_SEARCH_FREQ_OFFSET_TYPE_E search_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* there are two slices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * slice0 - TS0, TS1, TS2 & TS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * slice1 - TS4, TS5, TS6 & TS7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define MXL_HYDRA_TS_SLICE_MAX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define MAX_FIXED_PID_NUM 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define MXL_HYDRA_NCO_CLK 418 /* 418 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define MXL_HYDRA_MAX_TS_CLOCK 139 /* 139 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define MXL_HYDRA_TS_FIXED_PID_FILT_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define MXL_HYDRA_SHARED_PID_FILT_SIZE_DEFAULT 33 /* Shared PID filter size in 1-1 mux mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define MXL_HYDRA_SHARED_PID_FILT_SIZE_2_TO_1 66 /* Shared PID filter size in 2-1 mux mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define MXL_HYDRA_SHARED_PID_FILT_SIZE_4_TO_1 132 /* Shared PID filter size in 4-1 mux mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) enum MXL_HYDRA_PID_BANK_TYPE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MXL_HYDRA_SOFTWARE_PID_BANK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MXL_HYDRA_HARDWARE_PID_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) enum MXL_HYDRA_TS_MUX_MODE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MXL_HYDRA_TS_MUX_PID_REMAP = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MXL_HYDRA_TS_MUX_PREFIX_EXTRA_HEADER = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) enum MXL_HYDRA_TS_MUX_TYPE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MXL_HYDRA_TS_MUX_DISABLE = 0, /* No Mux ( 1 TSIF to 1 TSIF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MXL_HYDRA_TS_MUX_2_TO_1, /* Mux 2 TSIF to 1 TSIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MXL_HYDRA_TS_MUX_4_TO_1, /* Mux 4 TSIF to 1 TSIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) enum MXL_HYDRA_TS_GROUP_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MXL_HYDRA_TS_GROUP_0_3 = 0, /* TS group 0 to 3 (TS0, TS1, TS2 & TS3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MXL_HYDRA_TS_GROUP_4_7, /* TS group 0 to 3 (TS4, TS5, TS6 & TS7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) enum MXL_HYDRA_TS_PID_FLT_CTRL_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MXL_HYDRA_TS_PIDS_ALLOW_ALL = 0, /* Allow all pids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MXL_HYDRA_TS_PIDS_DROP_ALL, /* Drop all pids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MXL_HYDRA_TS_INVALIDATE_PID_FILTER, /* Delete current PD filter in the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) enum MXL_HYDRA_TS_PID_TYPE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MXL_HYDRA_TS_PID_FIXED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MXL_HYDRA_TS_PID_REGULAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct MXL_HYDRA_TS_PID_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u16 original_pid; /* pid from TS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u16 remapped_pid; /* remapped pid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) enum MXL_BOOL_E enable; /* enable or disable pid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) enum MXL_BOOL_E allow_or_drop; /* allow or drop pid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) enum MXL_BOOL_E enable_pid_remap; /* enable or disable pid remap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 bond_id; /* Bond ID in A0 always 0 - Only for 568 Sku */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 dest_id; /* Output port ID for the PID - Only for 568 Sku */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct MXL_HYDRA_TS_MUX_PREFIX_HEADER_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) enum MXL_BOOL_E enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u8 num_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 header[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) enum MXL_HYDRA_PID_FILTER_BANK_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MXL_HYDRA_PID_BANK_A = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MXL_HYDRA_PID_BANK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) enum MXL_HYDRA_MPEG_DATA_FMT_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MXL_HYDRA_MPEG_SERIAL_MSB_1ST = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MXL_HYDRA_MPEG_SERIAL_LSB_1ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MXL_HYDRA_MPEG_SYNC_WIDTH_BIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MXL_HYDRA_MPEG_SYNC_WIDTH_BYTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) enum MXL_HYDRA_MPEG_MODE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MXL_HYDRA_MPEG_MODE_SERIAL_4_WIRE = 0, /* MPEG 4 Wire serial mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE, /* MPEG 3 Wire serial mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MXL_HYDRA_MPEG_MODE_SERIAL_2_WIRE, /* MPEG 2 Wire serial mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MXL_HYDRA_MPEG_MODE_PARALLEL /* MPEG parallel mode - valid only for MxL581 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) enum MXL_HYDRA_MPEG_CLK_TYPE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MXL_HYDRA_MPEG_CLK_CONTINUOUS = 0, /* Continuous MPEG clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MXL_HYDRA_MPEG_CLK_GAPPED, /* Gapped (gated) MPEG clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) enum MXL_HYDRA_MPEG_CLK_FMT_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MXL_HYDRA_MPEG_ACTIVE_LOW = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MXL_HYDRA_MPEG_ACTIVE_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MXL_HYDRA_MPEG_CLK_NEGATIVE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MXL_HYDRA_MPEG_CLK_POSITIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MXL_HYDRA_MPEG_CLK_IN_PHASE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MXL_HYDRA_MPEG_CLK_INVERTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) enum MXL_HYDRA_MPEG_CLK_PHASE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_90_DEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_180_DEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_270_DEG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) enum MXL_HYDRA_MPEG_ERR_INDICATION_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MXL_HYDRA_MPEG_ERR_REPLACE_SYNC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MXL_HYDRA_MPEG_ERR_REPLACE_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct MXL_HYDRA_MPEGOUT_PARAM_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int enable; /* Enable or Disable MPEG OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) enum MXL_HYDRA_MPEG_CLK_TYPE_E mpeg_clk_type; /* Continuous or gapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) enum MXL_HYDRA_MPEG_CLK_FMT_E mpeg_clk_pol; /* MPEG Clk polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u8 max_mpeg_clk_rate; /* Max MPEG Clk rate (0 - 104 MHz, 139 MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) enum MXL_HYDRA_MPEG_CLK_PHASE_E mpeg_clk_phase; /* MPEG Clk phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) enum MXL_HYDRA_MPEG_DATA_FMT_E lsb_or_msb_first; /* LSB first or MSB first in TS transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) enum MXL_HYDRA_MPEG_DATA_FMT_E mpeg_sync_pulse_width; /* MPEG SYNC pulse width (1-bit or 1-byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) enum MXL_HYDRA_MPEG_CLK_FMT_E mpeg_valid_pol; /* MPEG VALID polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) enum MXL_HYDRA_MPEG_CLK_FMT_E mpeg_sync_pol; /* MPEG SYNC polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) enum MXL_HYDRA_MPEG_MODE_E mpeg_mode; /* config 4/3/2-wire serial or parallel TS out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) enum MXL_HYDRA_MPEG_ERR_INDICATION_E mpeg_error_indication; /* Enable or Disable MPEG error indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) enum MXL_HYDRA_EXT_TS_IN_ID_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MXL_HYDRA_EXT_TS_IN_0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MXL_HYDRA_EXT_TS_IN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) MXL_HYDRA_EXT_TS_IN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) MXL_HYDRA_EXT_TS_IN_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) MXL_HYDRA_EXT_TS_IN_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) enum MXL_HYDRA_TS_OUT_ID_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) MXL_HYDRA_TS_OUT_0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MXL_HYDRA_TS_OUT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) MXL_HYDRA_TS_OUT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MXL_HYDRA_TS_OUT_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) MXL_HYDRA_TS_OUT_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MXL_HYDRA_TS_OUT_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) MXL_HYDRA_TS_OUT_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) MXL_HYDRA_TS_OUT_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) MXL_HYDRA_TS_OUT_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) enum MXL_HYDRA_TS_DRIVE_STRENGTH_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MXL_HYDRA_TS_DRIVE_STRENGTH_1X = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MXL_HYDRA_TS_DRIVE_STRENGTH_2X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MXL_HYDRA_TS_DRIVE_STRENGTH_3X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MXL_HYDRA_TS_DRIVE_STRENGTH_4X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MXL_HYDRA_TS_DRIVE_STRENGTH_5X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MXL_HYDRA_TS_DRIVE_STRENGTH_6X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MXL_HYDRA_TS_DRIVE_STRENGTH_7X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MXL_HYDRA_TS_DRIVE_STRENGTH_8X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) enum MXL_HYDRA_DEVICE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MXL_HYDRA_DEVICE_581 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MXL_HYDRA_DEVICE_584,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MXL_HYDRA_DEVICE_585,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) MXL_HYDRA_DEVICE_544,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MXL_HYDRA_DEVICE_561,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) MXL_HYDRA_DEVICE_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) MXL_HYDRA_DEVICE_582,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MXL_HYDRA_DEVICE_541,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MXL_HYDRA_DEVICE_568,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MXL_HYDRA_DEVICE_542,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) MXL_HYDRA_DEVICE_541S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) MXL_HYDRA_DEVICE_561S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) MXL_HYDRA_DEVICE_581S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) MXL_HYDRA_DEVICE_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* Demod IQ data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct MXL_HYDRA_DEMOD_IQ_SRC_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 demod_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 source_of_iq; /* == 0, it means I/Q comes from Formatter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * == 1, Legacy FEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * == 2, Frequency Recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * == 3, NBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * == 4, CTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * == 5, EQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * == 6, FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct MXL_HYDRA_DEMOD_ABORT_TUNE_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 demod_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct MXL_HYDRA_TUNER_CMD {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u8 tuner_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u8 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Demod Para for Channel Tune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct MXL_HYDRA_DEMOD_PARAM_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 tuner_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 demod_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 frequency_in_hz; /* Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 standard; /* one of MXL_HYDRA_BCAST_STD_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 spectrum_inversion; /* Input : Spectrum inversion. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u32 roll_off; /* rollOff (alpha) factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u32 symbol_rate_in_hz; /* Symbol rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u32 pilots; /* TRUE = pilots enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u32 modulation_scheme; /* Input : Modulation Scheme is one of MXL_HYDRA_MODULATION_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 fec_code_rate; /* Input : Forward error correction rate. Is one of MXL_HYDRA_FEC_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u32 max_carrier_offset_in_mhz; /* Maximum carrier freq offset in MHz. Same as freqSearchRangeKHz, but in unit of MHz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct MXL_HYDRA_DEMOD_SCRAMBLE_CODE_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u32 demod_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u8 scramble_sequence[12]; /* scramble sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u32 scramble_code; /* scramble gold code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct MXL_INTR_CFG_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 intr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u32 intr_duration_in_nano_secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u32 intr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct MXL_HYDRA_POWER_MODE_CMD {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u8 power_mode; /* enumeration values are defined in MXL_HYDRA_PWR_MODE_E (device API.h) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct MXL_HYDRA_RF_WAKEUP_PARAM_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u32 time_interval_in_seconds; /* in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 tuner_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) s32 rssi_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct MXL_HYDRA_RF_WAKEUP_CFG_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 tuner_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct MXL_HYDRA_RF_WAKEUP_PARAM_T params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) enum MXL_HYDRA_AUX_CTRL_MODE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) MXL_HYDRA_AUX_CTRL_MODE_FSK = 0, /* Select FSK controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MXL_HYDRA_AUX_CTRL_MODE_DISEQC, /* Select DiSEqC controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) enum MXL_HYDRA_DISEQC_OPMODE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) MXL_HYDRA_DISEQC_ENVELOPE_MODE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) MXL_HYDRA_DISEQC_TONE_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) enum MXL_HYDRA_DISEQC_VER_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) MXL_HYDRA_DISEQC_1_X = 0, /* Config DiSEqC 1.x mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) MXL_HYDRA_DISEQC_2_X, /* Config DiSEqC 2.x mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) MXL_HYDRA_DISEQC_DISABLE /* Disable DiSEqC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) enum MXL_HYDRA_DISEQC_CARRIER_FREQ_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) MXL_HYDRA_DISEQC_CARRIER_FREQ_22KHZ = 0, /* DiSEqC signal frequency of 22 KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) MXL_HYDRA_DISEQC_CARRIER_FREQ_33KHZ, /* DiSEqC signal frequency of 33 KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) MXL_HYDRA_DISEQC_CARRIER_FREQ_44KHZ /* DiSEqC signal frequency of 44 KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) enum MXL_HYDRA_DISEQC_ID_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) MXL_HYDRA_DISEQC_ID_0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) MXL_HYDRA_DISEQC_ID_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) MXL_HYDRA_DISEQC_ID_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) MXL_HYDRA_DISEQC_ID_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) enum MXL_HYDRA_FSK_OP_MODE_E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) MXL_HYDRA_FSK_CFG_TYPE_39KPBS = 0, /* 39.0kbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) MXL_HYDRA_FSK_CFG_TYPE_39_017KPBS, /* 39.017kbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) MXL_HYDRA_FSK_CFG_TYPE_115_2KPBS /* 115.2kbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct MXL58X_DSQ_OP_MODE_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u32 diseqc_id; /* DSQ 0, 1, 2 or 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u32 op_mode; /* Envelope mode (0) or internal tone mode (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u32 version; /* 0: 1.0, 1: 1.1, 2: Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u32 center_freq; /* 0: 22KHz, 1: 33KHz and 2: 44 KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct MXL_HYDRA_DISEQC_CFG_CONT_TONE_T {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u32 diseqc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u32 cont_tone_flag; /* 1: Enable , 0: Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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