Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Driver for Zarlink DVB-T MT352 demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Written by Holger Waechtler <holger@qanu.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	 and Daniel Mack <daniel@qanu.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  AVerMedia AVerTV DVB-T 771 support by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *       Wolfram Joost <dbox2@frokaschwei.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  Support for Samsung TDTC9251DH01C(M) tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *                     Amauri  Celani  <acelani@essegi.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *  DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *       Christopher Pascoe <c.pascoe@itee.uq.edu.au>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #ifndef _MT352_PRIV_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define _MT352_PRIV_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ID_MT352        0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define msb(x) (((x) >> 8) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define lsb(x) ((x) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) enum mt352_reg_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	STATUS_0           = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	STATUS_1           = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	STATUS_2           = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	STATUS_3           = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	STATUS_4           = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	INTERRUPT_0        = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	INTERRUPT_1        = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	INTERRUPT_2        = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	INTERRUPT_3        = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	SNR                = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	VIT_ERR_CNT_2      = 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	VIT_ERR_CNT_1      = 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	VIT_ERR_CNT_0      = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	RS_ERR_CNT_2       = 0x0D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	RS_ERR_CNT_1       = 0x0E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	RS_ERR_CNT_0       = 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	RS_UBC_1           = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	RS_UBC_0           = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	AGC_GAIN_3         = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	AGC_GAIN_2         = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	AGC_GAIN_1         = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	AGC_GAIN_0         = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	FREQ_OFFSET_2      = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	FREQ_OFFSET_1      = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	FREQ_OFFSET_0      = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	TIMING_OFFSET_1    = 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	TIMING_OFFSET_0    = 0x1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	CHAN_FREQ_1        = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	CHAN_FREQ_0        = 0x1D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	TPS_RECEIVED_1     = 0x1E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	TPS_RECEIVED_0     = 0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	TPS_CURRENT_1      = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	TPS_CURRENT_0      = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	TPS_CELL_ID_1      = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	TPS_CELL_ID_0      = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	TPS_MISC_DATA_2    = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	TPS_MISC_DATA_1    = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	TPS_MISC_DATA_0    = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	RESET              = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	TPS_GIVEN_1        = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	TPS_GIVEN_0        = 0x52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ACQ_CTL            = 0x53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	TRL_NOMINAL_RATE_1 = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	TRL_NOMINAL_RATE_0 = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	INPUT_FREQ_1       = 0x56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	INPUT_FREQ_0       = 0x57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	TUNER_ADDR         = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	CHAN_START_1       = 0x59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	CHAN_START_0       = 0x5A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	CONT_1             = 0x5B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	CONT_0             = 0x5C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	TUNER_GO           = 0x5D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	STATUS_EN_0        = 0x5F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	STATUS_EN_1        = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	INTERRUPT_EN_0     = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	INTERRUPT_EN_1     = 0x62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	INTERRUPT_EN_2     = 0x63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	INTERRUPT_EN_3     = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	AGC_TARGET         = 0x67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	AGC_CTL            = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	CAPT_RANGE         = 0x75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	SNR_SELECT_1       = 0x79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	SNR_SELECT_0       = 0x7A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	RS_ERR_PER_1       = 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	RS_ERR_PER_0       = 0x7D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	CHIP_ID            = 0x7F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	CHAN_STOP_1        = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	CHAN_STOP_0        = 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	CHAN_STEP_1        = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	CHAN_STEP_0        = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	FEC_LOCK_TIME      = 0x85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	OFDM_LOCK_TIME     = 0x86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	ACQ_DELAY          = 0x87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	SCAN_CTL           = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	CLOCK_CTL          = 0x89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	CONFIG             = 0x8A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	MCLK_RATIO         = 0x8B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	GPP_CTL            = 0x8C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	ADC_CTL_1          = 0x8E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	ADC_CTL_0          = 0x8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* here we assume 1/6MHz == 166.66kHz stepsize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IF_FREQUENCYx6 217    /* 6 * 36.16666666667MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif                          /* _MT352_PRIV_ */