^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Zarlink DVB-T MT352 demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Written by Holger Waechtler <holger@qanu.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * and Daniel Mack <daniel@qanu.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * AVerMedia AVerTV DVB-T 771 support by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Wolfram Joost <dbox2@frokaschwei.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Support for Samsung TDTC9251DH01C(M) tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Amauri Celani <acelani@essegi.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Christopher Pascoe <c.pascoe@itee.uq.edu.au>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "mt352_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "mt352.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct mt352_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct mt352_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (debug) printk(KERN_DEBUG "mt352: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct mt352_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 buf[2] = { reg, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int err = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (err != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int _mt352_write(struct dvb_frontend* fe, const u8 ibuf[], int ilen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int err,i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) for (i=0; i < ilen-1; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int mt352_read_register(struct mt352_state* state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 b0 [] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 b1 [] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct i2c_msg msg [] = { { .addr = state->config.demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .buf = b0, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { .addr = state->config.demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .buf = b1, .len = 1 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ret = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) printk("%s: readreg error (reg=%d, ret==%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int mt352_sleep(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) _mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void mt352_calc_nominal_rate(struct mt352_state* state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 adc_clock = 20480; /* 20.340 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 bw,value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) switch (bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bw = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bw = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bw = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (state->config.adc_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) adc_clock = state->config.adc_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) value = 64 * bw * (1<<16) / (7 * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) value = value * 1000 / adc_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __func__, bw, adc_clock, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) buf[0] = msb(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) buf[1] = lsb(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void mt352_calc_input_freq(struct mt352_state* state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int adc_clock = 20480; /* 20.480000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int if2 = 36167; /* 36.166667 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int ife,value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (state->config.adc_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) adc_clock = state->config.adc_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (state->config.if2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if2 = state->config.if2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (adc_clock >= if2 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ife = if2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ife = adc_clock - (if2 % adc_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (ife > adc_clock / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ife = adc_clock - ife;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) value = -16374 * ife / adc_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __func__, if2, ife, adc_clock, value, value & 0x3fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) buf[0] = msb(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) buf[1] = lsb(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int mt352_set_parameters(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct dtv_frontend_properties *op = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct mt352_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned char buf[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static unsigned char tuner_go[] = { 0x5d, 0x01 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static unsigned char fsm_go[] = { 0x5e, 0x01 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int tps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) switch (op->code_rate_HP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) tps |= (1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) tps |= (2 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) tps |= (3 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) tps |= (4 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case FEC_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) switch (op->code_rate_LP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) tps |= (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) tps |= (2 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tps |= (3 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) tps |= (4 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case FEC_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case FEC_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (op->hierarchy == HIERARCHY_AUTO ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) op->hierarchy == HIERARCHY_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) switch (op->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case QPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case QAM_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) tps |= (1 << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tps |= (2 << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) switch (op->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case TRANSMISSION_MODE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case TRANSMISSION_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) tps |= (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) switch (op->guard_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case GUARD_INTERVAL_1_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case GUARD_INTERVAL_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case GUARD_INTERVAL_1_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tps |= (1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case GUARD_INTERVAL_1_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) tps |= (2 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case GUARD_INTERVAL_1_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) tps |= (3 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) switch (op->hierarchy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case HIERARCHY_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case HIERARCHY_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case HIERARCHY_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) tps |= (1 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case HIERARCHY_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) tps |= (2 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case HIERARCHY_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) tps |= (3 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) buf[1] = msb(tps); /* TPS_GIVEN_(1|0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) buf[2] = lsb(tps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) buf[3] = 0x50; // old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) // buf[3] = 0xf4; // pinnacle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mt352_calc_nominal_rate(state, op->bandwidth_hz, buf+4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mt352_calc_input_freq(state, buf+6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (state->config.no_tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) _mt352_write(fe, buf, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) _mt352_write(fe, fsm_go, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (fe->ops.tuner_ops.calc_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) fe->ops.tuner_ops.calc_regs(fe, buf+8, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) buf[8] <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) _mt352_write(fe, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) _mt352_write(fe, tuner_go, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int mt352_get_parameters(struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct dtv_frontend_properties *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct mt352_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u16 tps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u16 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u8 trl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const u8 tps_fec_to_api[8] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) FEC_1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) FEC_2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) FEC_3_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) FEC_5_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) FEC_7_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) FEC_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) FEC_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) FEC_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * the mt352 sometimes works with the wrong parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) switch ( (tps >> 13) & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) op->modulation = QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) op->modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) op->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) op->modulation = QAM_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) switch ( (tps >> 2) & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) op->guard_interval = GUARD_INTERVAL_1_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) op->guard_interval = GUARD_INTERVAL_1_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) op->guard_interval = GUARD_INTERVAL_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) op->guard_interval = GUARD_INTERVAL_1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) op->guard_interval = GUARD_INTERVAL_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) switch ( (tps >> 10) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) op->hierarchy = HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) op->hierarchy = HIERARCHY_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) op->hierarchy = HIERARCHY_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) op->hierarchy = HIERARCHY_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) op->hierarchy = HIERARCHY_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) op->frequency = (500 * (div - IF_FREQUENCYx6)) / 3 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (trl == 0x72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) op->bandwidth_hz = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) else if (trl == 0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) op->bandwidth_hz = 7000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) op->bandwidth_hz = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (mt352_read_register(state, STATUS_2) & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) op->inversion = INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) op->inversion = INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int mt352_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct mt352_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int s0, s1, s3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* FIXME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * The MT352 design manual from Zarlink states (page 46-47):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * Notes about the TUNER_GO register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * byte is copied from the tuner to the STATUS_3 register and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * completion of the read operation is indicated by bit-5 of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * INTERRUPT_3 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (s0 & (1 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (s0 & (1 << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) *status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (s0 & (1 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (s1 & (1 << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (s3 & (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) *status &= ~FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct mt352_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) (mt352_read_register (state, RS_ERR_CNT_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct mt352_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* align the 12 bit AGC gain with the most significant bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) (mt352_read_register(state, AGC_GAIN_0) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* inverse of gain is signal strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) *strength = ~signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct mt352_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u8 _snr = mt352_read_register (state, SNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) *snr = (_snr << 8) | _snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct mt352_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) *ucblocks = (mt352_read_register (state, RS_UBC_1) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) (mt352_read_register (state, RS_UBC_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) fe_tune_settings->min_delay_ms = 800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) fe_tune_settings->step_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) fe_tune_settings->max_drift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int mt352_init(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct mt352_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static u8 mt352_reset_attach [] = { RESET, 0xC0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dprintk("%s: hello\n",__func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) (mt352_read_register(state, CONFIG) & 0x20) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Do a "hard" reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) _mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return state->config.demod_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static void mt352_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct mt352_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct dvb_frontend_ops mt352_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct dvb_frontend* mt352_attach(const struct mt352_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct i2c_adapter* i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct mt352_state* state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (state == NULL) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) memcpy(&state->config,config,sizeof(struct mt352_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const struct dvb_frontend_ops mt352_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .name = "Zarlink MT352 DVB-T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .frequency_min_hz = 174 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .frequency_max_hz = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .frequency_stepsize_hz = 166667,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) FE_CAN_MUTE_TS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .release = mt352_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .init = mt352_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .sleep = mt352_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .write = _mt352_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .set_frontend = mt352_set_parameters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .get_frontend = mt352_get_parameters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .get_tune_settings = mt352_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .read_status = mt352_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .read_ber = mt352_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .read_signal_strength = mt352_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .read_snr = mt352_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .read_ucblocks = mt352_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) EXPORT_SYMBOL(mt352_attach);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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