^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Driver for Zarlink VP310/MT312/ZL10313 Satellite Channel Decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 2008 Matthias Schwarzott <zzam@gentoo.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) References:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) http://products.zarlink.com/product_profiles/MT312.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) http://products.zarlink.com/product_profiles/SL1935.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "mt312_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "mt312.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Max transfer size done by I2C transfer functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MAX_XFER_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct mt312_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) const struct mt312_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned long xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 freq_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) printk(KERN_DEBUG "mt312: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MT312_PLL_CLK 10000000UL /* 10 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MT312_PLL_CLK_10_111 10111000UL /* 10.111 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 *buf, const size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 regbuf[1] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) msg[0].addr = state->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) msg[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) msg[0].buf = regbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) msg[0].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) msg[1].addr = state->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) msg[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) msg[1].len = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ret = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (debug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dprintk("R(%d):", reg & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) printk(KERN_CONT " %02x", buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const u8 *src, const size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 buf[MAX_XFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (1 + count > sizeof(buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "mt312: write: len=%zu is too big!\n", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (debug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dprintk("W(%d):", reg & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) printk(KERN_CONT " %02x", src[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) buf[0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) memcpy(&buf[1], src, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) msg.addr = state->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) msg.len = count + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dprintk("%s: ret == %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline int mt312_readreg(struct mt312_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const enum mt312_reg_addr reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return mt312_read(state, reg, val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline int mt312_writereg(struct mt312_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const enum mt312_reg_addr reg, const u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return mt312_write(state, reg, &tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int mt312_reset(struct mt312_state *state, const u8 full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int mt312_get_inversion(struct mt312_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum fe_spectral_inversion *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 vit_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = mt312_readreg(state, VIT_MODE, &vit_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (vit_mode & 0x80) /* auto inversion was used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 sym_rate_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 dec_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u16 sym_rat_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u16 monitor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (sym_rate_h & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* symbol rate search was used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ret = mt312_writereg(state, MON_CTRL, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) monitor = (buf[0] << 8) | buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dprintk("sr(auto) = %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DIV_ROUND_CLOSEST(monitor * 15625, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = mt312_writereg(state, MON_CTRL, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) sym_rat_op = (buf[0] << 8) | buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dprintk("sym_rat_op=%d dec_ratio=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) sym_rat_op, dec_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dprintk("*sr(manual) = %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) (((state->xtal * 8192) / (sym_rat_op + 8192)) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 2) - dec_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int mt312_get_code_rate(struct mt312_state *state, enum fe_code_rate *cr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) const enum fe_code_rate fec_tab[8] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) FEC_AUTO, FEC_AUTO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u8 fec_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = mt312_readreg(state, FEC_STATUS, &fec_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *cr = fec_tab[(fec_status >> 4) & 0x07];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int mt312_initfe(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* wake up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = mt312_writereg(state, CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) (state->freq_mult == 6 ? 0x88 : 0x8c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* wait at least 150 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* full reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = mt312_reset(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Per datasheet, write correct values. 09/28/03 ACCJr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 0x01, 0x00, 0x00, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) switch (state->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case ID_ZL10313:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* enable ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = mt312_writereg(state, GPP_CTRL, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* configure ZL10313 for optimal ADC performance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) buf[0] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) buf[1] = 0xB0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = mt312_write(state, HW_CTRL, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* enable MPEG output and ADCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ret = mt312_writereg(state, HW_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret = mt312_writereg(state, MPEG_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* SYS_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) buf[0] = DIV_ROUND_CLOSEST(state->xtal * state->freq_mult * 2, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* DISEQC_RATIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) buf[1] = DIV_ROUND_CLOSEST(state->xtal, 22000 * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* different MOCLK polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) switch (state->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case ID_ZL10313:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) buf[0] = 0x33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) buf[0] = 0x53;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = mt312_writereg(state, OP_CTRL, buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* TS_SW_LIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) buf[0] = 0x8c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) buf[1] = 0x98;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = mt312_writereg(state, CS_SW_LIM, 0x69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int mt312_send_master_cmd(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct dvb_diseqc_master_cmd *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u8 diseqc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = mt312_writereg(state, DISEQC_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) | 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* is there a better way to wait for message to be transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* set DISEQC_MODE[2:0] to zero if a return message is expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (c->msg[0] & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int mt312_send_burst(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const enum fe_sec_mini_cmd c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) const u8 mini_tab[2] = { 0x02, 0x03 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 diseqc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (c > SEC_MINI_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = mt312_writereg(state, DISEQC_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) (diseqc_mode & 0x40) | mini_tab[c]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int mt312_set_tone(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) const enum fe_sec_tone_mode t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) const u8 tone_tab[2] = { 0x01, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u8 diseqc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (t > SEC_TONE_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = mt312_writereg(state, DISEQC_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) (diseqc_mode & 0x40) | tone_tab[t]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int mt312_set_voltage(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) const enum fe_sec_voltage v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (v > SEC_VOLTAGE_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) val = volt_tab[v];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (state->config->voltage_inverted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) val ^= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return mt312_writereg(state, DISEQC_MODE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int mt312_read_status(struct dvb_frontend *fe, enum fe_status *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u8 status[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *s = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) status[0], status[1], status[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (status[0] & 0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) *s |= FE_HAS_SIGNAL; /* signal noise ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (status[0] & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *s |= FE_HAS_CARRIER; /* qpsk carrier lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (status[2] & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) *s |= FE_HAS_VITERBI; /* viterbi lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (status[2] & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *s |= FE_HAS_SYNC; /* byte align lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (status[0] & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) *s |= FE_HAS_LOCK; /* qpsk lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = mt312_read(state, RS_BERCNT_H, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int mt312_read_signal_strength(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u16 *signal_strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u16 agc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) s16 err_db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = mt312_read(state, AGC_H, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) agc = (buf[0] << 6) | (buf[1] >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) *signal_strength = agc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dprintk("agc=%08x err_db=%hd\n", agc, err_db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) *ubc = (buf[0] << 8) | buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int mt312_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u8 buf[5], config_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u16 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) const u8 fec_tab[10] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dprintk("%s: Freq %d\n", __func__, p->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if ((p->frequency < fe->ops.info.frequency_min_hz / kHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) || (p->frequency > fe->ops.info.frequency_max_hz / kHz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (((int)p->inversion < INVERSION_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) || (p->inversion > INVERSION_ON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if ((p->symbol_rate < fe->ops.info.symbol_rate_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) || (p->symbol_rate > fe->ops.info.symbol_rate_max))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (((int)p->fec_inner < FEC_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) || (p->fec_inner > FEC_AUTO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if ((p->fec_inner == FEC_4_5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) || (p->fec_inner == FEC_8_9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) switch (state->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case ID_VP310:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* For now we will do this only for the VP310.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * It should be better for the mt312 as well,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * but tuning will be slower. ACCJr 09/29/03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = mt312_readreg(state, CONFIG, &config_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (p->symbol_rate >= 30000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Note that 30MS/s should use 90MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (state->freq_mult == 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* We are running 60MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) state->freq_mult = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = mt312_initfe(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (state->freq_mult == 9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* We are running 90MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) state->freq_mult = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = mt312_initfe(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case ID_MT312:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) case ID_ZL10313:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* sr = (u16)(sr * 256.0 / 1000000.0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) sr = DIV_ROUND_CLOSEST(p->symbol_rate * 4, 15625);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* SYM_RATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) buf[0] = (sr >> 8) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) buf[1] = (sr >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* VIT_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) buf[2] = inv_tab[p->inversion] | fec_tab[p->fec_inner];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* QPSK_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) buf[3] = 0x40; /* swap I and Q before QPSK demodulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (p->symbol_rate < 10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) buf[3] |= 0x04; /* use afc mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* GO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) buf[4] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = mt312_reset(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int mt312_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ret = mt312_get_inversion(state, &p->inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ret = mt312_get_symbol_rate(state, &p->symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ret = mt312_get_code_rate(state, &p->fec_inner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u8 val = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) switch (state->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case ID_ZL10313:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ret = mt312_readreg(state, GPP_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* preserve this bit to not accidentally shutdown ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) val &= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) val |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) val &= ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret = mt312_writereg(state, GPP_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int mt312_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u8 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* reset all registers to defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret = mt312_reset(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (state->id == ID_ZL10313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* reset ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ret = mt312_writereg(state, GPP_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* full shutdown of ADCs, mpeg bus tristated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = mt312_writereg(state, HW_CTRL, 0x0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ret = mt312_readreg(state, CONFIG, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* enter standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ret = mt312_writereg(state, CONFIG, config & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int mt312_get_tune_settings(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct dvb_frontend_tune_settings *fesettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) fesettings->min_delay_ms = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) fesettings->step_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) fesettings->max_drift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static void mt312_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct mt312_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define MT312_SYS_CLK 90000000UL /* 90 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const struct dvb_frontend_ops mt312_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .delsys = { SYS_DVBS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .name = "Zarlink ???? DVB-S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .frequency_min_hz = 950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* FIXME: adjust freq to real used xtal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .frequency_stepsize_hz = MT312_PLL_CLK / 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .symbol_rate_max = MT312_SYS_CLK / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .caps =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) FE_CAN_RECOVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .release = mt312_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .init = mt312_initfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .sleep = mt312_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .i2c_gate_ctrl = mt312_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .set_frontend = mt312_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .get_frontend = mt312_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .get_tune_settings = mt312_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .read_status = mt312_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .read_ber = mt312_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .read_signal_strength = mt312_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .read_snr = mt312_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .read_ucblocks = mt312_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .diseqc_send_master_cmd = mt312_send_master_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .diseqc_send_burst = mt312_send_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .set_tone = mt312_set_tone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .set_voltage = mt312_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct dvb_frontend *mt312_attach(const struct mt312_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct mt312_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (mt312_readreg(state, ID, &state->id) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) memcpy(&state->frontend.ops, &mt312_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) switch (state->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case ID_VP310:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) strscpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) sizeof(state->frontend.ops.info.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) state->xtal = MT312_PLL_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) state->freq_mult = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case ID_MT312:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) strscpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) sizeof(state->frontend.ops.info.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) state->xtal = MT312_PLL_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) state->freq_mult = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) case ID_ZL10313:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) strscpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) sizeof(state->frontend.ops.info.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) state->xtal = MT312_PLL_CLK_10_111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) state->freq_mult = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313 are supported chips.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) EXPORT_SYMBOL(mt312_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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