^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2013 Mauro Carvalho Chehab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "mb86a20s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define NUM_LAYERS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum mb86a20s_bandwidth {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MB86A20S_13SEG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MB86A20S_13SEG_PARTIAL = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MB86A20S_1SEG = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MB86A20S_3SEG = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static u8 mb86a20s_subchannel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 0xb0, 0xc0, 0xd0, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 0xf0, 0x00, 0x10, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct mb86a20s_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) const struct mb86a20s_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 last_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum mb86a20s_bandwidth bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) bool inversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 subchannel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 estimated_rate[NUM_LAYERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned long get_strength_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) bool need_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct regdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BER_SAMPLING_RATE 1 /* Seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Initialization sequence: Use whatevere default values that PV SBTVD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * does on its initialisation, obtained via USB snoop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct regdata mb86a20s_init1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { 0x70, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { 0x70, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { 0x08, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { 0x50, 0xd1 }, { 0x51, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct regdata mb86a20s_init2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { 0x50, 0xd1 }, { 0x51, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 0x39, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 0x71, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { 0x3b, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { 0x3c, 0x3a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { 0x01, 0x0d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { 0x04, 0x08 }, { 0x05, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { 0x04, 0x0e }, { 0x05, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 0x04, 0x0f }, { 0x05, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { 0x04, 0x0b }, { 0x05, 0x8c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 0x04, 0x00 }, { 0x05, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 0x04, 0x01 }, { 0x05, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 0x04, 0x02 }, { 0x05, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { 0x04, 0x03 }, { 0x05, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 0x04, 0x09 }, { 0x05, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { 0x04, 0x0a }, { 0x05, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 0x04, 0x27 }, { 0x05, 0x64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 0x04, 0x28 }, { 0x05, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 0x04, 0x1e }, { 0x05, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 0x04, 0x29 }, { 0x05, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { 0x04, 0x32 }, { 0x05, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 0x04, 0x14 }, { 0x05, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { 0x04, 0x04 }, { 0x05, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { 0x04, 0x05 }, { 0x05, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { 0x04, 0x06 }, { 0x05, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { 0x04, 0x07 }, { 0x05, 0xd8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { 0x04, 0x12 }, { 0x05, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { 0x04, 0x13 }, { 0x05, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * On this demod, when the bit count reaches the count below,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * it collects the bit error count. The bit counters are initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * to 65535 here. This warrants that all of them will be quickly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * calculated when device gets locked. As TMCC is parsed, the values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * will be adjusted later in the driver's code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { 0x52, 0x01 }, /* Turn on BER before Viterbi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 0x50, 0xa7 }, { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0x50, 0xa8 }, { 0x51, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 0x50, 0xa9 }, { 0x51, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { 0x50, 0xaa }, { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { 0x50, 0xab }, { 0x51, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { 0x50, 0xac }, { 0x51, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { 0x50, 0xad }, { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { 0x50, 0xae }, { 0x51, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { 0x50, 0xaf }, { 0x51, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * On this demod, post BER counts blocks. When the count reaches the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * value below, it collects the block error count. The block counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * are initialized to 127 here. This warrants that all of them will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * quickly calculated when device gets locked. As TMCC is parsed, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * values will be adjusted later in the driver's code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 0x50, 0xdc }, { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0x50, 0xdd }, { 0x51, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0x50, 0xde }, { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 0x50, 0xdf }, { 0x51, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 0x50, 0xe0 }, { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 0x50, 0xe1 }, { 0x51, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * On this demod, when the block count reaches the count below,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * it collects the block error count. The block counters are initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * to 127 here. This warrants that all of them will be quickly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * calculated when device gets locked. As TMCC is parsed, the values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * will be adjusted later in the driver's code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 0x50, 0xb2 }, { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { 0x50, 0xb3 }, { 0x51, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { 0x50, 0xb4 }, { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { 0x50, 0xb5 }, { 0x51, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { 0x50, 0xb6 }, { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { 0x50, 0xb7 }, { 0x51, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { 0x45, 0x04 }, /* CN symbol 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { 0x48, 0x04 }, /* CN manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { 0x50, 0xd5 }, { 0x51, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { 0x50, 0xd6 }, { 0x51, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { 0x50, 0xd2 }, { 0x51, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { 0x50, 0xd7 }, { 0x51, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { 0x1c, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { 0x50, 0x1e }, { 0x51, 0x5d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { 0x50, 0x22 }, { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { 0x50, 0x23 }, { 0x51, 0xc8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 0x50, 0x24 }, { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { 0x50, 0x25 }, { 0x51, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { 0x50, 0x26 }, { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { 0x50, 0x27 }, { 0x51, 0xc3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 0x50, 0x39 }, { 0x51, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 0x50, 0xd5 }, { 0x51, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 0xd0, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct regdata mb86a20s_reset_reception[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 0x70, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 0x70, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 0x08, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 0x08, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct regdata mb86a20s_per_ber_reset[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { 0x53, 0x00 }, /* pre BER Counter reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { 0x53, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { 0x5f, 0x00 }, /* post BER Counter reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 0x5f, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { 0x50, 0xb1 }, /* PER Counter reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 0x51, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * I2C read/write functions and macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 i2c_addr, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 buf[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) rc = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (rc != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_err(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __func__, rc, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 i2c_addr, struct regdata *rd, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) rd[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 i2c_addr, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) rc = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (rc != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __func__, reg, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return (rc < 0) ? rc : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define mb86a20s_readreg(state, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define mb86a20s_writereg(state, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define mb86a20s_writeregdata(state, regdata) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) regdata, ARRAY_SIZE(regdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * Ancillary internal routines (likely compiled inlined)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * The functions below assume that gateway lock has already obtained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int mb86a20s_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) val = mb86a20s_readreg(state, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) val &= 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (val >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (val >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (val >= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) *status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (val >= 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Actually, on state S8, it starts receiving TS, but the TS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * output is only on normal state after the transition to S9.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (val >= 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) __func__, *status, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned rf_max, rf_min, rf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (state->get_strength_time &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) (!time_after(jiffies, state->get_strength_time)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return c->strength.stat[0].uvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Reset its value if an error happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) c->strength.stat[0].uvalue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Does a binary search to get RF strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) rf_max = 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) rf_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) rf = (rf_max + rf_min) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) rc = mb86a20s_writereg(state, 0x04, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) rc = mb86a20s_writereg(state, 0x05, rf >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) rc = mb86a20s_writereg(state, 0x04, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) rc = mb86a20s_writereg(state, 0x05, rf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) rc = mb86a20s_readreg(state, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (rc & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) rf_min = (rf_max + rf_min) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) rf_max = (rf_max + rf_min) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (rf_max - rf_min < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) rf = (rf_max + rf_min) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Rescale it from 2^12 (4096) to 2^16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) rf = rf << (16 - 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (rf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) rf |= (1 << 12) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "%s: signal strength = %d (%d < RF=%d < %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) __func__, rf, rf_min, rf >> 4, rf_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) c->strength.stat[0].uvalue = rf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) state->get_strength_time = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int mb86a20s_get_modulation(struct mb86a20s_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned layer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static unsigned char reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [0] = 0x86, /* Layer A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) [1] = 0x8a, /* Layer B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) [2] = 0x8e, /* Layer C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (layer >= ARRAY_SIZE(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) rc = mb86a20s_readreg(state, 0x6e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) switch ((rc >> 4) & 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return DQPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return QAM_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int mb86a20s_get_fec(struct mb86a20s_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned layer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static unsigned char reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) [0] = 0x87, /* Layer A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) [1] = 0x8b, /* Layer B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [2] = 0x8f, /* Layer C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (layer >= ARRAY_SIZE(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) rc = mb86a20s_readreg(state, 0x6e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) switch ((rc >> 4) & 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return FEC_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned layer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int interleaving[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 0, 1, 2, 4, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static unsigned char reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) [0] = 0x88, /* Layer A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) [1] = 0x8c, /* Layer B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) [2] = 0x90, /* Layer C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (layer >= ARRAY_SIZE(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) rc = mb86a20s_readreg(state, 0x6e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return interleaving[(rc >> 4) & 0x07];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned layer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int rc, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static unsigned char reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) [0] = 0x89, /* Layer A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) [1] = 0x8d, /* Layer B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) [2] = 0x91, /* Layer C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (layer >= ARRAY_SIZE(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) rc = mb86a20s_readreg(state, 0x6e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) count = (rc >> 4) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Fixed parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) c->delivery_system = SYS_ISDBT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) c->bandwidth_hz = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Initialize values that will be later autodetected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) c->isdbt_layer_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) c->transmission_mode = TRANSMISSION_MODE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) c->guard_interval = GUARD_INTERVAL_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) c->isdbt_sb_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) c->isdbt_sb_segment_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * Estimates the bit rate using the per-segment bit rate given by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * ABNT/NBR 15601 spec (table 4).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const u32 isdbt_rate[3][5][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) { /* DQPSK/QPSK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { 280850, 312060, 330420, 340430 }, /* 1/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { 374470, 416080, 440560, 453910 }, /* 2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) { 421280, 468090, 495630, 510650 }, /* 3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) { 468090, 520100, 550700, 567390 }, /* 5/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) { 491500, 546110, 578230, 595760 }, /* 7/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }, { /* QAM16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) { 561710, 624130, 660840, 680870 }, /* 1/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { 748950, 832170, 881120, 907820 }, /* 2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) { 842570, 936190, 991260, 1021300 }, /* 3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }, { /* QAM64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) { 842570, 936190, 991260, 1021300 }, /* 1/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static u32 isdbt_layer_min_bitrate(struct dtv_frontend_properties *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 layer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int mod, fec, guard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * If modulation/fec/guard is not detected, the default is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * to consider the lowest bit rate, to avoid taking too long time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * to get BER.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) switch (c->layer[layer].modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case DQPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case QPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) mod = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mod = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mod = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) switch (c->layer[layer].fec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case FEC_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) fec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) fec = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) fec = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) fec = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) fec = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) switch (c->guard_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case GUARD_INTERVAL_1_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) guard = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case GUARD_INTERVAL_1_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) guard = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) case GUARD_INTERVAL_1_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) guard = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case GUARD_INTERVAL_1_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) guard = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return isdbt_rate[mod][fec][guard] * c->layer[layer].segment_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int mb86a20s_get_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int layer, rc, rate, counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Reset frontend cache to default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mb86a20s_reset_frontend_cache(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Check for partial reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) rc = mb86a20s_writereg(state, 0x6d, 0x85);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) rc = mb86a20s_readreg(state, 0x6e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* Get per-layer data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) for (layer = 0; layer < NUM_LAYERS; layer++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) __func__, 'A' + layer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) rc = mb86a20s_get_segment_count(state, layer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) goto noperlayer_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (rc >= 0 && rc < 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) c->layer[layer].segment_count = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) c->layer[layer].segment_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) state->estimated_rate[layer] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) c->isdbt_layer_enabled |= 1 << layer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) rc = mb86a20s_get_modulation(state, layer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) goto noperlayer_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) c->layer[layer].modulation = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) rc = mb86a20s_get_fec(state, layer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) goto noperlayer_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) c->layer[layer].fec = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) rc = mb86a20s_get_interleaving(state, layer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) goto noperlayer_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) c->layer[layer].interleaving = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) rate = isdbt_layer_min_bitrate(c, layer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) counter = rate * BER_SAMPLING_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Avoids sampling too quickly or to overflow the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (counter < 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) counter = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) else if (counter > (1 << 24) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) counter = (1 << 24) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) __func__, 'A' + layer, rate / 1000, counter, counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) state->estimated_rate[layer] = counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) rc = mb86a20s_writereg(state, 0x6d, 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if ((rc & 0x60) == 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) c->isdbt_sb_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* At least, one segment should exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (!c->isdbt_sb_segment_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) c->isdbt_sb_segment_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* Get transmission mode and guard interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) rc = mb86a20s_readreg(state, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) c->transmission_mode = TRANSMISSION_MODE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if ((rc & 0x60) == 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Only modes 2 and 3 are supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) switch ((rc >> 2) & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) c->transmission_mode = TRANSMISSION_MODE_4K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) c->transmission_mode = TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) c->guard_interval = GUARD_INTERVAL_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (!(rc & 0x10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Guard interval 1/32 is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) switch (rc & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) c->guard_interval = GUARD_INTERVAL_1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) c->guard_interval = GUARD_INTERVAL_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) c->guard_interval = GUARD_INTERVAL_1_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) noperlayer_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* per-layer info is incomplete; discard all per-layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) c->isdbt_layer_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static int mb86a20s_reset_counters(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) int rc, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* Reset the counters, if the channel changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (state->last_frequency != c->frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) memset(&c->cnr, 0, sizeof(c->cnr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) memset(&c->block_error, 0, sizeof(c->block_error));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) memset(&c->block_count, 0, sizeof(c->block_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) state->last_frequency = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* Clear status for most stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* BER/PER counter reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* CNR counter reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) rc = mb86a20s_readreg(state, 0x45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) val = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) rc = mb86a20s_writereg(state, 0x45, val | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* MER counter reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) rc = mb86a20s_writereg(state, 0x50, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) val = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) rc = mb86a20s_writereg(state, 0x51, val | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) rc = mb86a20s_writereg(state, 0x51, val & 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) goto ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev_err(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) "%s: Can't reset FE statistics (error %d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ok:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) unsigned layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u32 *error, u32 *count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int rc, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (layer >= NUM_LAYERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Check if the BER measures are already available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) rc = mb86a20s_readreg(state, 0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* Check if data is available for that layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (!(rc & (1 << layer))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "%s: preBER for layer %c is not available yet.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) __func__, 'A' + layer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* Read Bit Error Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) rc = mb86a20s_readreg(state, 0x55 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) *error = rc << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) rc = mb86a20s_readreg(state, 0x56 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) *error |= rc << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) rc = mb86a20s_readreg(state, 0x57 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) *error |= rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) "%s: bit error before Viterbi for layer %c: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) __func__, 'A' + layer, *error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Read Bit Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) *count = rc << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) *count |= rc << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) *count |= rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) "%s: bit count before Viterbi for layer %c: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) __func__, 'A' + layer, *count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * As we get TMCC data from the frontend, we can better estimate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * BER bit counters, in order to do the BER measure during a longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * time. Use those data, if available, to update the bit count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * measure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (state->estimated_rate[layer]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) && state->estimated_rate[layer] != *count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) "%s: updating layer %c preBER counter to %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) __func__, 'A' + layer, state->estimated_rate[layer]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Turn off BER before Viterbi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) rc = mb86a20s_writereg(state, 0x52, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* Update counter for this layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) rc = mb86a20s_writereg(state, 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) state->estimated_rate[layer] >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) rc = mb86a20s_writereg(state, 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) state->estimated_rate[layer] >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) rc = mb86a20s_writereg(state, 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) state->estimated_rate[layer]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* Turn on BER before Viterbi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) rc = mb86a20s_writereg(state, 0x52, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* Reset all preBER counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) rc = mb86a20s_writereg(state, 0x53, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) rc = mb86a20s_writereg(state, 0x53, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /* Reset counter to collect new data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) rc = mb86a20s_readreg(state, 0x53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) val = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) unsigned layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) u32 *error, u32 *count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) u32 counter, collect_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) int rc, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (layer >= NUM_LAYERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* Check if the BER measures are already available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) rc = mb86a20s_readreg(state, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* Check if data is available for that layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (!(rc & (1 << layer))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) "%s: post BER for layer %c is not available yet.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) __func__, 'A' + layer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* Read Bit Error Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) rc = mb86a20s_readreg(state, 0x64 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) *error = rc << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) rc = mb86a20s_readreg(state, 0x65 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) *error |= rc << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) rc = mb86a20s_readreg(state, 0x66 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) *error |= rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) "%s: post bit error for layer %c: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) __func__, 'A' + layer, *error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* Read Bit Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) counter = rc << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) counter |= rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) *count = counter * 204 * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) "%s: post bit count for layer %c: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) __func__, 'A' + layer, *count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * As we get TMCC data from the frontend, we can better estimate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * BER bit counters, in order to do the BER measure during a longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * time. Use those data, if available, to update the bit count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * measure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (!state->estimated_rate[layer])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) goto reset_measurement;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) collect_rate = state->estimated_rate[layer] / 204 / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (collect_rate < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) collect_rate = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (collect_rate > 65535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) collect_rate = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (collect_rate != counter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) "%s: updating postBER counter on layer %c to %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) __func__, 'A' + layer, collect_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* Turn off BER after Viterbi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) rc = mb86a20s_writereg(state, 0x5e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* Update counter for this layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* Turn on BER after Viterbi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) rc = mb86a20s_writereg(state, 0x5e, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* Reset all preBER counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) rc = mb86a20s_writereg(state, 0x5f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) rc = mb86a20s_writereg(state, 0x5f, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) reset_measurement:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* Reset counter to collect new data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) rc = mb86a20s_readreg(state, 0x5f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) val = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) unsigned layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) u32 *error, u32 *count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) int rc, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) u32 collect_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (layer >= NUM_LAYERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* Check if the PER measures are already available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) rc = mb86a20s_writereg(state, 0x50, 0xb8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* Check if data is available for that layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (!(rc & (1 << layer))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) "%s: block counts for layer %c aren't available yet.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) __func__, 'A' + layer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* Read Packet error Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) *error = rc << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) *error |= rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) __func__, 'A' + layer, *error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* Read Bit Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) *count = rc << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) *count |= rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) "%s: block count for layer %c: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) __func__, 'A' + layer, *count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * As we get TMCC data from the frontend, we can better estimate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * BER bit counters, in order to do the BER measure during a longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * time. Use those data, if available, to update the bit count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * measure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (!state->estimated_rate[layer])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) goto reset_measurement;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) collect_rate = state->estimated_rate[layer] / 204 / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (collect_rate < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) collect_rate = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (collect_rate > 65535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) collect_rate = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (collect_rate != *count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) "%s: updating PER counter on layer %c to %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) __func__, 'A' + layer, collect_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Stop PER measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) rc = mb86a20s_writereg(state, 0x50, 0xb0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) rc = mb86a20s_writereg(state, 0x51, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* Update this layer's counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /* start PER measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) rc = mb86a20s_writereg(state, 0x50, 0xb0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) rc = mb86a20s_writereg(state, 0x51, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* Reset all counters to collect new data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) rc = mb86a20s_writereg(state, 0x50, 0xb1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) rc = mb86a20s_writereg(state, 0x51, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) rc = mb86a20s_writereg(state, 0x51, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) reset_measurement:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* Reset counter to collect new data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) rc = mb86a20s_writereg(state, 0x50, 0xb1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) val = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct linear_segments {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) unsigned x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * All tables below return a dB/1000 measurement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static const struct linear_segments cnr_to_db_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) { 19648, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) { 18187, 1000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) { 16534, 2000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) { 14823, 3000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) { 13161, 4000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) { 11622, 5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) { 10279, 6000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) { 9089, 7000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) { 8042, 8000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) { 7137, 9000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) { 6342, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) { 5641, 11000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) { 5030, 12000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) { 4474, 13000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) { 3988, 14000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) { 3556, 15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) { 3180, 16000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) { 2841, 17000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) { 2541, 18000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) { 2276, 19000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) { 2038, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) { 1800, 21000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) { 1625, 22000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) { 1462, 23000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) { 1324, 24000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) { 1175, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) { 1063, 26000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) { 980, 27000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) { 907, 28000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) { 840, 29000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) { 788, 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static const struct linear_segments cnr_64qam_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) { 3922688, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) { 3920384, 1000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) { 3902720, 2000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) { 3894784, 3000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) { 3882496, 4000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) { 3872768, 5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) { 3858944, 6000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) { 3851520, 7000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) { 3838976, 8000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) { 3829248, 9000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) { 3818240, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) { 3806976, 11000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) { 3791872, 12000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) { 3767040, 13000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) { 3720960, 14000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) { 3637504, 15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) { 3498496, 16000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) { 3296000, 17000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) { 3031040, 18000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) { 2715392, 19000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) { 2362624, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) { 1963264, 21000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) { 1649664, 22000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) { 1366784, 23000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) { 1120768, 24000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) { 890880, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) { 723456, 26000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) { 612096, 27000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) { 518912, 28000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) { 448256, 29000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) { 388864, 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static const struct linear_segments cnr_16qam_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) { 5314816, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) { 5219072, 1000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) { 5118720, 2000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) { 4998912, 3000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) { 4875520, 4000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) { 4736000, 5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) { 4604160, 6000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) { 4458752, 7000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) { 4300288, 8000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) { 4092928, 9000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) { 3836160, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) { 3521024, 11000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) { 3155968, 12000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) { 2756864, 13000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) { 2347008, 14000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) { 1955072, 15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) { 1593600, 16000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) { 1297920, 17000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) { 1043968, 18000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) { 839680, 19000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) { 672256, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) { 523008, 21000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) { 424704, 22000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) { 345088, 23000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) { 280064, 24000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) { 221440, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) { 179712, 26000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) { 151040, 27000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) { 128512, 28000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) { 110080, 29000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) { 95744, 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) static const struct linear_segments cnr_qpsk_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) { 2834176, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) { 2683648, 1000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) { 2536960, 2000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) { 2391808, 3000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) { 2133248, 4000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) { 1906176, 5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) { 1666560, 6000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) { 1422080, 7000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) { 1189632, 8000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) { 976384, 9000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) { 790272, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) { 633344, 11000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) { 505600, 12000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) { 402944, 13000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) { 320768, 14000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) { 255488, 15000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) { 204032, 16000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) { 163072, 17000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) { 130304, 18000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) { 105216, 19000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) { 83456, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) { 65024, 21000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) { 52480, 22000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) { 42752, 23000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) { 34560, 24000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) { 27136, 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) { 22016, 26000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) { 18432, 27000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) { 15616, 28000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) { 13312, 29000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) { 11520, 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static u32 interpolate_value(u32 value, const struct linear_segments *segments,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) unsigned len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) u64 tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) u32 dx, dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (value >= segments[0].x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return segments[0].y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (value < segments[len-1].x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) return segments[len-1].y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) for (i = 1; i < len - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /* If value is identical, no need to interpolate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (value == segments[i].x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return segments[i].y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (value > segments[i].x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* Linear interpolation between the two (x,y) points */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) dy = segments[i].y - segments[i - 1].y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) dx = segments[i - 1].x - segments[i].x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) tmp64 = value - segments[i].x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) tmp64 *= dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) do_div(tmp64, dx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ret = segments[i].y - tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) u32 cnr_linear, cnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) int rc, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* Check if CNR is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) rc = mb86a20s_readreg(state, 0x45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (!(rc & 0x40)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) val = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) rc = mb86a20s_readreg(state, 0x46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) cnr_linear = rc << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) rc = mb86a20s_readreg(state, 0x46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) cnr_linear |= rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) cnr = interpolate_value(cnr_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) c->cnr.stat[0].svalue = cnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) __func__, cnr / 1000, cnr % 1000, cnr_linear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* CNR counter reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) rc = mb86a20s_writereg(state, 0x45, val | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) u32 mer, cnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) int rc, val, layer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) const struct linear_segments *segs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) unsigned segs_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* Check if the measures are already available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) rc = mb86a20s_writereg(state, 0x50, 0x5b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* Check if data is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (!(rc & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) "%s: MER measures aren't available yet.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /* Read all layers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) for (layer = 0; layer < NUM_LAYERS; layer++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (!(c->isdbt_layer_enabled & (1 << layer))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) mer = rc << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) mer |= rc << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) mer |= rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) switch (c->layer[layer].modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) case DQPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) case QPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) segs = cnr_qpsk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) segs_len = ARRAY_SIZE(cnr_qpsk_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) segs = cnr_16qam_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) segs_len = ARRAY_SIZE(cnr_16qam_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) segs = cnr_64qam_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) segs_len = ARRAY_SIZE(cnr_64qam_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) cnr = interpolate_value(mer, segs, segs_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) c->cnr.stat[1 + layer].svalue = cnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) dev_dbg(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* Start a new MER measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* MER counter reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) rc = mb86a20s_writereg(state, 0x50, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) rc = mb86a20s_readreg(state, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) val = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) rc = mb86a20s_writereg(state, 0x51, val | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) rc = mb86a20s_writereg(state, 0x51, val & 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) int layer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* Fill the length of each status counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* Only global stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) c->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /* Per-layer stats - 3 layers + global */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) c->cnr.len = NUM_LAYERS + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) c->pre_bit_error.len = NUM_LAYERS + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) c->pre_bit_count.len = NUM_LAYERS + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) c->post_bit_error.len = NUM_LAYERS + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) c->post_bit_count.len = NUM_LAYERS + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) c->block_error.len = NUM_LAYERS + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) c->block_count.len = NUM_LAYERS + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /* Signal is always available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) c->strength.stat[0].scale = FE_SCALE_RELATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) c->strength.stat[0].uvalue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* Put all of them at FE_SCALE_NOT_AVAILABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) int rc = 0, layer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) u32 bit_error = 0, bit_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) u32 t_post_bit_error = 0, t_post_bit_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) u32 block_error = 0, block_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) u32 t_block_error = 0, t_block_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) int per_layers = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) mb86a20s_get_main_CNR(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* Get per-layer stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) mb86a20s_get_blk_error_layer_CNR(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * At state 7, only CNR is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * For BER measures, state=9 is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * FIXME: we may get MER measures with state=8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (status_nr < 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) for (layer = 0; layer < NUM_LAYERS; layer++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (c->isdbt_layer_enabled & (1 << layer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* Layer is active and has rc segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) active_layers++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) /* Handle BER before vterbi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) rc = mb86a20s_get_pre_ber(fe, layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) &bit_error, &bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (rc >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) } else if (rc != -EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) * If an I/O error happened,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) * measures are now unavailable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) dev_err(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) "%s: Can't get BER for layer %c (error %d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) __func__, 'A' + layer, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) pre_ber_layers++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* Handle BER post vterbi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) rc = mb86a20s_get_post_ber(fe, layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) &bit_error, &bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if (rc >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) c->post_bit_error.stat[1 + layer].uvalue += bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) c->post_bit_count.stat[1 + layer].uvalue += bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) } else if (rc != -EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * If an I/O error happened,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * measures are now unavailable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) dev_err(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) "%s: Can't get BER for layer %c (error %d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) __func__, 'A' + layer, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) post_ber_layers++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) /* Handle Block errors for PER/UCB reports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) rc = mb86a20s_get_blk_error(fe, layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) &block_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) &block_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) if (rc >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) c->block_error.stat[1 + layer].uvalue += block_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) c->block_count.stat[1 + layer].uvalue += block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) } else if (rc != -EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) * If an I/O error happened,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) * measures are now unavailable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) dev_err(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) "%s: Can't get PER for layer %c (error %d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) __func__, 'A' + layer, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) per_layers++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /* Update total preBER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /* Update total postBER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /* Update total PER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) t_block_error += c->block_error.stat[1 + layer].uvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) t_block_count += c->block_count.stat[1 + layer].uvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) * Start showing global count if at least one error count is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) * available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (pre_ber_layers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) * At least one per-layer BER measure was read. We can now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) * calculate the total BER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) * Total Bit Error/Count is calculated as the sum of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) * bit errors on all active layers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) * Start showing global count if at least one error count is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) * available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (post_ber_layers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) * At least one per-layer BER measure was read. We can now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) * calculate the total BER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) * Total Bit Error/Count is calculated as the sum of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) * bit errors on all active layers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) c->post_bit_error.stat[0].uvalue = t_post_bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) c->post_bit_count.stat[0].uvalue = t_post_bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) if (per_layers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) * At least one per-layer UCB measure was read. We can now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) * calculate the total UCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) * Total block Error/Count is calculated as the sum of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) * block errors on all active layers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) c->block_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) c->block_error.stat[0].uvalue = t_block_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) c->block_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) c->block_count.stat[0].uvalue = t_block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) c->block_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) * The functions below are called via DVB callbacks, so they need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) * properly use the I2C gate control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static int mb86a20s_initfe(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) u64 pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) u32 fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) u8 regD5 = 1, reg71, reg09 = 0x3a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) /* Initialize the frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) rc = mb86a20s_writeregdata(state, mb86a20s_init1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (!state->inversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) reg09 |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) rc = mb86a20s_writereg(state, 0x09, reg09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (!state->bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) reg71 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) reg71 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) rc = mb86a20s_writereg(state, 0x39, reg71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) rc = mb86a20s_writereg(state, 0x71, state->bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (state->subchannel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) rc = mb86a20s_writereg(state, 0x44, state->subchannel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) fclk = state->config->fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (!fclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) fclk = 32571428;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) /* Adjust IF frequency to match tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (fe->ops.tuner_ops.get_if_frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (!state->if_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) state->if_freq = 3300000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) pll = (((u64)1) << 34) * state->if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) do_div(pll, 63 * fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) pll = (1 << 25) - pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) rc = mb86a20s_writereg(state, 0x28, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) __func__, fclk, state->if_freq, (long long)pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) pll = state->if_freq * 1677721600L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) do_div(pll, 1628571429L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) rc = mb86a20s_writereg(state, 0x28, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) __func__, state->if_freq, (long long)pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (!state->config->is_serial)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) regD5 &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) rc = mb86a20s_writereg(state, 0x50, 0xd5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) rc = mb86a20s_writereg(state, 0x51, regD5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) rc = mb86a20s_writeregdata(state, mb86a20s_init2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) state->need_init = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) dev_info(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) "mb86a20s: Init failed. Will try again later\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) state->need_init = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) static int mb86a20s_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) int rc, if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (!c->isdbt_layer_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) c->isdbt_layer_enabled = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (c->isdbt_layer_enabled == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) state->bw = MB86A20S_1SEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) else if (c->isdbt_partial_reception)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) state->bw = MB86A20S_13SEG_PARTIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) state->bw = MB86A20S_13SEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (c->inversion == INVERSION_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) state->inversion = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) state->inversion = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (!c->isdbt_sb_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) state->subchannel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) c->isdbt_sb_subchannel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) * Gate should already be opened, but it doesn't hurt to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) * double-check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (fe->ops.tuner_ops.get_if_frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) * Make it more reliable: if, for some reason, the initial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) * device initialization doesn't happen, initialize it when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * a SBTVD parameters are adjusted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) * Unfortunately, due to a hard to track bug at tda829x/tda18271,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) * the agc callback logic is not called during DVB attach time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) * causing mb86a20s to not be initialized with Kworld SBTVD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) * So, this hack is needed, in order to make Kworld SBTVD to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) * It is also needed to change the IF after the initial init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) * HACK: Always init the frontend when set_frontend is called:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) * it was noticed that, on some devices, it fails to lock on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) * different channel. So, it is better to reset everything, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) * wasting some time, than to loose channel lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) mb86a20s_initfe(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) mb86a20s_reset_counters(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) mb86a20s_stats_not_ready(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) int rc, status_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) /* Get lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) status_nr = mb86a20s_read_status(fe, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if (status_nr < 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) mb86a20s_stats_not_ready(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) mb86a20s_reset_frontend_cache(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) if (status_nr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) dev_err(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) "%s: Can't read frontend lock status\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) rc = status_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) /* Get signal strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) rc = mb86a20s_read_signal_strength(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) dev_err(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) "%s: Can't reset VBER registers.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) mb86a20s_stats_not_ready(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) mb86a20s_reset_frontend_cache(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) rc = 0; /* Status is OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (status_nr >= 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) /* Get TMCC info*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) rc = mb86a20s_get_frontend(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) dev_err(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) "%s: Can't get FE TMCC data.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) rc = 0; /* Status is OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) /* Get statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) rc = mb86a20s_get_stats(fe, status_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (rc < 0 && rc != -EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) dev_err(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) "%s: Can't get FE statistics.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) rc = 0; /* Don't return EBUSY to userspace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) goto ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) mb86a20s_stats_not_ready(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ok:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) *strength = c->strength.stat[0].uvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) static int mb86a20s_tune(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) bool re_tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) unsigned int mode_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) unsigned int *delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) if (re_tune)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) rc = mb86a20s_set_frontend(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) mb86a20s_read_status_and_stats(fe, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static void mb86a20s_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) struct mb86a20s_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) static enum dvbfe_algo mb86a20s_get_frontend_algo(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) return DVBFE_ALGO_HW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) static const struct dvb_frontend_ops mb86a20s_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) struct mb86a20s_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) dev_dbg(&i2c->dev, "%s called.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) memcpy(&state->frontend.ops, &mb86a20s_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) /* Check if it is a mb86a20s frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) rev = mb86a20s_readreg(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (rev != 0x13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) dev_dbg(&i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) "Frontend revision %d is unknown - aborting.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) dev_info(&i2c->dev, "Detected a Fujitsu mb86a20s frontend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) EXPORT_SYMBOL(mb86a20s_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) static const struct dvb_frontend_ops mb86a20s_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .delsys = { SYS_ISDBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) /* Use dib8000 values per default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .name = "Fujitsu mb86A20s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .caps = FE_CAN_RECOVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) /* Actually, those values depend on the used tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .frequency_min_hz = 45 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .frequency_max_hz = 864 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .frequency_stepsize_hz = 62500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .release = mb86a20s_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .init = mb86a20s_initfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .set_frontend = mb86a20s_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .read_status = mb86a20s_read_status_and_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .tune = mb86a20s_tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .get_frontend_algo = mb86a20s_get_frontend_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) MODULE_AUTHOR("Mauro Carvalho Chehab");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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