^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) Manu Abraham (abraham.manu@gmail.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __MB86A16_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __MB86A16_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MB86A16_TSOUT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MB86A16_TSOUT_HIZSEL (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MB86A16_TSOUT_HIZCNTI (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MB86A16_TSOUT_MODE (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MB86A16_TSOUT_ORDER (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MB86A16_TSOUT_ERROR (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define Mb86A16_TSOUT_EDGE (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MB86A16_FEC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MB86A16_FEC_FSYNC (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MB86A16_FEC_PCKB8 (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MB86A16_FEC_DVDS (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MB86A16_FEC_EREN (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define Mb86A16_FEC_RSEN (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MB86A16_FEC_DIEN (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MB86A16_AGC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MB86A16_AGC_AGMD (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MB86A16_AGC_AGCW (0x0f << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MB86A16_AGC_AGCP (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MB86A16_AGC_AGCR (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MB86A16_SRATE1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MB86A16_SRATE1_DECI (0x07 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MB86A16_SRATE1_CSEL (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MB86A16_SRATE1_RSEL (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MB86A16_SRATE2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MB86A16_SRATE2_STOFSL (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MB86A16_SRATE3 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MB86A16_SRATE2_STOFSH (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MB86A16_VITERBI 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MB86A16_FRAMESYNC 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MB86A16_CRLFILTCOEF1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MB86A16_CRLFILTCOEF2 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MB86A16_STRFILTCOEF1 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MB86A16_STRFILTCOEF2 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MB86A16_RESET 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MB86A16_STATUS 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MB86A16_AFCML 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MB86A16_AFCMH 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MB86A16_BERMON 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MB86A16_BERTAB 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MB86A16_BERLSB 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MB86A16_BERMID 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MB86A16_BERMSB 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MB86A16_AGCM 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MB86A16_DCC1 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MB86A16_DCC1_DISTA (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MB86A16_DCC1_PRTY (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MB86A16_DCC1_CTOE (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MB86A16_DCC1_TBEN (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MB86A16_DCC1_TBO (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MB86A16_DCC1_NUM (0x07 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MB86A16_DCC2 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MB86A16_DCC2_DCBST (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MB86A16_DCC3 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MB86A16_DCC3_CODE0 (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MB86A16_DCC4 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MB86A16_DCC4_CODE1 (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MB86A16_DCC5 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MB86A16_DCC5_CODE2 (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MB86A16_DCC6 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MB86A16_DCC6_CODE3 (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MB86A16_DCC7 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MB86A16_DCC7_CODE4 (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MB86A16_DCC8 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MB86A16_DCC8_CODE5 (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MB86A16_DCCOUT 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MB86A16_DCCOUT_DISEN (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MB86A16_TONEOUT1 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MB86A16_TONE_TDIVL (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MB86A16_TONEOUT2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MB86A16_TONE_TMD (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MB86A16_TONE_TDIVH (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MB86A16_FREQ1 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MB86A16_FREQ2 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MB86A16_FREQ3 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MB86A16_FREQ4 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MB86A16_FREQSET 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MB86A16_CNM 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MB86A16_PORT0 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MB86A16_PORT1 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MB86A16_DRCFILT 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MB86A16_AFC 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MB86A16_AFCEXL 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MB86A16_AFCEXH 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MB86A16_DAGC 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MB86A16_SEQMODE 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MB86A16_S0S1T 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MB86A16_S2S3T 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MB86A16_S4S5T 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MB86A16_CNTMR 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MB86A16_SIG1 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MB86A16_SIG2 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MB86A16_VIMAG 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MB86A16_VISET1 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MB86A16_VISET2 0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MB86A16_VISET3 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MB86A16_FAGCS1 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MB86A16_FAGCS2 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MB86A16_FAGCS3 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MB86A16_FAGCS4 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MB86A16_FAGCS5 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MB86A16_FAGCS6 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MB86A16_CRM 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MB86A16_STRM 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MB86A16_DAGCML 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MB86A16_DAGCMH 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MB86A16_QPSKTST 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MB86A16_DISTMON 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MB86A16_VERSION 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #endif /* __MB86A16_PRIV_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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