^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) Manu Abraham (abraham.manu@gmail.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "mb86a16.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "mb86a16_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static unsigned int verbose = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) module_param(verbose, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct mb86a16_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct i2c_adapter *i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) const struct mb86a16_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* tuning parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Internal stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int master_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int deci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int csel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int rsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MB86A16_ERROR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MB86A16_NOTICE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MB86A16_INFO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MB86A16_DEBUG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define dprintk(x, y, z, format, arg...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (z) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if ((x > MB86A16_ERROR) && (x > y)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) else if ((x > MB86A16_NOTICE) && (x > y)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) else if ((x > MB86A16_INFO) && (x > y)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) else if ((x > MB86A16_DEBUG) && (x > y)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) } else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (x > y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) printk(format, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 buf[] = { reg, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .addr = state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .len = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) dprintk(verbose, MB86A16_DEBUG, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) state->config->demod_address, buf[0], buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ret = i2c_transfer(state->i2c_adap, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return (ret != 1) ? -EREMOTEIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 b0[] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 b1[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .addr = state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .buf = b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .len = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .addr = state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .buf = b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .len = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = i2c_transfer(state->i2c_adap, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=%i)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *val = b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int CNTM_set(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned char timint1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned char timint2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned char cnext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val = (timint1 << 4) | (timint2 << 2) | cnext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (mb86a16_write(state, MB86A16_CNTMR, val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int smrt_set(struct mb86a16_state *state, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int tmp ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int m ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned char STOFS0, STOFS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) m = 1 << state->deci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) STOFS0 = tmp & 0x0ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) STOFS1 = (tmp & 0xf00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) (state->csel << 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) state->rsel) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int srst(struct mb86a16_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int afcex_data_set(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned char AFCEX_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned char AFCEX_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int afcofs_data_set(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned char AFCEX_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned char AFCEX_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (mb86a16_write(state, 0x58, AFCEX_L) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (mb86a16_write(state, 0x59, AFCEX_H) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int stlp_set(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned char STRAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned char STRBS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int initial_set(struct mb86a16_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (stlp_set(state, 5, 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (afcex_data_set(state, 0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (afcofs_data_set(state, 0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (mb86a16_write(state, 0x2f, 0x21) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (mb86a16_write(state, 0x54, 0xff) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int S01T_set(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned char s1t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned s0t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int EN_set(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int cren,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int afcen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) val = 0x7a | (cren << 7) | (afcen << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (mb86a16_write(state, 0x49, val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int AFCEXEN_set(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int afcexen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int smrt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned char AFCA ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (smrt > 18875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) AFCA = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) else if (smrt > 9375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) AFCA = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) else if (smrt > 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) AFCA = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) AFCA = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int DAGC_data_set(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned char DAGCA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned char DAGCW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void smrt_info_get(struct mb86a16_state *state, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (rate >= 37501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) state->deci = 0; state->csel = 0; state->rsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) } else if (rate >= 30001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) state->deci = 0; state->csel = 0; state->rsel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } else if (rate >= 26251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) state->deci = 0; state->csel = 1; state->rsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) } else if (rate >= 22501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) state->deci = 0; state->csel = 1; state->rsel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } else if (rate >= 18751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) state->deci = 1; state->csel = 0; state->rsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) } else if (rate >= 15001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) state->deci = 1; state->csel = 0; state->rsel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } else if (rate >= 13126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) state->deci = 1; state->csel = 1; state->rsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } else if (rate >= 11251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) state->deci = 1; state->csel = 1; state->rsel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) } else if (rate >= 9376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) state->deci = 2; state->csel = 0; state->rsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) } else if (rate >= 7501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) state->deci = 2; state->csel = 0; state->rsel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) } else if (rate >= 6563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) state->deci = 2; state->csel = 1; state->rsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } else if (rate >= 5626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) state->deci = 2; state->csel = 1; state->rsel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) } else if (rate >= 4688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) state->deci = 3; state->csel = 0; state->rsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) } else if (rate >= 3751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) state->deci = 3; state->csel = 0; state->rsel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) } else if (rate >= 3282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) state->deci = 3; state->csel = 1; state->rsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } else if (rate >= 2814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) state->deci = 3; state->csel = 1; state->rsel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) } else if (rate >= 2344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) state->deci = 4; state->csel = 0; state->rsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) } else if (rate >= 1876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) state->deci = 4; state->csel = 0; state->rsel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) } else if (rate >= 1641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) state->deci = 4; state->csel = 1; state->rsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) } else if (rate >= 1407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) state->deci = 4; state->csel = 1; state->rsel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else if (rate >= 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) state->deci = 5; state->csel = 0; state->rsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } else if (rate >= 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) state->deci = 5; state->csel = 0; state->rsel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) } else if (rate >= 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) state->deci = 5; state->csel = 1; state->rsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) state->deci = 5; state->csel = 1; state->rsel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (state->csel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) state->master_clk = 92000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) state->master_clk = 61333;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int signal_det(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int smrt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned char *SIG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int smrtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned char S[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (*SIG > 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (CNTM_set(state, 2, 1, 2) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (CNTM_set(state, 3, 1, 2) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) smrtd = smrt * 98 / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) else if (i == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) smrtd = smrt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) smrtd = smrt * 102 / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) smrt_info_get(state, smrtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) smrt_set(state, smrtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) srst(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) msleep_interruptible(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (mb86a16_read(state, 0x37, &(S[i])) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if ((S[1] > S[0] * 112 / 100) && (S[1] > S[2] * 112 / 100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *SIG = S[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (CNTM_set(state, 0, 1, 2) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int rf_val_set(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int smrt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned char R)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned char C, F, B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned char rf_val[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int ack = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (smrt > 37750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) C = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) else if (smrt > 18875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) C = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) else if (smrt > 5500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) C = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) C = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (smrt > 30500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) F = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) else if (smrt > 9375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) F = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) else if (smrt > 4625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) F = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) F = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (f < 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) B = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) else if (f < 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) B = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) else if (f < 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) B = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) else if (f < 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) B = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) else if (f < 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) B = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else if (f < 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) B = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) else if (f < 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) B = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) else if (f < 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) B = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) else if (f < 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) B = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) B = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) M = f * (1 << R) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) rf_val[0] = 0x01 | (C << 3) | (F << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) rf_val[2] = (M & 0x00ff0) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) rf_val[3] = ((M & 0x0000f) << 4) | B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Frequency Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (mb86a16_write(state, 0x21, rf_val[0]) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ack = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (mb86a16_write(state, 0x22, rf_val[1]) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ack = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (mb86a16_write(state, 0x23, rf_val[2]) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ack = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (mb86a16_write(state, 0x24, rf_val[3]) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ack = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (mb86a16_write(state, 0x25, 0x01) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ack = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (ack == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int afcerr_chk(struct mb86a16_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned char AFCM_L, AFCM_H ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int AFCM ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int afcm, afcerr ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (mb86a16_read(state, 0x0e, &AFCM_L) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (mb86a16_read(state, 0x0f, &AFCM_H) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) AFCM = (AFCM_H << 8) + AFCM_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (AFCM > 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) afcm = AFCM - 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) afcm = AFCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) afcerr = afcm * state->master_clk / 8192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return afcerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int dagcm_val_get(struct mb86a16_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int DAGCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned char DAGCM_H, DAGCM_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (mb86a16_read(state, 0x45, &DAGCM_L) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (mb86a16_read(state, 0x46, &DAGCM_H) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) DAGCM = (DAGCM_H << 8) + DAGCM_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return DAGCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static int mb86a16_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u8 stat, stat2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct mb86a16_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if ((stat > 25) && (stat2 > 25))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if ((stat > 45) && (stat2 > 45))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) *status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (stat & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (stat & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) *status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if ((stat & 0x0f) && (*status & FE_HAS_VITERBI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int sync_chk(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned char *VIRM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (mb86a16_read(state, 0x0d, &val) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) sync = val & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) *VIRM = (val & 0x1c) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) *VIRM = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int freqerr_chk(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int fTP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int smrt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned char CRM, AFCML, AFCMH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) unsigned char temp1, temp2, temp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int crm, afcm, AFCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int crrerr, afcerr; /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int frqerr; /* MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int afcen, afcexen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int R, M, fOSC, fOSC_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (mb86a16_read(state, 0x43, &CRM) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (CRM > 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) crm = CRM - 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) crm = CRM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) crrerr = smrt * crm / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (mb86a16_read(state, 0x49, &temp1) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) afcen = (temp1 & 0x04) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (afcen == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (mb86a16_read(state, 0x2a, &temp1) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) afcexen = (temp1 & 0x20) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (afcen == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (mb86a16_read(state, 0x0e, &AFCML) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (mb86a16_read(state, 0x0f, &AFCMH) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) } else if (afcexen == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (mb86a16_read(state, 0x2b, &AFCML) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (mb86a16_read(state, 0x2c, &AFCMH) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if ((afcen == 1) || (afcexen == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) smrt_info_get(state, smrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) AFCM = ((AFCMH & 0x01) << 8) + AFCML;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (AFCM > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) afcm = AFCM - 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) afcm = AFCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) afcerr = afcm * state->master_clk / 8192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) afcerr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (mb86a16_read(state, 0x22, &temp1) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (mb86a16_read(state, 0x23, &temp2) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (mb86a16_read(state, 0x24, &temp3) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) R = (temp1 & 0xe0) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (R == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) fOSC = 2 * M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) fOSC = M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) fOSC_OFS = fOSC - fTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (unit == 0) { /* MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (crrerr + afcerr + fOSC_OFS * 1000 >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) } else { /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) frqerr = crrerr + afcerr + fOSC_OFS * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return frqerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) unsigned char R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (smrt > 9375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) R = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) R = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static void swp_info_get(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int fOSC_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int smrt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int v, int R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int swp_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) int *fOSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) int *afcex_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) unsigned char *AFCEX_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) unsigned char *AFCEX_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int AFCEX ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int crnt_swp_freq ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (R == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) *fOSC = (crnt_swp_freq + 1000) / 2000 * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) *fOSC = (crnt_swp_freq + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (*fOSC >= crnt_swp_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) *afcex_freq = *fOSC * 1000 - crnt_swp_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) *afcex_freq = crnt_swp_freq - *fOSC * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) AFCEX = *afcex_freq * 8192 / state->master_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) *AFCEX_L = AFCEX & 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) *AFCEX_H = (AFCEX & 0x0f00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int swp_freq ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if ((i % 2 == 1) && (v <= vmax)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* positive v (case 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if ((v - 1 == vmin) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) (*(V + 30 + v) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) (*(V + 30 + v - 1) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) (*(V + 30 + v - 1) > *(V + 30 + v)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) (*(V + 30 + v - 1) > SIGMIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) *SIG1 = *(V + 30 + v - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) } else if ((v == vmax) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) (*(V + 30 + v) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) (*(V + 30 + v - 1) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) (*(V + 30 + v) > *(V + 30 + v - 1)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) (*(V + 30 + v) > SIGMIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* (case 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) swp_freq = fOSC * 1000 + afcex_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) *SIG1 = *(V + 30 + v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) } else if ((*(V + 30 + v) > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) (*(V + 30 + v - 1) > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) (*(V + 30 + v - 2) > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) (*(V + 30 + v - 3) > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) (*(V + 30 + v - 1) > *(V + 30 + v)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) (*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ((*(V + 30 + v - 1) > SIGMIN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) (*(V + 30 + v - 2) > SIGMIN))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* (case 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) *SIG1 = *(V + 30 + v - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) *SIG1 = *(V + 30 + v - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) } else if ((v == vmax) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) (*(V + 30 + v) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) (*(V + 30 + v - 1) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) (*(V + 30 + v - 2) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) (*(V + 30 + v) > *(V + 30 + v - 2)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) (*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ((*(V + 30 + v) > SIGMIN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) (*(V + 30 + v - 1) > SIGMIN))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* (case 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) swp_freq = fOSC * 1000 + afcex_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) *SIG1 = *(V + 30 + v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) *SIG1 = *(V + 30 + v - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) swp_freq = -1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) } else if ((i % 2 == 0) && (v >= vmin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* Negative v (case 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if ((*(V + 30 + v) > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) (*(V + 30 + v + 1) > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) (*(V + 30 + v + 2) > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) (*(V + 30 + v + 1) > *(V + 30 + v)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) (*(V + 30 + v + 1) > SIGMIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) *SIG1 = *(V + 30 + v + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) } else if ((v + 1 == vmax) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) (*(V + 30 + v) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) (*(V + 30 + v + 1) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) (*(V + 30 + v + 1) > *(V + 30 + v)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) (*(V + 30 + v + 1) > SIGMIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* (case 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) *SIG1 = *(V + 30 + v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) } else if ((v == vmin) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) (*(V + 30 + v) > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) (*(V + 30 + v + 1) > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) (*(V + 30 + v + 2) > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) (*(V + 30 + v) > *(V + 30 + v + 1)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) (*(V + 30 + v) > *(V + 30 + v + 2)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) (*(V + 30 + v) > SIGMIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* (case 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) swp_freq = fOSC * 1000 + afcex_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) *SIG1 = *(V + 30 + v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) } else if ((*(V + 30 + v) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) (*(V + 30 + v + 1) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) (*(V + 30 + v + 2) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) (*(V + 30 + v + 3) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) (*(V + 30 + v + 1) > *(V + 30 + v)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) (*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ((*(V + 30 + v + 1) > SIGMIN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) (*(V + 30 + v + 2) > SIGMIN))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* (case 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) *SIG1 = *(V + 30 + v + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) *SIG1 = *(V + 30 + v + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) } else if ((*(V + 30 + v) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) (*(V + 30 + v + 1) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) (*(V + 30 + v + 2) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) (*(V + 30 + v + 3) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) (*(V + 30 + v) > *(V + 30 + v + 2)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) (*(V + 30 + v) > *(V + 30 + v + 3)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) (*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ((*(V + 30 + v) > SIGMIN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) (*(V + 30 + v + 1) > SIGMIN))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* (case 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) swp_freq = fOSC * 1000 + afcex_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) *SIG1 = *(V + 30 + v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) *SIG1 = *(V + 30 + v + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) } else if ((v + 2 == vmin) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) (*(V + 30 + v) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) (*(V + 30 + v + 1) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) (*(V + 30 + v + 2) >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) (*(V + 30 + v + 1) > *(V + 30 + v)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) (*(V + 30 + v + 2) > *(V + 30 + v)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ((*(V + 30 + v + 1) > SIGMIN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) (*(V + 30 + v + 2) > SIGMIN))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* (case 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) *SIG1 = *(V + 30 + v + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) *SIG1 = *(V + 30 + v + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) swp_freq = fOSC * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) *SIG1 = *(V + 30 + v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) swp_freq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) swp_freq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return swp_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static void swp_info_get2(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int smrt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) int R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) int swp_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) int *afcex_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) int *fOSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) unsigned char *AFCEX_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) unsigned char *AFCEX_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int AFCEX ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (R == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) *fOSC = (swp_freq + 1000) / 2000 * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) *fOSC = (swp_freq + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (*fOSC >= swp_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) *afcex_freq = *fOSC * 1000 - swp_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) *afcex_freq = swp_freq - *fOSC * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) AFCEX = *afcex_freq * 8192 / state->master_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) *AFCEX_L = AFCEX & 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) *AFCEX_H = (AFCEX & 0x0f00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static void afcex_info_get(struct mb86a16_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) int afcex_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) unsigned char *AFCEX_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) unsigned char *AFCEX_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) int AFCEX ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) AFCEX = afcex_freq * 8192 / state->master_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) *AFCEX_L = AFCEX & 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) *AFCEX_H = (AFCEX & 0x0f00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static int SEQ_set(struct mb86a16_state *state, unsigned char loop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* SLOCK0 = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* Viterbi Rate, IQ Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static int FEC_srst(struct mb86a16_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static int S2T_set(struct mb86a16_state *state, unsigned char S2T)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static int mb86a16_set_fe(struct mb86a16_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) u8 agcval, cnmval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int fOSC = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) int fOSC_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) int wait_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) int fcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) int swp_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) int V[60];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) u8 SIG1MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) unsigned char CREN, AFCEN, AFCEXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) unsigned char SIG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) unsigned char TIMINT1, TIMINT2, TIMEXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) unsigned char S0T, S1T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) unsigned char S2T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* unsigned char S2T, S3T; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) unsigned char S4T, S5T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) unsigned char AFCEX_L, AFCEX_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) unsigned char R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) unsigned char VIRM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) unsigned char ETH, VIA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) unsigned char junk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) int loop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int ftemp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) int v, vmax, vmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) int vmax_his, vmin_his;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) int swp_freq, prev_swp_freq[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) int prev_freq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) int signal_dupl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) int afcex_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) int signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) int afcerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) int temp_freq, delta_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) int dagcm[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) int smrt_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* int freq_err; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) int sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) fcp = 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) swp_ofs = state->srate / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) for (i = 0; i < 60; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) V[i] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) for (i = 0; i < 20; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) prev_swp_freq[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) SIG1MIN = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) for (n = 0; ((n < 3) && (ret == -1)); n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) SEQ_set(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) iq_vt_set(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) CREN = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) AFCEN = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) AFCEXEN = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) TIMINT1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) TIMINT2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) TIMEXT = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) S1T = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) S0T = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (initial_set(state) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dprintk(verbose, MB86A16_ERROR, 1, "initial set failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (DAGC_data_set(state, 3, 2) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (EN_set(state, CREN, AFCEN) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return -1; /* (0, 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return -1; /* (1, smrt) = (1, symbolrate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return -1; /* (0, 1, 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (S01T_set(state, S1T, S0T) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return -1; /* (0, 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) smrt_info_get(state, state->srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (smrt_set(state, state->srate) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) R = vco_dev_get(state, state->srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (R == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) fOSC_start = state->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) else if (R == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (state->frequency % 2 == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) fOSC_start = state->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) fOSC_start = state->frequency + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (fOSC_start > 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) fOSC_start = state->frequency - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) loop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ftemp = fOSC_start * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) vmax = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) while (loop == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ftemp = ftemp + swp_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) vmax++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* Upper bound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (ftemp > 2150000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) vmax--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if ((ftemp == 2150000) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) (ftemp - state->frequency * 1000 >= fcp + state->srate / 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) loop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ftemp = fOSC_start * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) vmin = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) while (loop == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ftemp = ftemp - swp_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) vmin--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /* Lower bound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (ftemp < 950000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) vmin++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if ((ftemp == 950000) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) (state->frequency * 1000 - ftemp >= fcp + state->srate / 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) wait_t = (8000 + state->srate / 2) / state->srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (wait_t == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) wait_t = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) prev_freq_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) loop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) signal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) vmax_his = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) vmin_his = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) while (loop == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) swp_info_get(state, fOSC_start, state->srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) v, R, swp_ofs, &fOSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) &afcex_freq, &AFCEX_L, &AFCEX_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (rf_val_set(state, fOSC, state->srate, R) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (srst(state) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dprintk(verbose, MB86A16_ERROR, 1, "srst error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) msleep_interruptible(wait_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (mb86a16_read(state, 0x37, &SIG1) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) V[30 + v] = SIG1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) SIG1MIN, fOSC, afcex_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) swp_ofs, &SIG1); /* changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) signal_dupl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) for (j = 0; j < prev_freq_num; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if ((abs(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) signal_dupl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if ((signal_dupl == 0) && (swp_freq > 0) && (abs(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) prev_swp_freq[prev_freq_num] = swp_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) prev_freq_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) swp_info_get2(state, state->srate, R, swp_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) &afcex_freq, &fOSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) &AFCEX_L, &AFCEX_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (rf_val_set(state, fOSC, state->srate, R) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) signal = signal_det(state, state->srate, &SIG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (signal == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again...");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) smrt_info_get(state, state->srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (smrt_set(state, state->srate) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (v > vmax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) vmax_his = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (v < vmin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) vmin_his = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if ((i % 2 == 1) && (vmax_his == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if ((i % 2 == 0) && (vmin_his == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (i % 2 == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) v = (i + 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) v = -i / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if ((vmax_his == 1) && (vmin_his == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) loop = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (signal == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) S1T = 7 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) S0T = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) CREN = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) AFCEN = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) AFCEXEN = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (S01T_set(state, S1T, S0T) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) smrt_info_get(state, state->srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (smrt_set(state, state->srate) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (EN_set(state, CREN, AFCEN) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (srst(state) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) dprintk(verbose, MB86A16_ERROR, 1, "srst error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* delay 4~200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) wait_t = 200000 / state->master_clk + 200000 / state->srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) msleep(wait_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) afcerr = afcerr_chk(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (afcerr == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) swp_freq = fOSC * 1000 + afcerr ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) AFCEXEN = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (state->srate >= 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) smrt_d = state->srate / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) smrt_d = state->srate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) smrt_info_get(state, smrt_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (smrt_set(state, smrt_d) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) R = vco_dev_get(state, smrt_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (DAGC_data_set(state, 2, 0) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) temp_freq = swp_freq + (i - 1) * state->srate / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) wait_t = 200000 / state->master_clk + 40000 / smrt_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) msleep(wait_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dagcm[i] = dagcm_val_get(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if ((dagcm[0] > dagcm[1]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) (dagcm[0] > dagcm[2]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) temp_freq = swp_freq - 2 * state->srate / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) wait_t = 200000 / state->master_clk + 40000 / smrt_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) msleep(wait_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) dagcm[3] = dagcm_val_get(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (dagcm[3] > dagcm[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) delta_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) } else if ((dagcm[2] > dagcm[1]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) (dagcm[2] > dagcm[0]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) temp_freq = swp_freq + 2 * state->srate / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dprintk(verbose, MB86A16_ERROR, 1, "rf val set");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) wait_t = 200000 / state->master_clk + 40000 / smrt_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) msleep(wait_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) dagcm[3] = dagcm_val_get(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (dagcm[3] > dagcm[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) delta_freq = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) delta_freq = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) swp_freq += delta_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (abs(state->frequency * 1000 - swp_freq) > 3800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) S1T = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) S0T = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) CREN = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) AFCEN = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) AFCEXEN = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (S01T_set(state, S1T, S0T) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (DAGC_data_set(state, 0, 0) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) R = vco_dev_get(state, state->srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) smrt_info_get(state, state->srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (smrt_set(state, state->srate) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (EN_set(state, CREN, AFCEN) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (rf_val_set(state, fOSC, state->srate, R) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (srst(state) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) dprintk(verbose, MB86A16_ERROR, 1, "srst error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) wait_t = 7 + (10000 + state->srate / 2) / state->srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (wait_t == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) wait_t = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) msleep_interruptible(wait_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (mb86a16_read(state, 0x37, &SIG1) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (SIG1 > 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) wait_t = 7 + (917504 + state->srate / 2) / state->srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) } else if (SIG1 > 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) wait_t = 7 + (1048576 + state->srate / 2) / state->srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) } else if (SIG1 > 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) wait_t = 7 + (1310720 + state->srate / 2) / state->srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) } else if (SIG1 > 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) wait_t = 7 + (1572864 + state->srate / 2) / state->srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) wait_t = 7 + (2097152 + state->srate / 2) / state->srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) wait_t *= 2; /* FOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) S2T_set(state, S2T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) S45T_set(state, S4T, S5T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) Vi_set(state, ETH, VIA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) srst(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) msleep_interruptible(wait_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) sync = sync_chk(state, &VIRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (VIRM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (VIRM == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* 5/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (SIG1 > 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) wait_t = (786432 + state->srate / 2) / state->srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) wait_t = (1572864 + state->srate / 2) / state->srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) msleep_interruptible(wait_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (sync_chk(state, &junk) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) iq_vt_set(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) FEC_srst(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* 1/2, 2/3, 3/4, 7/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (SIG1 > 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) wait_t = (786432 + state->srate / 2) / state->srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) wait_t = (1572864 + state->srate / 2) / state->srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) msleep_interruptible(wait_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) SEQ_set(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) SEQ_set(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) sync = sync_chk(state, &junk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (sync) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) freqerr_chk(state, state->frequency, state->srate, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) mb86a16_read(state, 0x15, &agcval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) mb86a16_read(state, 0x26, &cnmval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) struct dvb_diseqc_master_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct mb86a16_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) u8 regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) regs = 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (cmd->msg_len > 5 || cmd->msg_len < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) for (i = 0; i < cmd->msg_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (mb86a16_write(state, regs, cmd->msg[i]) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) regs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) i += 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) msleep_interruptible(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (mb86a16_write(state, MB86A16_DCC1, i) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) enum fe_sec_mini_cmd burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) struct mb86a16_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) switch (burst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) case SEC_MINI_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) MB86A16_DCC1_TBEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) MB86A16_DCC1_TBO) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) case SEC_MINI_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) MB86A16_DCC1_TBEN) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) static int mb86a16_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) struct mb86a16_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) switch (tone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) case SEC_TONE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) MB86A16_DCC1_CTOE) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) case SEC_TONE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) struct mb86a16_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) state->frequency = p->frequency / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) state->srate = p->symbol_rate / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (!mb86a16_set_fe(state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) return DVBFE_ALGO_SEARCH_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) return DVBFE_ALGO_SEARCH_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) static void mb86a16_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) struct mb86a16_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) static int mb86a16_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) static int mb86a16_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) u32 timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) struct mb86a16_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) *ber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /* BER monitor invalid when BER_EN = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (ber_mon & 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /* coarse, fast calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) *ber = ber_tab & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (ber_mon & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * BER_SEL = 1, The monitored BER is the estimated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * value with a Reed-Solomon decoder error amount at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) * the deinterleaver output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) * monitored BER is expressed as a 20 bit output in total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) ber_rst = (ber_mon >> 3) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (ber_rst == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) timer = 12500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) else if (ber_rst == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) timer = 25000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) else if (ber_rst == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) timer = 50000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) else /* ber_rst == 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) timer = 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) *ber /= timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) * BER_SEL = 0, The monitored BER is the estimated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) * value with a Viterbi decoder error amount at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) * QPSK demodulator output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) * monitored BER is expressed as a 24 bit output in total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ber_tim = (ber_mon >> 1) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (ber_tim == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) timer = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) else /* ber_tim == 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) timer = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) *ber /= 2 ^ timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) u8 agcm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) struct mb86a16_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) *strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) *strength = ((0xff - agcm) * 100) / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) *strength = (0xffff - 0xff) + agcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) struct cnr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) u8 cn_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) u8 cn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static const struct cnr cnr_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) { 35, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) { 40, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) { 50, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) { 60, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) { 70, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) { 80, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) { 92, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) { 103, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) { 115, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) { 138, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) { 162, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) { 180, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) { 185, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) { 189, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) { 195, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) { 199, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) { 201, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) { 202, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) { 203, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) { 205, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) { 208, 30 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) struct mb86a16_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) int low_tide = 2, high_tide = 30, q_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) u8 cn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) *snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (mb86a16_read(state, 0x26, &cn) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (cn < cnr_tab[i].cn_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) *snr = cnr_tab[i].cn_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) q_level = (*snr * 100) / (high_tide - low_tide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) *snr = (0xffff - 0xff) + *snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) u8 dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) struct mb86a16_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) *ucblocks = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return DVBFE_ALGO_CUSTOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static const struct dvb_frontend_ops mb86a16_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .delsys = { SYS_DVBS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .name = "Fujitsu MB86A16 DVB-S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .frequency_min_hz = 950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .frequency_stepsize_hz = 3 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .symbol_rate_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .symbol_rate_max = 45000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .symbol_rate_tolerance = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) FE_CAN_FEC_7_8 | FE_CAN_QPSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) FE_CAN_FEC_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .release = mb86a16_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .get_frontend_algo = mb86a16_frontend_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .search = mb86a16_search,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .init = mb86a16_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .sleep = mb86a16_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .read_status = mb86a16_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .read_ber = mb86a16_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .read_signal_strength = mb86a16_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .read_snr = mb86a16_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .read_ucblocks = mb86a16_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .diseqc_send_master_cmd = mb86a16_send_diseqc_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .diseqc_send_burst = mb86a16_send_diseqc_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .set_tone = mb86a16_set_tone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) u8 dev_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct mb86a16_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) state->i2c_adap = i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) mb86a16_read(state, 0x7f, &dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (dev_id != 0xfe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) state->frontend.ops.set_voltage = state->config->set_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) EXPORT_SYMBOL(mb86a16_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) MODULE_AUTHOR("Manu Abraham");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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