Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *    Support for Legend Silicon GB20600 (a.k.a DMB-TH) demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *    LGS8913, LGS8GL5, LGS8G75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *    experimental support LGS8G42, LGS8G52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *    Copyright (C) 2007-2009 David T.L. Wong <davidtlwong@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *    Copyright (C) 2008 Sirius International (Hong Kong) Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *    Timothy Lee <timothy.lee@siriushk.com> (for initial work on LGS8GL5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef LGS8913_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define LGS8913_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct lgs8gxx_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	/* configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	const struct lgs8gxx_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	u16 curr_gi; /* current guard interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SC_MASK		0x1C	/* Sub-Carrier Modulation Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SC_QAM64	0x10	/* 64QAM modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SC_QAM32	0x0C	/* 32QAM modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SC_QAM16	0x08	/* 16QAM modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SC_QAM4NR	0x04	/* 4QAM-NR modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SC_QAM4		0x00	/* 4QAM modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LGS_FEC_MASK	0x03	/* FEC Rate Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LGS_FEC_0_4	0x00	/* FEC Rate 0.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LGS_FEC_0_6	0x01	/* FEC Rate 0.6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LGS_FEC_0_8	0x02	/* FEC Rate 0.8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TIM_MASK	  0x20	/* Time Interleave Length Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TIM_LONG	  0x20	/* Time Interleave Length = 720 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TIM_MIDDLE     0x00   /* Time Interleave Length = 240 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CF_MASK	0x80	/* Control Frame Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CF_EN	0x80	/* Control Frame On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GI_MASK	0x03	/* Guard Interval Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GI_420	0x00	/* 1/9 Guard Interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GI_595	0x01	/* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GI_945	0x02	/* 1/4 Guard Interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TS_PARALLEL	0x00	/* Parallel TS Output a.k.a. SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TS_SERIAL	0x01	/* Serial TS Output a.k.a. SSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TS_CLK_NORMAL		0x00	/* MPEG Clock Normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TS_CLK_INVERTED		0x02	/* MPEG Clock Inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TS_CLK_GATED		0x00	/* MPEG clock gated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TS_CLK_FREERUN		0x04	/* MPEG clock free running*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif