^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support for LGDT3306A - 8VSB/QAM-B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * - driver structure based on lgdt3305.[ch] by Michael Krufky
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * - code based on LG3306_V0.35 API by LG Electronics Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <media/dvb_math.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "lgdt3306a.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c-mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Older drivers treated QAM64 and QAM256 the same; that is the HW always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * used "Auto" mode during detection. Setting "forced_manual"=1 allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * the user to treat these modes as separate. For backwards compatibility,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * it's off by default. QAM_AUTO can now be specified to achive that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * effect even if "forced_manual"=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int forced_manual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) module_param(forced_manual, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_PARM_DESC(forced_manual, "if set, QAM64 and QAM256 will only lock to modulation specified");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DBG_INFO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DBG_REG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DBG_DUMP 4 /* FGR - comment out to remove dump code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define lg_debug(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) printk(KERN_DEBUG pr_fmt(fmt), ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define dbg_info(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (debug & DBG_INFO) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) lg_debug(fmt, ## arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define dbg_reg(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (debug & DBG_REG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) lg_debug(fmt, ## arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define lg_chkerr(ret) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int __ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __ret = (ret < 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (__ret) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pr_err("error %d on line %d\n", ret, __LINE__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct lgdt3306a_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct i2c_adapter *i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) const struct lgdt3306a_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) enum fe_modulation current_modulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 current_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct i2c_mux_core *muxc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * LG3306A Register Usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * (LG does not really name the registers, so this code does not either)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * 0000 -> 00FF Common control and status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * 1000 -> 10FF Synchronizer control and status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * 1F00 -> 1FFF Smart Antenna control and status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * 2100 -> 21FF VSB Equalizer control and status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * 2800 -> 28FF QAM Equalizer control and status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 3000 -> 30FF FEC control and status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum lgdt3306a_lock_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) LG3306_UNLOCK = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) LG3306_LOCK = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) LG3306_UNKNOWN_LOCK = 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum lgdt3306a_neverlock_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) LG3306_NL_INIT = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) LG3306_NL_PROCESS = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) LG3306_NL_LOCK = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) LG3306_NL_FAIL = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) LG3306_NL_UNKNOWN = 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) enum lgdt3306a_modulation {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) LG3306_VSB = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) LG3306_QAM64 = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) LG3306_QAM256 = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) LG3306_UNKNOWN_MODE = 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) enum lgdt3306a_lock_check {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) LG3306_SYNC_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) LG3306_FEC_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) LG3306_TR_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) LG3306_AGC_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #ifdef DBG_DUMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 buf[] = { reg >> 8, reg & 0xff, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .addr = state->cfg->i2c_addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .buf = buf, .len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = i2c_transfer(state->i2c_adap, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pr_err("error (addr %02x %02x <- %02x, err = %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) msg.buf[0], msg.buf[1], msg.buf[2], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 reg_buf[] = { reg >> 8, reg & 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { .addr = state->cfg->i2c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .flags = 0, .buf = reg_buf, .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { .addr = state->cfg->i2c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .flags = I2C_M_RD, .buf = val, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = i2c_transfer(state->i2c_adap, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pr_err("error (addr %02x reg %04x error (ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) state->cfg->i2c_addr, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define read_reg(state, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 __val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int ret = lgdt3306a_read_reg(state, reg, &__val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (lg_chkerr(ret)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __val = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u16 reg, int bit, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = lgdt3306a_read_reg(state, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val &= ~(1 << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val |= (onoff & 1) << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = lgdt3306a_write_reg(state, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) lg_chkerr(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dbg_info("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) lg_chkerr(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) enum lgdt3306a_mpeg_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dbg_info("(%d)\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* transport packet format - TPSENB=0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * start of packet signal duration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = lgdt3306a_read_reg(state, 0x0070, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) val |= 0x10; /* TPCLKSUPB=0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (mode == LGDT3306A_MPEG_PARALLEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) val &= ~0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = lgdt3306a_write_reg(state, 0x0070, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) lg_chkerr(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) enum lgdt3306a_tp_clock_edge edge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) enum lgdt3306a_tp_valid_polarity valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dbg_info("edge=%d, valid=%d\n", edge, valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = lgdt3306a_read_reg(state, 0x0070, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (edge == LGDT3306A_TPCLK_RISING_EDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) val |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (valid == LGDT3306A_TP_VALID_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) val |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = lgdt3306a_write_reg(state, 0x0070, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) lg_chkerr(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dbg_info("(%d)\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = lgdt3306a_read_reg(state, 0x0070, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * TPDATAOUTEN=0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) val &= ~0xa8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = lgdt3306a_write_reg(state, 0x0070, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* enable IFAGC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = lgdt3306a_read_reg(state, 0x0070, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) val |= 0xa8; /* enable bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = lgdt3306a_write_reg(state, 0x0070, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct lgdt3306a_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dbg_info("acquire=%d\n", acquire);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int lgdt3306a_power(struct lgdt3306a_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dbg_info("(%d)\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (mode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* into reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #ifdef DBG_DUMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) lgdt3306a_DumpAllRegs(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dbg_info("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* 0. Spectrum inversion detection manual; spectrum inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = lgdt3306a_read_reg(state, 0x0002, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) val &= 0xf7; /* SPECINVAUTO Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) val |= 0x04; /* SPECINV On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = lgdt3306a_write_reg(state, 0x0002, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* 2. Bandwidth mode for VSB(6MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = lgdt3306a_read_reg(state, 0x0009, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) val &= 0xe3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = lgdt3306a_write_reg(state, 0x0009, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* 3. QAM mode detection mode(None) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = lgdt3306a_read_reg(state, 0x0009, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = lgdt3306a_write_reg(state, 0x0009, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* 4. ADC sampling frequency rate(2x sampling) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = lgdt3306a_read_reg(state, 0x000d, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) val &= 0xbf; /* SAMPLING4XFEN=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = lgdt3306a_write_reg(state, 0x000d, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* FGR - disable any AICC filtering, testing only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* AICCFIXFREQ0 NT N-1(Video rejection) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* AICCFIXFREQ1 NT N-1(Audio rejection) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* FGR - this works well for HVR-1955,1975 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* 5. AICCOPMODE NT N-1 Adj. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* AICCFIXFREQ0 NT N-1(Video rejection) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* AICCFIXFREQ1 NT N-1(Audio rejection) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ret = lgdt3306a_read_reg(state, 0x001e, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) val &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) val |= 0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = lgdt3306a_write_reg(state, 0x001e, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = lgdt3306a_read_reg(state, 0x211f, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) val &= 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = lgdt3306a_write_reg(state, 0x211f, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = lgdt3306a_read_reg(state, 0x1061, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) val &= 0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) val |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ret = lgdt3306a_write_reg(state, 0x1061, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = lgdt3306a_read_reg(state, 0x103d, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) val &= 0xcf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = lgdt3306a_write_reg(state, 0x103d, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = lgdt3306a_read_reg(state, 0x2141, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) val &= 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = lgdt3306a_write_reg(state, 0x2141, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = lgdt3306a_read_reg(state, 0x2135, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) val &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) val |= 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ret = lgdt3306a_write_reg(state, 0x2135, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret = lgdt3306a_read_reg(state, 0x0003, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) val &= 0xf7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ret = lgdt3306a_write_reg(state, 0x0003, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret = lgdt3306a_read_reg(state, 0x001c, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) val &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = lgdt3306a_write_reg(state, 0x001c, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* 6. EQ step size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = lgdt3306a_read_reg(state, 0x2179, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) val &= 0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = lgdt3306a_write_reg(state, 0x2179, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = lgdt3306a_read_reg(state, 0x217a, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) val &= 0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ret = lgdt3306a_write_reg(state, 0x217a, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* 7. Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = lgdt3306a_soft_reset(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dbg_info("complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dbg_info("modulation=%d\n", modulation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* 1a. Spectrum inversion detection to Auto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ret = lgdt3306a_read_reg(state, 0x0002, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) val &= 0xfb; /* SPECINV Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) val |= 0x08; /* SPECINVAUTO On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = lgdt3306a_write_reg(state, 0x0002, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* 2. Bandwidth mode for QAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = lgdt3306a_read_reg(state, 0x0009, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = lgdt3306a_write_reg(state, 0x0009, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* 3. : 64QAM/256QAM detection(manual, auto) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = lgdt3306a_read_reg(state, 0x0009, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) val &= 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Check for forced Manual modulation modes; otherwise always "auto" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if(forced_manual && (modulation != QAM_AUTO)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) val |= 0x01; /* STDOPDETCMODE[1:0]= 1=Manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) val |= 0x02; /* STDOPDETCMODE[1:0]= 2=Auto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = lgdt3306a_write_reg(state, 0x0009, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* 3a. : 64QAM/256QAM selection for manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = lgdt3306a_read_reg(state, 0x101a, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) val &= 0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (modulation == QAM_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = lgdt3306a_write_reg(state, 0x101a, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* 4. ADC sampling frequency rate(4x sampling) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret = lgdt3306a_read_reg(state, 0x000d, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) val &= 0xbf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) val |= 0x40; /* SAMPLING4XFEN=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = lgdt3306a_write_reg(state, 0x000d, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* 5. No AICC operation in QAM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = lgdt3306a_read_reg(state, 0x0024, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) val &= 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = lgdt3306a_write_reg(state, 0x0024, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* 5.1 V0.36 SRDCHKALWAYS : For better QAM detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ret = lgdt3306a_read_reg(state, 0x000a, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) val &= 0xfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) val |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = lgdt3306a_write_reg(state, 0x000a, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* 5.2 V0.36 Control of "no signal" detector function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = lgdt3306a_read_reg(state, 0x2849, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) val &= 0xdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ret = lgdt3306a_write_reg(state, 0x2849, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* 5.3 Fix for Blonder Tongue HDE-2H-QAM and AQM modulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = lgdt3306a_read_reg(state, 0x302b, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) val &= 0x7f; /* SELFSYNCFINDEN_CQS=0; disable auto reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = lgdt3306a_write_reg(state, 0x302b, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* 6. Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = lgdt3306a_soft_reset(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dbg_info("complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dbg_info("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) switch (p->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case VSB_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret = lgdt3306a_set_vsb(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case QAM_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ret = lgdt3306a_set_qam(state, p->modulation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) state->current_modulation = p->modulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* TODO: anything we want to do here??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dbg_info("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) switch (p->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) case VSB_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) case QAM_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int inversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dbg_info("(%d)\n", inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dbg_info("(%d)\n", enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct dtv_frontend_properties *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int inversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dbg_info("(%d)\n", inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * FGR - spectral_inversion defaults already set for VSB and QAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * can enable later if desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = lgdt3306a_set_inversion(state, inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) switch (p->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) case VSB_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* Manual only for VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ret = lgdt3306a_set_inversion_auto(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) case QAM_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Auto ok for QAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = lgdt3306a_set_inversion_auto(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int lgdt3306a_set_if(struct lgdt3306a_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u16 if_freq_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u8 nco1, nco2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) switch (p->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) case VSB_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if_freq_khz = state->cfg->vsb_if_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case QAM_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if_freq_khz = state->cfg->qam_if_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) switch (if_freq_khz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) pr_warn("IF=%d KHz is not supported, 3250 assumed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if_freq_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case 3250: /* 3.25Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) nco1 = 0x34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) nco2 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) case 3500: /* 3.50Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) nco1 = 0x38;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) nco2 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) case 4000: /* 4.00Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) nco1 = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) nco2 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case 5000: /* 5.00Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) nco1 = 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) nco2 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) case 5380: /* 5.38Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) nco1 = 0x56;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) nco2 = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = lgdt3306a_write_reg(state, 0x0010, nco1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = lgdt3306a_write_reg(state, 0x0011, nco2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dbg_info("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct lgdt3306a_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (state->cfg->deny_i2c_rptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dbg_info("(%d)\n", enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* NI2CRPTEN=0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int lgdt3306a_sleep(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dbg_info("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) state->current_frequency = -1; /* force re-tune, when we wake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ret = lgdt3306a_power(state, 0); /* power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) lg_chkerr(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct lgdt3306a_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return lgdt3306a_sleep(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static int lgdt3306a_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct lgdt3306a_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dbg_info("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* 1. Normal operation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* 2. Spectrum inversion auto detection (Not valid for VSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ret = lgdt3306a_set_inversion_auto(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* 3. Spectrum inversion(According to the tuner configuration) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ret = lgdt3306a_set_inversion(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* 4. Peak-to-peak voltage of ADC input signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* 5. ADC output data capture clock phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* 0=same phase as ADC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* 5a. ADC sampling clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* 6. Automatic PLL set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* PLLSETAUTO=0x40; 0=off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (state->cfg->xtalMHz == 24) { /* 24MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ret = lgdt3306a_read_reg(state, 0x0005, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) val &= 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) val |= 0x25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) ret = lgdt3306a_write_reg(state, 0x0005, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ret = lgdt3306a_read_reg(state, 0x000d, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) val &= 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) val |= 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ret = lgdt3306a_write_reg(state, 0x000d, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* 7. Frequency for PLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ret = lgdt3306a_read_reg(state, 0x0005, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) val &= 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) val |= 0x25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ret = lgdt3306a_write_reg(state, 0x0005, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ret = lgdt3306a_read_reg(state, 0x000d, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) val &= 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) val |= 0x19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ret = lgdt3306a_write_reg(state, 0x000d, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* 9. Center frequency of input signal of ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* 10. Fixed gain error value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* 10a. VSB TR BW gear shift initial step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ret = lgdt3306a_read_reg(state, 0x103c, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) val &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ret = lgdt3306a_write_reg(state, 0x103c, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* 10b. Timing offset calibration in low temperature for VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ret = lgdt3306a_read_reg(state, 0x103d, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) val &= 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) val |= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = lgdt3306a_write_reg(state, 0x103d, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* 10c. Timing offset calibration in low temperature for QAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret = lgdt3306a_read_reg(state, 0x1036, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) val &= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) val |= 0x0c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ret = lgdt3306a_write_reg(state, 0x1036, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* 11. Using the imaginary part of CIR in CIR loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ret = lgdt3306a_read_reg(state, 0x211f, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) val &= 0xef; /* do not use imaginary of CIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ret = lgdt3306a_write_reg(state, 0x211f, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* 12. Control of no signal detector function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ret = lgdt3306a_read_reg(state, 0x2849, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ret = lgdt3306a_write_reg(state, 0x2849, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* FGR - put demod in some known mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ret = lgdt3306a_set_vsb(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* 13. TP stream format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* 14. disable output buses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) ret = lgdt3306a_mpeg_tristate(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /* 15. Sleep (in reset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ret = lgdt3306a_sleep(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) lg_chkerr(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) c->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct lgdt3306a_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dbg_info("(%d, %d)\n", p->frequency, p->modulation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (state->current_frequency == p->frequency &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) state->current_modulation == p->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) dbg_info(" (already set, skipping ...)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) state->current_frequency = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) state->current_modulation = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ret = lgdt3306a_power(state, 1); /* power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ret = fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) state->current_frequency = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ret = lgdt3306a_set_modulation(state, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ret = lgdt3306a_agc_setup(state, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ret = lgdt3306a_set_if(state, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = lgdt3306a_spectral_inversion(state, p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) state->cfg->spectral_inversion ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ret = lgdt3306a_mpeg_mode_polarity(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) state->cfg->tpclk_edge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) state->cfg->tpvalid_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ret = lgdt3306a_soft_reset(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #ifdef DBG_DUMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) lgdt3306a_DumpAllRegs(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) state->current_frequency = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static int lgdt3306a_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct lgdt3306a_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dbg_info("(%u, %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) state->current_frequency, state->current_modulation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) p->modulation = state->current_modulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) p->frequency = state->current_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return DVBFE_ALGO_CUSTOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return DVBFE_ALGO_HW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) u8 snrRef, maxPowerMan, nCombDet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) u16 fbDlyCir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ret = lgdt3306a_read_reg(state, 0x21a1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) snrRef = val & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = lgdt3306a_read_reg(state, 0x2191, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) nCombDet = (val & 0x80) >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ret = lgdt3306a_read_reg(state, 0x2180, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) fbDlyCir = (val & 0x03) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret = lgdt3306a_read_reg(state, 0x2181, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) fbDlyCir |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) snrRef, maxPowerMan, nCombDet, fbDlyCir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* Carrier offset sub loop bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) ret = lgdt3306a_read_reg(state, 0x1061, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) val &= 0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if ((snrRef > 18) && (maxPowerMan > 0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) && (nCombDet == 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* SNR is over 18dB and no ghosting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) val |= 0x00; /* final bandwidth = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) val |= 0x04; /* final bandwidth = 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) ret = lgdt3306a_write_reg(state, 0x1061, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* Adjust Notch Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ret = lgdt3306a_read_reg(state, 0x0024, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) val &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (nCombDet == 0) { /* Turn on the Notch Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) val |= 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ret = lgdt3306a_write_reg(state, 0x0024, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /* VSB Timing Recovery output normalization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ret = lgdt3306a_read_reg(state, 0x103d, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) val &= 0xcf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) val |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret = lgdt3306a_write_reg(state, 0x103d, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static enum lgdt3306a_modulation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ret = lgdt3306a_read_reg(state, 0x0081, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (val & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) dbg_info("VSB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return LG3306_VSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (val & 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = lgdt3306a_read_reg(state, 0x00a6, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) val = val >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (val & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) dbg_info("QAM256\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return LG3306_QAM256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) dbg_info("QAM64\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return LG3306_QAM64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) pr_warn("UNKNOWN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return LG3306_UNKNOWN_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static enum lgdt3306a_lock_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) enum lgdt3306a_lock_check whatLock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) enum lgdt3306a_modulation modeOper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) enum lgdt3306a_lock_status lockStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) modeOper = LG3306_UNKNOWN_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) switch (whatLock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) case LG3306_SYNC_LOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ret = lgdt3306a_read_reg(state, 0x00a6, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if ((val & 0x80) == 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) lockStatus = LG3306_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) lockStatus = LG3306_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dbg_info("SYNC_LOCK=%x\n", lockStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) case LG3306_AGC_LOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ret = lgdt3306a_read_reg(state, 0x0080, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if ((val & 0x40) == 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) lockStatus = LG3306_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) lockStatus = LG3306_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dbg_info("AGC_LOCK=%x\n", lockStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) case LG3306_TR_LOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) modeOper = lgdt3306a_check_oper_mode(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ret = lgdt3306a_read_reg(state, 0x1094, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if ((val & 0x80) == 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) lockStatus = LG3306_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) lockStatus = LG3306_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) lockStatus = LG3306_UNKNOWN_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) dbg_info("TR_LOCK=%x\n", lockStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) case LG3306_FEC_LOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) modeOper = lgdt3306a_check_oper_mode(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ret = lgdt3306a_read_reg(state, 0x0080, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if ((val & 0x10) == 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) lockStatus = LG3306_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) lockStatus = LG3306_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) lockStatus = LG3306_UNKNOWN_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dbg_info("FEC_LOCK=%x\n", lockStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) lockStatus = LG3306_UNKNOWN_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) pr_warn("UNKNOWN whatLock=%d\n", whatLock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return lockStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static enum lgdt3306a_neverlock_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) enum lgdt3306a_neverlock_status lockStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ret = lgdt3306a_read_reg(state, 0x0080, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) dbg_info("NeverLock=%d", lockStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return lockStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* Channel variation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* SNR of Frame sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ret = lgdt3306a_read_reg(state, 0x21a1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) snrRef = val & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* Strong Main CIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = lgdt3306a_read_reg(state, 0x2199, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) mainStrong = (val & 0x40) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ret = lgdt3306a_read_reg(state, 0x0090, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) aiccrejStatus = (val & 0xf0) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /* Dynamic ghost exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if ((mainStrong == 0) && (currChDiffACQ > 0x70))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (mainStrong == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ret = lgdt3306a_read_reg(state, 0x2135, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) val &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) val |= 0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret = lgdt3306a_write_reg(state, 0x2135, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) ret = lgdt3306a_read_reg(state, 0x2141, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) val &= 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) val |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ret = lgdt3306a_write_reg(state, 0x2141, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) } else { /* Weak ghost or static channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) ret = lgdt3306a_read_reg(state, 0x2135, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) val &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) val |= 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ret = lgdt3306a_write_reg(state, 0x2135, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ret = lgdt3306a_read_reg(state, 0x2141, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) val &= 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) val |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ret = lgdt3306a_write_reg(state, 0x2141, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static enum lgdt3306a_lock_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) syncLockStatus = lgdt3306a_check_lock_status(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) LG3306_SYNC_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (syncLockStatus == LG3306_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dbg_info("locked(%d)\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return LG3306_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) dbg_info("not locked\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) return LG3306_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) static enum lgdt3306a_lock_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) FECLockStatus = lgdt3306a_check_lock_status(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) LG3306_FEC_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (FECLockStatus == LG3306_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) dbg_info("locked(%d)\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return FECLockStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) dbg_info("not locked\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return FECLockStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static enum lgdt3306a_neverlock_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) NLLockStatus = lgdt3306a_check_neverlock_status(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (NLLockStatus == LG3306_NL_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) dbg_info("NL_LOCK(%d)\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return NLLockStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) dbg_info("NLLockStatus=%d\n", NLLockStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return NLLockStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) ret = lgdt3306a_read_reg(state, 0x00fa, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static const u32 valx_x10[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) 10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static const u32 log10x_x1000[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static u32 log10_x1000(u32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) u32 diff_val, step_val, step_log10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) u32 log_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (x <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return -1000000; /* signal error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (x == 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return 0; /* log(1)=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (x < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) while (x < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) x = x * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) log_val--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) } else { /* x > 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) while (x >= 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) x = x / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) log_val++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) log_val *= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (x == 10) /* was our input an exact multiple of 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return log_val; /* don't need to interpolate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* find our place on the log curve */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) for (i = 1; i < ARRAY_SIZE(valx_x10); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (valx_x10[i] >= x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (i == ARRAY_SIZE(valx_x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return log_val + log10x_x1000[i - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) diff_val = x - valx_x10[i-1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) step_val = valx_x10[i] - valx_x10[i - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) /* do a linear interpolation to get in-between values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return log_val + log10x_x1000[i - 1] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) ((diff_val*step_log10) / step_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) u32 mse; /* Mean-Square Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) u32 pwr; /* Constelation power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) u32 snr_x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) mse = (read_reg(state, 0x00ec) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) (read_reg(state, 0x00ed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) pwr = (read_reg(state, 0x00e8) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) (read_reg(state, 0x00e9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (mse == 0) /* no signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) dbg_info("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return snr_x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static enum lgdt3306a_lock_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) u8 cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) u8 packet_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) u32 snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) for (cnt = 0; cnt < 10; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) dbg_info("no sync lock!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return LG3306_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) ret = lgdt3306a_pre_monitoring(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) packet_error = lgdt3306a_get_packet_error(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) snr = lgdt3306a_calculate_snr_x100(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if ((snr >= 1500) && (packet_error < 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) return LG3306_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) dbg_info("not locked!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return LG3306_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) static enum lgdt3306a_lock_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) u8 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) u8 packet_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) u32 snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) for (cnt = 0; cnt < 10; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) dbg_info("no fec lock!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return LG3306_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) packet_error = lgdt3306a_get_packet_error(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) snr = lgdt3306a_calculate_snr_x100(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if ((snr >= 1500) && (packet_error < 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) return LG3306_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) dbg_info("not locked!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) return LG3306_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static int lgdt3306a_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) struct lgdt3306a_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) u16 strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (fe->ops.tuner_ops.get_rf_strength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) dbg_info("strength=%d\n", strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) *status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) switch (state->current_modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) case QAM_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) *status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) case VSB_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) *status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ret = lgdt3306a_monitor_vsb(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (*status & FE_HAS_SYNC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) c->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) c->cnr.stat[0].svalue = lgdt3306a_calculate_snr_x100(state) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) c->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) struct lgdt3306a_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) state->snr = lgdt3306a_calculate_snr_x100(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) /* report SNR in dB * 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) *snr = state->snr/10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) * Calculate some sort of "strength" from SNR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) struct lgdt3306a_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) u16 snr; /* snr_x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) u32 ref_snr; /* snr*100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) u32 str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) *strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) switch (state->current_modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) case VSB_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) ref_snr = 1600; /* 16dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) case QAM_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) /* need to know actual modulation to set proper SNR baseline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) ret = lgdt3306a_read_reg(state, 0x00a6, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if(val & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) ref_snr = 2800; /* QAM-256 28dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) ref_snr = 2200; /* QAM-64 22dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) ret = fe->ops.read_snr(fe, &snr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (state->snr <= (ref_snr - 100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) str = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) else if (state->snr <= ref_snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) str = (0xffff * 65) / 100; /* 65% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) str = state->snr - ref_snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) str /= 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) str += 78; /* 78%-100% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (str > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) str = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) str = (0xffff * str) / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) *strength = (u16)str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) dbg_info("strength=%u\n", *strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) struct lgdt3306a_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) *ber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /* FGR - FIXME - I don't know what value is expected by dvb_core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) * what is the scale of the value?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) *ber = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) dbg_info("ber=%u\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) struct lgdt3306a_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) *ucblocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) /* FGR - FIXME - I don't know what value is expected by dvb_core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * what happens when value wraps? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) dbg_info("ucblocks=%u\n", *ucblocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) unsigned int mode_flags, unsigned int *delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) struct lgdt3306a_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) dbg_info("re_tune=%u\n", re_tune);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) if (re_tune) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) state->current_frequency = -1; /* force re-tune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) ret = lgdt3306a_set_parameters(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) *delay = 125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) ret = lgdt3306a_read_status(fe, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) struct dvb_frontend_tune_settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) *fe_tune_settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) fe_tune_settings->min_delay_ms = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) dbg_info("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static enum dvbfe_search lgdt3306a_search(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) enum fe_status status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) /* set frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ret = lgdt3306a_set_parameters(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) ret = lgdt3306a_read_status(fe, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) /* check if we have a valid signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if (status & FE_HAS_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) return DVBFE_ALGO_SEARCH_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) return DVBFE_ALGO_SEARCH_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) dbg_info("failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) return DVBFE_ALGO_SEARCH_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) static void lgdt3306a_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) struct lgdt3306a_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) dbg_info("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static const struct dvb_frontend_ops lgdt3306a_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) struct lgdt3306a_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) dbg_info("(%d-%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) config ? config->i2c_addr : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) state->cfg = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) state->i2c_adap = i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) memcpy(&state->frontend.ops, &lgdt3306a_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) /* verify that we're talking to a lg3306a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) /* FGR - NOTE - there is no obvious ChipId to check; we check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) * some "known" bits after reset, but it's still just a guess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) ret = lgdt3306a_read_reg(state, 0x0000, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if ((val & 0x74) != 0x74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) /* FIXME - re-enable when we know this is right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) ret = lgdt3306a_read_reg(state, 0x0001, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) if ((val & 0xf6) != 0xc6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) /* FIXME - re-enable when we know this is right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) ret = lgdt3306a_read_reg(state, 0x0002, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (lg_chkerr(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) if ((val & 0x73) != 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /* FIXME - re-enable when we know this is right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) state->current_frequency = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) state->current_modulation = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) lgdt3306a_sleep(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) pr_warn("unable to detect LGDT3306A hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) EXPORT_SYMBOL(lgdt3306a_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) #ifdef DBG_DUMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static const short regtab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) 0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) 0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) 0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) 0x0003, /* AGCRFOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) 0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) 0x0005, /* PLLINDIVSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) 0x0006, /* PLLCTRL[7:0] 11100001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) 0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) 0x0008, /* STDOPMODE[7:0] 10000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) 0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) 0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) 0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) 0x000d, /* x SAMPLING4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) 0x000e, /* SAMFREQ[15:8] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) 0x000f, /* SAMFREQ[7:0] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) 0x0010, /* IFFREQ[15:8] 01100000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) 0x0011, /* IFFREQ[7:0] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) 0x0012, /* AGCEN AGCREFMO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) 0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) 0x0014, /* AGCFIXVALUE[7:0] 01111111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) 0x0015, /* AGCREF[15:8] 00001010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) 0x0016, /* AGCREF[7:0] 11100100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) 0x0017, /* AGCDELAY[7:0] 00100000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) 0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) 0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) 0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) 0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) 0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) 0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) 0x0020, /* AICCDETTH[15:8] 01111100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) 0x0021, /* AICCDETTH[7:0] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) 0x0022, /* AICCOFFTH[15:8] 00000101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) 0x0023, /* AICCOFFTH[7:0] 11100000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) 0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) 0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) 0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) 0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) 0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) 0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) 0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) 0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) 0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) 0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) 0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) 0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) 0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) 0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) 0x0032, /* DAGC1STEN DAGC1STER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) 0x0033, /* DAGC1STREF[15:8] 00001010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) 0x0034, /* DAGC1STREF[7:0] 11100100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) 0x0035, /* DAGC2NDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) 0x0036, /* DAGC2NDREF[15:8] 00001010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) 0x0037, /* DAGC2NDREF[7:0] 10000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) 0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) 0x003d, /* 1'b1 SAMGEARS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) 0x0040, /* SAMLFGMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) 0x0041, /* SAMLFBWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) 0x0044, /* 1'b1 CRGEARSHE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) 0x0045, /* CRLFGMAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) 0x0046, /* CFLFBWMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) 0x0047, /* CRLFGMAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) 0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) 0x0049, /* CRLFBWMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) 0x004a, /* CRLFBWMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) 0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) 0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) 0x0071, /* TPSENB TPSSOPBITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) 0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) 0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) 0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) 0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) 0x0078, /* NBERPOLY[31:24] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) 0x0079, /* NBERPOLY[23:16] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) 0x007a, /* NBERPOLY[15:8] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) 0x007b, /* NBERPOLY[7:0] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) 0x007c, /* NBERPED[31:24] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) 0x007d, /* NBERPED[23:16] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) 0x007e, /* NBERPED[15:8] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) 0x007f, /* NBERPED[7:0] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) 0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) 0x0085, /* SPECINVST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) 0x0088, /* SYSLOCKTIME[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) 0x0089, /* SYSLOCKTIME[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) 0x008c, /* FECLOCKTIME[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) 0x008d, /* FECLOCKTIME[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) 0x008e, /* AGCACCOUT[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) 0x008f, /* AGCACCOUT[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) 0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) 0x0091, /* AICCVSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) 0x009c, /* CARRFREQOFFSET[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) 0x009d, /* CARRFREQOFFSET[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) 0x00a1, /* SAMFREQOFFSET[23:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) 0x00a2, /* SAMFREQOFFSET[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) 0x00a3, /* SAMFREQOFFSET[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) 0x00a6, /* SYNCLOCK SYNCLOCKH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) #if 0 /* covered elsewhere */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) 0x00e8, /* CONSTPWR[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) 0x00e9, /* CONSTPWR[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) 0x00ea, /* BMSE[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) 0x00eb, /* BMSE[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) 0x00ec, /* MSE[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) 0x00ed, /* MSE[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) 0x00ee, /* CONSTI[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) 0x00ef, /* CONSTQ[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) 0x00f4, /* TPIFTPERRCNT[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) 0x00f5, /* TPCORREC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) 0x00f6, /* VBBER[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) 0x00f7, /* VBBER[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) 0x00f8, /* VABER[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) 0x00f9, /* VABER[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) 0x00fa, /* TPERRCNT[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) 0x00fb, /* NBERLOCK x x x x x x x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) 0x00fc, /* NBERVALUE[31:24] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) 0x00fd, /* NBERVALUE[23:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) 0x00fe, /* NBERVALUE[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) 0x00ff, /* NBERVALUE[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) 0x1000, /* 1'b0 WODAGCOU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) 0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) 0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) 0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) 0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) 0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) 0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) 0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) 0x103f, /* SAMZTEDSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) 0x105d, /* EQSTATUSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) 0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) 0x1060, /* 1'b1 EQSTATUSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) 0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) 0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) 0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) 0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) 0x106e, /* x x x x x CREPHNEN_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) 0x106f, /* CREPHNTH_V[7:0] 00010101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) 0x1072, /* CRSWEEPN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) 0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) 0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) 0x1080, /* DAFTSTATUS[1:0] x x x x x x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) 0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) 0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) 0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) #if 0 /* SMART_ANT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) 0x1f00, /* MODEDETE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) 0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) 0x1f03, /* NUMOFANT[7:0] 10000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) 0x1f04, /* x SELMASK[6:0] x0000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) 0x1f05, /* x SETMASK[6:0] x0000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) 0x1f06, /* x TXDATA[6:0] x0000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) 0x1f07, /* x CHNUMBER[6:0] x0000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) 0x1f09, /* AGCTIME[23:16] 10011000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) 0x1f0a, /* AGCTIME[15:8] 10010110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) 0x1f0b, /* AGCTIME[7:0] 10000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) 0x1f0c, /* ANTTIME[31:24] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) 0x1f0d, /* ANTTIME[23:16] 00000011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) 0x1f0e, /* ANTTIME[15:8] 10010000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) 0x1f0f, /* ANTTIME[7:0] 10010000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) 0x1f11, /* SYNCTIME[23:16] 10011000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) 0x1f12, /* SYNCTIME[15:8] 10010110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) 0x1f13, /* SYNCTIME[7:0] 10000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) 0x1f14, /* SNRTIME[31:24] 00000001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) 0x1f15, /* SNRTIME[23:16] 01111101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) 0x1f16, /* SNRTIME[15:8] 01111000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) 0x1f17, /* SNRTIME[7:0] 01000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) 0x1f19, /* FECTIME[23:16] 00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) 0x1f1a, /* FECTIME[15:8] 01110010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) 0x1f1b, /* FECTIME[7:0] 01110000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) 0x1f1d, /* FECTHD[7:0] 00000011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) 0x1f1f, /* SNRTHD[23:16] 00001000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) 0x1f20, /* SNRTHD[15:8] 01111111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) 0x1f21, /* SNRTHD[7:0] 10000101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) 0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) 0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) 0x1f82, /* x x x SCANOPCD[4:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) 0x1f83, /* x x x x MAINOPCD[3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) 0x1f84, /* x x RXDATA[13:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) 0x1f85, /* RXDATA[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) 0x1f86, /* x x SDTDATA[13:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) 0x1f87, /* SDTDATA[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) 0x1f89, /* ANTSNR[23:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) 0x1f8a, /* ANTSNR[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) 0x1f8b, /* ANTSNR[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) 0x1f8c, /* x x x x ANTFEC[13:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) 0x1f8d, /* ANTFEC[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) 0x1f8e, /* MAXCNT[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) 0x1f8f, /* SCANCNT[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) 0x1f91, /* MAXPW[23:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) 0x1f92, /* MAXPW[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) 0x1f93, /* MAXPW[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) 0x1f95, /* CURPWMSE[23:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) 0x1f96, /* CURPWMSE[15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) 0x1f97, /* CURPWMSE[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) #endif /* SMART_ANT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) 0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) 0x212a, /* EQAUTOST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) 0x2122, /* CHFAST[7:0] 01100000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) 0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) 0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) 0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) 0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) 0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) 0x2162, /* AICCCTRLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) 0x2173, /* PHNCNFCNT[7:0] 00000100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) 0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) 0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) 0x217e, /* CNFCNTTPIF[7:0] 00001000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) 0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) 0x2180, /* x x x x x x FBDLYCIR[9:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) 0x2181, /* FBDLYCIR[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) 0x2185, /* MAXPWRMAIN[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) 0x2191, /* NCOMBDET x x x x x x x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) 0x2199, /* x MAINSTRON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) 0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) 0x21a1, /* x x SNRREF[5:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) 0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) 0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) 0x2847, /* ENNOSIGDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) 0x2849, /* 1'b1 1'b1 NOUSENOSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) 0x284a, /* EQINITWAITTIME[7:0] 01100100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) 0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) 0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) 0x3031, /* FRAMELOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) 0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) 0x30a9, /* VDLOCK_Q FRAMELOCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) 0x30aa, /* MPEGLOCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) #define numDumpRegs (ARRAY_SIZE(regtab))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) static u8 regval1[numDumpRegs] = {0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) static u8 regval2[numDumpRegs] = {0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) memset(regval2, 0xff, sizeof(regval2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) lgdt3306a_DumpRegs(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) int sav_debug = debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if ((debug & DBG_DUMP) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) lg_debug("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) for (i = 0; i < numDumpRegs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) lgdt3306a_read_reg(state, regtab[i], ®val1[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) if (regval1[i] != regval2[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) lg_debug(" %04X = %02X\n", regtab[i], regval1[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) regval2[i] = regval1[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) debug = sav_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) #endif /* DBG_DUMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) static const struct dvb_frontend_ops lgdt3306a_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .frequency_min_hz = 54 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .frequency_max_hz = 858 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .frequency_stepsize_hz = 62500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .caps = FE_CAN_QAM_AUTO | FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .i2c_gate_ctrl = lgdt3306a_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .init = lgdt3306a_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .sleep = lgdt3306a_fe_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) /* if this is set, it overrides the default swzigzag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .tune = lgdt3306a_tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .set_frontend = lgdt3306a_set_parameters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .get_frontend = lgdt3306a_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .get_frontend_algo = lgdt3306a_get_frontend_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .get_tune_settings = lgdt3306a_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .read_status = lgdt3306a_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .read_ber = lgdt3306a_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .read_signal_strength = lgdt3306a_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .read_snr = lgdt3306a_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .read_ucblocks = lgdt3306a_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .release = lgdt3306a_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .ts_bus_ctrl = lgdt3306a_ts_bus_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .search = lgdt3306a_search,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) static int lgdt3306a_select(struct i2c_mux_core *muxc, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) struct i2c_client *client = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) struct lgdt3306a_state *state = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) return lgdt3306a_i2c_gate_ctrl(&state->frontend, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) static int lgdt3306a_deselect(struct i2c_mux_core *muxc, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) struct i2c_client *client = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) struct lgdt3306a_state *state = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) return lgdt3306a_i2c_gate_ctrl(&state->frontend, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) static int lgdt3306a_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) struct lgdt3306a_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) struct lgdt3306a_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) config = kmemdup(client->dev.platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) sizeof(struct lgdt3306a_config), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) if (config == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) config->i2c_addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) fe = lgdt3306a_attach(config, client->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) if (fe == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) goto err_fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) i2c_set_clientdata(client, fe->demodulator_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) state->frontend.ops.release = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) /* create mux i2c adapter for tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) state->muxc = i2c_mux_alloc(client->adapter, &client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) 1, 0, I2C_MUX_LOCKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) lgdt3306a_select, lgdt3306a_deselect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) if (!state->muxc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) state->muxc->priv = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) fe->ops.i2c_gate_ctrl = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) *config->i2c_adapter = state->muxc->adapter[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) *config->fe = fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) dev_info(&client->dev, "LG Electronics LGDT3306A successfully identified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) err_kfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) err_fe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) kfree(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) dev_warn(&client->dev, "probe failed = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) static int lgdt3306a_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) struct lgdt3306a_state *state = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) i2c_mux_del_adapters(state->muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) state->frontend.ops.release = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) state->frontend.demodulator_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) kfree(state->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) static const struct i2c_device_id lgdt3306a_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) {"lgdt3306a", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) MODULE_DEVICE_TABLE(i2c, lgdt3306a_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) static struct i2c_driver lgdt3306a_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .name = "lgdt3306a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .probe = lgdt3306a_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .remove = lgdt3306a_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .id_table = lgdt3306a_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) module_i2c_driver(lgdt3306a_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) MODULE_VERSION("0.2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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