Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *    Support for LG Electronics LGDT3304 and LGDT3305 - VSB/QAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *    Copyright (C) 2008, 2009, 2010 Michael Krufky <mkrufky@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _LGDT3305_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _LGDT3305_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) enum lgdt3305_mpeg_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	LGDT3305_MPEG_PARALLEL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	LGDT3305_MPEG_SERIAL = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum lgdt3305_tp_clock_edge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	LGDT3305_TPCLK_RISING_EDGE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	LGDT3305_TPCLK_FALLING_EDGE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum lgdt3305_tp_clock_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	LGDT3305_TPCLK_GATED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	LGDT3305_TPCLK_FIXED = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum lgdt3305_tp_valid_polarity {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	LGDT3305_TP_VALID_LOW = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	LGDT3305_TP_VALID_HIGH = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum lgdt_demod_chip_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	LGDT3305 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	LGDT3304 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct lgdt3305_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	u8 i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	/* user defined IF frequency in KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	u16 qam_if_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	u16 vsb_if_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	/* AGC Power reference - defaults are used if left unset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	u16 usref_8vsb;   /* default: 0x32c4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	u16 usref_qam64;  /* default: 0x5400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	u16 usref_qam256; /* default: 0x2a80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	/* disable i2c repeater - 0:repeater enabled 1:repeater disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	unsigned int deny_i2c_rptr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	/* spectral inversion - 0:disabled 1:enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	unsigned int spectral_inversion:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	/* use RF AGC loop - 0:disabled 1:enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	unsigned int rf_agc_loop:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	enum lgdt3305_mpeg_mode mpeg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	enum lgdt3305_tp_clock_edge tpclk_edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	enum lgdt3305_tp_clock_mode tpclk_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	enum lgdt3305_tp_valid_polarity tpvalid_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	enum lgdt_demod_chip_type demod_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #if IS_REACHABLE(CONFIG_DVB_LGDT3305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 				     struct i2c_adapter *i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 				     struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif /* CONFIG_DVB_LGDT3305 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif /* _LGDT3305_H_ */