^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support for LG2160 - ATSC/MH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Michael Krufky <mkrufky@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "lg2160.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DBG_INFO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DBG_REG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define lg_printk(kern, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) printk(kern "%s: " fmt, __func__, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define lg_info(fmt, arg...) printk(KERN_INFO "lg2160: " fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) lg_printk(KERN_DEBUG, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define lg_reg(fmt, arg...) if (debug & DBG_REG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) lg_printk(KERN_DEBUG, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define lg_fail(ret) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int __ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) __ret = (ret < 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (__ret) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) lg_err("error %d on line %d\n", ret, __LINE__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct lg216x_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct i2c_adapter *i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const struct lg2160_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 current_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 parade_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 fic_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int last_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int lg216x_write_reg(struct lg216x_state *state, u16 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 buf[] = { reg >> 8, reg & 0xff, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .addr = state->cfg->i2c_addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .buf = buf, .len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ret = i2c_transfer(state->i2c_adap, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) msg.buf[0], msg.buf[1], msg.buf[2], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int lg216x_read_reg(struct lg216x_state *state, u16 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 reg_buf[] = { reg >> 8, reg & 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { .addr = state->cfg->i2c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .flags = 0, .buf = reg_buf, .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { .addr = state->cfg->i2c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .flags = I2C_M_RD, .buf = val, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) lg_reg("reg: 0x%04x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = i2c_transfer(state->i2c_adap, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) lg_err("error (addr %02x reg %04x error (ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) state->cfg->i2c_addr, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct lg216x_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int lg216x_write_regs(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct lg216x_reg *regs, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) lg_reg("writing %d registers...\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = lg216x_write_reg(state, regs[i].reg, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int lg216x_set_reg_bit(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u16 reg, int bit, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = lg216x_read_reg(state, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) val &= ~(1 << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) val |= (onoff & 1) << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = lg216x_write_reg(state, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int lg216x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct lg216x_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (state->cfg->deny_i2c_rptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) lg_dbg("(%d)\n", enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = lg216x_set_reg_bit(state, 0x0000, 0, enable ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int lg216x_soft_reset(struct lg216x_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) lg_dbg("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = lg216x_write_reg(state, 0x0002, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ret = lg216x_write_reg(state, 0x0002, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) state->last_reset = jiffies_to_msecs(jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int lg216x_initialize(struct lg216x_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct lg216x_reg lg2160_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { .reg = 0x0015, .val = 0xe6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .reg = 0x0015, .val = 0xf7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .reg = 0x001b, .val = 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { .reg = 0x0208, .val = 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { .reg = 0x0209, .val = 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { .reg = 0x0210, .val = 0xf9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .reg = 0x020a, .val = 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { .reg = 0x020b, .val = 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { .reg = 0x020d, .val = 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { .reg = 0x020f, .val = 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct lg216x_reg lg2161_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { .reg = 0x0000, .val = 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { .reg = 0x0001, .val = 0xfb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { .reg = 0x0216, .val = 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { .reg = 0x0219, .val = 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .reg = 0x021b, .val = 0x55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { .reg = 0x0606, .val = 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = lg216x_write_regs(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) lg2160_init, ARRAY_SIZE(lg2160_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = lg216x_write_regs(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) lg2161_init, ARRAY_SIZE(lg2161_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = lg216x_soft_reset(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int lg216x_set_if(struct lg216x_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) lg_dbg("%d KHz\n", state->cfg->if_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = lg216x_read_reg(state, 0x0132, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) val &= 0xfb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) val |= (0 == state->cfg->if_khz) ? 0x04 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = lg216x_write_reg(state, 0x0132, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* if NOT zero IF, 6 MHz is the default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int lg2160_agc_fix(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int if_agc_fix, int rf_agc_fix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = lg216x_read_reg(state, 0x0100, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) val &= 0xf3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) val |= (if_agc_fix) ? 0x08 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) val |= (rf_agc_fix) ? 0x04 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = lg216x_write_reg(state, 0x0100, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int lg2160_agc_freeze(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int if_agc_freeze, int rf_agc_freeze)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = lg216x_read_reg(state, 0x0100, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) val &= 0xcf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) val |= (if_agc_freeze) ? 0x20 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) val |= (rf_agc_freeze) ? 0x10 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ret = lg216x_write_reg(state, 0x0100, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int lg2160_agc_polarity(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int if_agc_polarity, int rf_agc_polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = lg216x_read_reg(state, 0x0100, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) val &= 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) val |= (if_agc_polarity) ? 0x02 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) val |= (rf_agc_polarity) ? 0x01 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = lg216x_write_reg(state, 0x0100, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int lg2160_tuner_pwr_save_polarity(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = lg216x_read_reg(state, 0x0008, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) val &= 0xfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) val |= (polarity) ? 0x01 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = lg216x_write_reg(state, 0x0008, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int lg2160_spectrum_polarity(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int inverted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = lg216x_read_reg(state, 0x0132, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) val &= 0xfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) val |= (inverted) ? 0x02 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ret = lg216x_write_reg(state, 0x0132, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return lg216x_soft_reset(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int lg2160_tuner_pwr_save(struct lg216x_state *state, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = lg216x_read_reg(state, 0x0007, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) val &= 0xbf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) val |= (onoff) ? 0x40 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret = lg216x_write_reg(state, 0x0007, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int lg216x_set_parade(struct lg216x_state *state, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = lg216x_write_reg(state, 0x013e, id & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) state->parade_id = id & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int lg216x_set_ensemble(struct lg216x_state *state, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) reg = 0x0400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) reg = 0x0500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = lg216x_read_reg(state, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) val &= 0xfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) val |= (id) ? 0x01 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = lg216x_write_reg(state, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int lg2160_set_spi_clock(struct lg216x_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = lg216x_read_reg(state, 0x0014, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) val &= 0xf3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) val |= (state->cfg->spi_clock << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = lg216x_write_reg(state, 0x0014, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int lg2161_set_output_interface(struct lg216x_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = lg216x_read_reg(state, 0x0014, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) val &= ~0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) val |= state->cfg->output_if; /* FIXME: needs sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = lg216x_write_reg(state, 0x0014, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int lg216x_enable_fic(struct lg216x_state *state, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = lg216x_write_reg(state, 0x0017, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = lg216x_write_reg(state, 0x0016, 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = lg216x_write_reg(state, 0x0016,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 0xfc | ((onoff) ? 0x02 : 0x00));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = lg216x_write_reg(state, 0x0016, (onoff) ? 0x10 : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = lg216x_initialize(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (onoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = lg216x_write_reg(state, 0x0017, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int lg216x_get_fic_version(struct lg216x_state *state, u8 *ficver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) *ficver = 0xff; /* invalid value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = lg216x_read_reg(state, 0x0128, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) *ficver = (val >> 3) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int lg2160_get_parade_id(struct lg216x_state *state, u8 *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) *id = 0xff; /* invalid value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret = lg216x_read_reg(state, 0x0123, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) *id = val & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int lg216x_get_nog(struct lg216x_state *state, u8 *nog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) *nog = 0xff; /* invalid value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = lg216x_read_reg(state, 0x0124, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) *nog = ((val >> 4) & 0x07) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int lg216x_get_tnog(struct lg216x_state *state, u8 *tnog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) *tnog = 0xff; /* invalid value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ret = lg216x_read_reg(state, 0x0125, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) *tnog = val & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int lg216x_get_sgn(struct lg216x_state *state, u8 *sgn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) *sgn = 0xff; /* invalid value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = lg216x_read_reg(state, 0x0124, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) *sgn = val & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int lg216x_get_prc(struct lg216x_state *state, u8 *prc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) *prc = 0xff; /* invalid value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ret = lg216x_read_reg(state, 0x0125, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) *prc = ((val >> 5) & 0x07) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static int lg216x_get_rs_frame_mode(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) enum atscmh_rs_frame_mode *rs_framemode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = lg216x_read_reg(state, 0x0410, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret = lg216x_read_reg(state, 0x0513, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) switch ((val >> 4) & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) *rs_framemode = ATSCMH_RSFRAME_PRI_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) *rs_framemode = ATSCMH_RSFRAME_PRI_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) *rs_framemode = ATSCMH_RSFRAME_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int lg216x_get_rs_frame_ensemble(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) enum atscmh_rs_frame_ensemble *rs_frame_ens)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ret = lg216x_read_reg(state, 0x0400, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = lg216x_read_reg(state, 0x0500, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) val &= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) *rs_frame_ens = (enum atscmh_rs_frame_ensemble) val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int lg216x_get_rs_code_mode(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) enum atscmh_rs_code_mode *rs_code_pri,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) enum atscmh_rs_code_mode *rs_code_sec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ret = lg216x_read_reg(state, 0x0410, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = lg216x_read_reg(state, 0x0513, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) *rs_code_pri = (enum atscmh_rs_code_mode) ((val >> 2) & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) *rs_code_sec = (enum atscmh_rs_code_mode) (val & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static int lg216x_get_sccc_block_mode(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) enum atscmh_sccc_block_mode *sccc_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret = lg216x_read_reg(state, 0x0315, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = lg216x_read_reg(state, 0x0511, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) switch (val & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) *sccc_block = ATSCMH_SCCC_BLK_SEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) *sccc_block = ATSCMH_SCCC_BLK_COMB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) *sccc_block = ATSCMH_SCCC_BLK_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int lg216x_get_sccc_code_mode(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) enum atscmh_sccc_code_mode *mode_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) enum atscmh_sccc_code_mode *mode_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) enum atscmh_sccc_code_mode *mode_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) enum atscmh_sccc_code_mode *mode_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = lg216x_read_reg(state, 0x0316, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ret = lg216x_read_reg(state, 0x0512, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) switch ((val >> 6) & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) *mode_a = ATSCMH_SCCC_CODE_HLF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) *mode_a = ATSCMH_SCCC_CODE_QTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) *mode_a = ATSCMH_SCCC_CODE_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) switch ((val >> 4) & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) *mode_b = ATSCMH_SCCC_CODE_HLF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) *mode_b = ATSCMH_SCCC_CODE_QTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) *mode_b = ATSCMH_SCCC_CODE_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) switch ((val >> 2) & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) *mode_c = ATSCMH_SCCC_CODE_HLF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) *mode_c = ATSCMH_SCCC_CODE_QTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) *mode_c = ATSCMH_SCCC_CODE_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) switch (val & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) *mode_d = ATSCMH_SCCC_CODE_HLF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) *mode_d = ATSCMH_SCCC_CODE_QTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) *mode_d = ATSCMH_SCCC_CODE_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static int lg216x_read_fic_err_count(struct lg216x_state *state, u8 *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u8 fic_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) *err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ret = lg216x_read_reg(state, 0x0012, &fic_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = lg216x_read_reg(state, 0x001e, &fic_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) *err = fic_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static int lg2160_read_crc_err_count(struct lg216x_state *state, u16 *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u8 crc_err1, crc_err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) *err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = lg216x_read_reg(state, 0x0411, &crc_err1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ret = lg216x_read_reg(state, 0x0412, &crc_err2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) *err = (u16)(((crc_err2 & 0x0f) << 8) | crc_err1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int lg2161_read_crc_err_count(struct lg216x_state *state, u16 *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u8 crc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) *err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = lg216x_read_reg(state, 0x0612, &crc_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) *err = (u16)crc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static int lg216x_read_crc_err_count(struct lg216x_state *state, u16 *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ret = lg2160_read_crc_err_count(state, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ret = lg2161_read_crc_err_count(state, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int lg2160_read_rs_err_count(struct lg216x_state *state, u16 *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u8 rs_err1, rs_err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) *err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret = lg216x_read_reg(state, 0x0413, &rs_err1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ret = lg216x_read_reg(state, 0x0414, &rs_err2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) *err = (u16)(((rs_err2 & 0x0f) << 8) | rs_err1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static int lg2161_read_rs_err_count(struct lg216x_state *state, u16 *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) u8 rs_err1, rs_err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) *err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ret = lg216x_read_reg(state, 0x0613, &rs_err1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ret = lg216x_read_reg(state, 0x0614, &rs_err2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) *err = (u16)((rs_err1 << 8) | rs_err2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int lg216x_read_rs_err_count(struct lg216x_state *state, u16 *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ret = lg2160_read_rs_err_count(state, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret = lg2161_read_rs_err_count(state, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static int lg216x_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct dtv_frontend_properties *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct lg216x_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) lg_dbg("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) c->modulation = VSB_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) c->frequency = state->current_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) c->delivery_system = SYS_ATSCMH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ret = lg216x_get_fic_version(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) &c->atscmh_fic_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (state->fic_ver != c->atscmh_fic_ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) state->fic_ver = c->atscmh_fic_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ret = lg2160_get_parade_id(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) &c->atscmh_parade_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* #else */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) c->atscmh_parade_id = state->parade_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ret = lg216x_get_nog(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) &c->atscmh_nog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ret = lg216x_get_tnog(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) &c->atscmh_tnog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ret = lg216x_get_sgn(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) &c->atscmh_sgn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = lg216x_get_prc(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) &c->atscmh_prc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ret = lg216x_get_rs_frame_mode(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) (enum atscmh_rs_frame_mode *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) &c->atscmh_rs_frame_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ret = lg216x_get_rs_frame_ensemble(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) (enum atscmh_rs_frame_ensemble *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) &c->atscmh_rs_frame_ensemble);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ret = lg216x_get_rs_code_mode(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) (enum atscmh_rs_code_mode *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) &c->atscmh_rs_code_mode_pri,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) (enum atscmh_rs_code_mode *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) &c->atscmh_rs_code_mode_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = lg216x_get_sccc_block_mode(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) (enum atscmh_sccc_block_mode *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) &c->atscmh_sccc_block_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret = lg216x_get_sccc_code_mode(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) (enum atscmh_sccc_code_mode *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) &c->atscmh_sccc_code_mode_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) (enum atscmh_sccc_code_mode *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) &c->atscmh_sccc_code_mode_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) (enum atscmh_sccc_code_mode *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) &c->atscmh_sccc_code_mode_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) (enum atscmh_sccc_code_mode *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) &c->atscmh_sccc_code_mode_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ret = lg216x_read_fic_err_count(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) (u8 *)&c->atscmh_fic_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ret = lg216x_read_crc_err_count(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) &c->atscmh_crc_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ret = lg216x_read_rs_err_count(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) &c->atscmh_rs_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (((c->atscmh_rs_err >= 240) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) (c->atscmh_crc_err >= 240)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ((jiffies_to_msecs(jiffies) - state->last_reset) > 6000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ret = lg216x_soft_reset(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* no fix needed here (as far as we know) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static int lg2160_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct lg216x_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) lg_dbg("(%d)\n", fe->dtv_property_cache.frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ret = fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) state->current_frequency = fe->dtv_property_cache.frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ret = lg2160_agc_fix(state, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ret = lg2160_agc_polarity(state, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ret = lg2160_tuner_pwr_save_polarity(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ret = lg216x_set_if(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ret = lg2160_spectrum_polarity(state, state->cfg->spectral_inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* be tuned before this point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ret = lg216x_soft_reset(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret = lg2160_tuner_pwr_save(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = lg2160_set_spi_clock(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ret = lg2161_set_output_interface(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ret = lg216x_set_parade(state, fe->dtv_property_cache.atscmh_parade_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ret = lg216x_set_ensemble(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) fe->dtv_property_cache.atscmh_rs_frame_ensemble);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ret = lg216x_initialize(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = lg216x_enable_fic(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) lg_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) lg216x_get_frontend(fe, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static int lg2160_read_lock_status(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) int *acq_lock, int *sync_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) *acq_lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) *sync_lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) ret = lg216x_read_reg(state, 0x011b, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) *sync_lock = (val & 0x20) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) *acq_lock = (val & 0x40) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #ifdef USE_LG2161_LOCK_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static int lg2161_read_lock_status(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) int *acq_lock, int *sync_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) *acq_lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) *sync_lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ret = lg216x_read_reg(state, 0x0304, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) *sync_lock = (val & 0x80) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ret = lg216x_read_reg(state, 0x011b, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) *acq_lock = (val & 0x40) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static int lg216x_read_lock_status(struct lg216x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) int *acq_lock, int *sync_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #ifdef USE_LG2161_LOCK_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) switch (state->cfg->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ret = lg2160_read_lock_status(state, acq_lock, sync_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret = lg2161_read_lock_status(state, acq_lock, sync_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return lg2160_read_lock_status(state, acq_lock, sync_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static int lg216x_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct lg216x_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) int ret, acq_lock, sync_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ret = lg216x_read_lock_status(state, &acq_lock, &sync_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) lg_dbg("%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) acq_lock ? "SIGNALEXIST " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) sync_lock ? "SYNCLOCK" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (acq_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (sync_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (*status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) *status |= FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static int lg2160_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) struct lg216x_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) u8 snr1, snr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) *snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ret = lg216x_read_reg(state, 0x0202, &snr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) ret = lg216x_read_reg(state, 0x0203, &snr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if ((snr1 == 0xba) || (snr2 == 0xdf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) *snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) *snr = ((snr1 >> 4) * 100) + ((snr1 & 0x0f) * 10) + (snr2 >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #else /* BCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) *snr = (snr2 | (snr1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) static int lg2161_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) struct lg216x_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) u8 snr1, snr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) *snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ret = lg216x_read_reg(state, 0x0302, &snr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ret = lg216x_read_reg(state, 0x0303, &snr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if ((snr1 == 0xba) || (snr2 == 0xfd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) *snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) *snr = ((snr1 >> 4) * 100) + ((snr1 & 0x0f) * 10) + (snr2 & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static int lg216x_read_signal_strength(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* borrowed from lgdt330x.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * Calculate strength from SNR up to 35dB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * Even though the SNR can go higher than 35dB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * there is some comfort factor in having a range of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * strong signals that can show at 100%
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct lg216x_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) u16 snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) *strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ret = fe->ops.read_snr(fe, &snr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* scale the range 0 - 35*2^24 into 0 - 65535 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (state->snr >= 8960 * 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) *strength = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) *strength = state->snr / 8960;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static int lg216x_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct lg216x_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) ret = lg216x_read_rs_err_count(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) &fe->dtv_property_cache.atscmh_rs_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (lg_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) *ucblocks = fe->dtv_property_cache.atscmh_rs_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) *ucblocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static int lg216x_get_tune_settings(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct dvb_frontend_tune_settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) *fe_tune_settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) fe_tune_settings->min_delay_ms = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) lg_dbg("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static void lg216x_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) struct lg216x_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) lg_dbg("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static const struct dvb_frontend_ops lg2160_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .delsys = { SYS_ATSCMH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .name = "LG Electronics LG2160 ATSC/MH Frontend",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .frequency_min_hz = 54 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .frequency_max_hz = 858 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .frequency_stepsize_hz = 62500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .i2c_gate_ctrl = lg216x_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .init = lg216x_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .sleep = lg216x_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .set_frontend = lg2160_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .get_frontend = lg216x_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .get_tune_settings = lg216x_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .read_status = lg216x_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .read_ber = lg216x_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .read_signal_strength = lg216x_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .read_snr = lg2160_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .read_ucblocks = lg216x_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .release = lg216x_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static const struct dvb_frontend_ops lg2161_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .delsys = { SYS_ATSCMH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .name = "LG Electronics LG2161 ATSC/MH Frontend",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .frequency_min_hz = 54 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .frequency_max_hz = 858 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .frequency_stepsize_hz = 62500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .i2c_gate_ctrl = lg216x_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .init = lg216x_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .sleep = lg216x_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .set_frontend = lg2160_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .get_frontend = lg216x_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .get_tune_settings = lg216x_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .read_status = lg216x_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .read_ber = lg216x_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .read_signal_strength = lg216x_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .read_snr = lg2161_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .read_ucblocks = lg216x_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .release = lg216x_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) struct dvb_frontend *lg2160_attach(const struct lg2160_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct lg216x_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) lg_dbg("(%d-%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) config ? config->i2c_addr : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) state = kzalloc(sizeof(struct lg216x_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) state->cfg = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) state->i2c_adap = i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) state->fic_ver = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) state->parade_id = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) switch (config->lg_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) lg_warn("invalid chip requested, defaulting to LG2160");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) case LG2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) memcpy(&state->frontend.ops, &lg2160_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) case LG2161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) memcpy(&state->frontend.ops, &lg2161_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) state->current_frequency = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) /* parade 1 by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) state->frontend.dtv_property_cache.atscmh_parade_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) EXPORT_SYMBOL(lg2160_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) MODULE_DESCRIPTION("LG Electronics LG216x ATSC/MH Demodulator Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) MODULE_VERSION("0.3");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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