Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Driver for the Integrant ITD1000 "Zero-IF Tuner IC for Direct Broadcast Satellite"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (c) 2007-8 Patrick Boettcher <pb@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "itd1000.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "itd1000_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* Max transfer size done by I2C transfer functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MAX_XFER_SIZE  64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define itd_dbg(args...)  do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	if (debug) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		printk(KERN_DEBUG   "ITD1000: " args);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define itd_warn(args...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	printk(KERN_WARNING "ITD1000: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define itd_info(args...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	printk(KERN_INFO    "ITD1000: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* don't write more than one byte with flexcop behind */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u8 buf[MAX_XFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	if (1 + len > sizeof(buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		       "itd1000: i2c wr reg=%04x: len=%d is too big!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		       reg, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	buf[0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	memcpy(&buf[1], v, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/* itd_dbg("wr %02x: %02x\n", reg, v[0]); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (i2c_transfer(state->i2c, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		printk(KERN_WARNING "itd1000 I2C write failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static int itd1000_read_reg(struct itd1000_state *state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		{ .addr = state->cfg->i2c_address, .flags = 0,        .buf = &reg, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		{ .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/* ugly flexcop workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (i2c_transfer(state->i2c, msg, 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		itd_warn("itd1000 I2C read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u8 tmp = v; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	int ret = itd1000_write_regs(state, r, &tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	state->shadow[r] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u8  pgaext  : 4; /* PLLFH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u8  bbgvmin : 4; /* BBGVMIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) } itd1000_lpf_pga[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{        0, 0x8, 0x3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{  5200000, 0x8, 0x3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	{ 12200000, 0x4, 0x3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	{ 15400000, 0x2, 0x3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{ 19800000, 0x2, 0x3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{ 21500000, 0x2, 0x3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{ 24500000, 0x2, 0x3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{ 28400000, 0x2, 0x3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{ 33400000, 0x2, 0x3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{ 34400000, 0x1, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	{ 34400000, 0x1, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	{ 38400000, 0x1, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	{ 38400000, 0x1, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{ 40400000, 0x1, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{ 45400000, 0x1, 0x4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void itd1000_set_lpf_bw(struct itd1000_state *state, u32 symbol_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u8 con1    = itd1000_read_reg(state, CON1)    & 0xfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u8 pllfh   = itd1000_read_reg(state, PLLFH)   & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u8 bw      = itd1000_read_reg(state, BW)      & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	itd_dbg("symbol_rate = %d\n", symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/* not sure what is that ? - starting to download the table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	itd1000_write_reg(state, CON1, con1 | (1 << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	for (i = 0; i < ARRAY_SIZE(itd1000_lpf_pga); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		if (symbol_rate < itd1000_lpf_pga[i].symbol_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			itd_dbg("symrate: index: %d pgaext: %x, bbgvmin: %x\n", i, itd1000_lpf_pga[i].pgaext, itd1000_lpf_pga[i].bbgvmin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			itd1000_write_reg(state, PLLFH,   pllfh | (itd1000_lpf_pga[i].pgaext << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			itd1000_write_reg(state, BBGVMIN, bbgvmin | (itd1000_lpf_pga[i].bbgvmin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			itd1000_write_reg(state, BW,      bw | (i & 0x0f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	itd1000_write_reg(state, CON1, con1 | (0 << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u8 vcorg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u32 fmax_rg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } itd1000_vcorg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	{  1,  920000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{  2,  971000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	{  3, 1031000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	{  4, 1091000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	{  5, 1171000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{  6, 1281000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{  7, 1381000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{  8,  500000 },	/* this is intentional. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{  9, 1451000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	{ 10, 1531000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	{ 11, 1631000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	{ 12, 1741000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{ 13, 1891000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	{ 14, 2071000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	{ 15, 2250000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u8 gvbb_i2c     = itd1000_read_reg(state, GVBB_I2C) & 0xbf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u8 adcout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* reserved bit again (reset ?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	itd1000_write_reg(state, GVBB_I2C, gvbb_i2c | (1 << 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	for (i = 0; i < ARRAY_SIZE(itd1000_vcorg); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (freq_khz < itd1000_vcorg[i].fmax_rg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | (itd1000_vcorg[i].vcorg << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			itd_dbg("VCO: %dkHz: %d -> ADCOUT: %d %02x\n", freq_khz, itd1000_vcorg[i].vcorg, adcout, vco_chp1_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			if (adcout > 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 				if (!(itd1000_vcorg[i].vcorg == 7 || itd1000_vcorg[i].vcorg == 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 					itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg + 1) << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			} else if (adcout < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				if (!(itd1000_vcorg[i].vcorg == 1 || itd1000_vcorg[i].vcorg == 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 					itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg - 1) << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u8 values[10]; /* RFTR, RFST1 - RFST9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) } itd1000_fre_values[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	{ 1075000, { 0x59, 0x1d, 0x1c, 0x17, 0x16, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	{ 1250000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	{ 1450000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	{ 1650000, { 0x69, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	{ 1750000, { 0x69, 0x1e, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	{ 1850000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	{ 1900000, { 0x69, 0x1d, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	{ 1950000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0d, 0x0b, 0x0a } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	{ 2050000, { 0x69, 0x1e, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0b, 0x0a } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	{ 2150000, { 0x69, 0x1d, 0x1c, 0x17, 0x15, 0x14, 0x13, 0x0f, 0x0e, 0x0b } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define FREF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	u32 plln, pllf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	plln = (freq_khz * 1000) / 2 / FREF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* Compute the factional part times 1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	tmp  = plln % 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	plln /= 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	tmp *= 1048576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	do_div(tmp, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	pllf = (u32) tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	itd1000_write_reg(state, PLLNL, plln & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	for (i = 0; i < ARRAY_SIZE(itd1000_fre_values); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		if (freq_khz <= itd1000_fre_values[i].freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			itd_dbg("fre_values: %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			for (j = 0; j < 9; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				itd1000_write_reg(state, RFST1+j, itd1000_fre_values[i].values[j+1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	itd1000_set_vco(state, freq_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int itd1000_set_parameters(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct itd1000_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	u8 pllcon1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	itd1000_set_lo(state, c->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	itd1000_set_lpf_bw(state, c->symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	itd1000_write_reg(state, PLLCON1, pllcon1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int itd1000_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct itd1000_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	*frequency = state->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int itd1000_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static u8 itd1000_init_tab[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	{ PLLCON1,       0x65 }, /* Register does not change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	{ PLLNH,         0x80 }, /* Bits [7:6] do not change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	{ RESERVED_0X6D, 0x3b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	{ VCO_CHP2_I2C,  0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	{ 0x72,          0xf9 }, /* No such regsister defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	{ RESERVED_0X73, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	{ RESERVED_0X74, 0xb2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	{ RESERVED_0X75, 0xc7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	{ EXTGVBBRF,     0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	{ DIVAGCCK,      0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	{ BBTR,          0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	{ RESERVED_0X7E, 0x4f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	{ 0x82,          0x88 }, /* No such regsister defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	{ 0x83,          0x80 }, /* No such regsister defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	{ 0x84,          0x80 }, /* No such regsister defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	{ RESERVED_0X85, 0x74 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	{ RESERVED_0X86, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	{ RESERVED_0X88, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	{ RESERVED_0X89, 0x16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	{ RFST0,         0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	{ RESERVED_0X94, 0x66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	{ RESERVED_0X95, 0x66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	{ RESERVED_0X96, 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	{ RESERVED_0X97, 0x99 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	{ RESERVED_0X98, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	{ RESERVED_0X99, 0xfc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	{ RESERVED_0X9A, 0xba },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	{ RESERVED_0X9B, 0xaa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static u8 itd1000_reinit_tab[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	{ VCO_CHP1_I2C, 0x8a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	{ BW,           0x87 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	{ GVBB_I2C,     0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	{ BBGVMIN,      0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	{ CON1,         0x2e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int itd1000_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	struct itd1000_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	for (i = 0; i < ARRAY_SIZE(itd1000_init_tab); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	for (i = 0; i < ARRAY_SIZE(itd1000_reinit_tab); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int itd1000_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void itd1000_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	kfree(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const struct dvb_tuner_ops itd1000_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.name              = "Integrant ITD1000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.frequency_min_hz  =  950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		.frequency_max_hz  = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.frequency_step_hz =  125 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	.release       = itd1000_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	.init          = itd1000_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	.sleep         = itd1000_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	.set_params    = itd1000_set_parameters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	.get_frequency = itd1000_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	.get_bandwidth = itd1000_get_bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	struct itd1000_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	u8 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	state = kzalloc(sizeof(struct itd1000_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	state->cfg = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	i = itd1000_read_reg(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (i != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	itd_info("successfully identified (ID: %d)\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	memset(state->shadow, 0xff, sizeof(state->shadow));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	for (i = 0x65; i < 0x9c; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		state->shadow[i] = itd1000_read_reg(state, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	memcpy(&fe->ops.tuner_ops, &itd1000_tuner_ops, sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	fe->tuner_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) EXPORT_SYMBOL(itd1000_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MODULE_AUTHOR("Patrick Boettcher <pb@linuxtv.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MODULE_DESCRIPTION("Integrant ITD1000 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MODULE_LICENSE("GPL");