Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * horus3a.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Sony Horus3A DVB-S/S2 tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright 2012 Sony Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2014 NetUP Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "horus3a.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MAX_WRITE_REGSIZE      5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) enum horus3a_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	STATE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	STATE_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	STATE_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) struct horus3a_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32			frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u8			i2c_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct i2c_adapter	*i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	enum horus3a_state	state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	void			*set_tuner_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	int			(*set_tuner)(void *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static void horus3a_i2c_debug(struct horus3a_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			      u8 reg, u8 write, const u8 *data, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	dev_dbg(&priv->i2c->dev, "horus3a: I2C %s reg 0x%02x size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		(write == 0 ? "read" : "write"), reg, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	print_hex_dump_bytes("horus3a: I2C data: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		DUMP_PREFIX_OFFSET, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static int horus3a_write_regs(struct horus3a_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			      u8 reg, const u8 *data, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u8 buf[MAX_WRITE_REGSIZE + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct i2c_msg msg[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			.addr = priv->i2c_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			.flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			.len = len + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			.buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (len + 1 > sizeof(buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			 reg, len + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	horus3a_i2c_debug(priv, reg, 1, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	buf[0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	memcpy(&buf[1], data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ret = i2c_transfer(priv->i2c, msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (ret >= 0 && ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		dev_warn(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			"%s: i2c wr failed=%d reg=%02x len=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			KBUILD_MODNAME, ret, reg, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static int horus3a_write_reg(struct horus3a_priv *priv, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return horus3a_write_regs(priv, reg, &tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static int horus3a_enter_power_save(struct horus3a_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (priv->state == STATE_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/* IQ Generator disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	horus3a_write_reg(priv, 0x2a, 0x79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* MDIV_EN = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	horus3a_write_reg(priv, 0x29, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* VCO disable preparation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	horus3a_write_reg(priv, 0x28, 0x3e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/* VCO buffer disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	horus3a_write_reg(priv, 0x2a, 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* VCO calibration disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	horus3a_write_reg(priv, 0x1c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/* Power save setting (xtal is not stopped) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	data[0] = 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* LNA is Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	data[1] = 0xA7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* 0x11 - 0x12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	horus3a_write_regs(priv, 0x11, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	priv->state = STATE_SLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int horus3a_leave_power_save(struct horus3a_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (priv->state == STATE_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	/* Leave power save */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	data[0] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* LNA is Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	data[1] = 0xa7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* 0x11 - 0x12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	horus3a_write_regs(priv, 0x11, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* VCO buffer enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	horus3a_write_reg(priv, 0x2a, 0x79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* VCO calibration enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	horus3a_write_reg(priv, 0x1c, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/* MDIV_EN = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	horus3a_write_reg(priv, 0x29, 0x71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	usleep_range(5000, 7000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	priv->state = STATE_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int horus3a_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct horus3a_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void horus3a_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct horus3a_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	kfree(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int horus3a_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct horus3a_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	horus3a_enter_power_save(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int horus3a_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct horus3a_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	u32 frequency = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u32 symbol_rate = p->symbol_rate/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u8 mixdiv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u8 mdiv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u32 ms = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u8 f_ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	u8 g_ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	u8 fc_lpf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	u8 data[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	dev_dbg(&priv->i2c->dev, "%s(): frequency %dkHz symbol_rate %dksps\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		__func__, frequency, symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (priv->set_tuner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		priv->set_tuner(priv->set_tuner_data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (priv->state == STATE_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		horus3a_leave_power_save(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* frequency should be X MHz (X : integer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	frequency = DIV_ROUND_CLOSEST(frequency, 1000) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (frequency <= 1155000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		mixdiv = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		mdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		mixdiv = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		mdiv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* Assumed that fREF == 1MHz (1000kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	ms = DIV_ROUND_CLOSEST((frequency * mixdiv) / 2, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (ms > 0x7FFF) { /* 15 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		dev_err(&priv->i2c->dev, "horus3a: invalid frequency %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (frequency < 975000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		/* F_CTL=11100 G_CTL=001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		f_ctl = 0x1C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		g_ctl = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	} else if (frequency < 1050000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		/* F_CTL=11000 G_CTL=010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		f_ctl = 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		g_ctl = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	} else if (frequency < 1150000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		/* F_CTL=10100 G_CTL=010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		f_ctl = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		g_ctl = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	} else if (frequency < 1250000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		/* F_CTL=10000 G_CTL=011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		f_ctl = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		g_ctl = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	} else if (frequency < 1350000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		/* F_CTL=01100 G_CTL=100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		f_ctl = 0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		g_ctl = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	} else if (frequency < 1450000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		/* F_CTL=01010 G_CTL=100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		f_ctl = 0x0A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		g_ctl = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	} else if (frequency < 1600000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		/* F_CTL=00111 G_CTL=101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		f_ctl = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		g_ctl = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	} else if (frequency < 1800000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		/* F_CTL=00100 G_CTL=010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		f_ctl = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		g_ctl = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	} else if (frequency < 2000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		/* F_CTL=00010 G_CTL=001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		f_ctl = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		g_ctl = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		/* F_CTL=00000 G_CTL=000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		f_ctl = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		g_ctl = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/* LPF cutoff frequency setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (p->delivery_system == SYS_DVBS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		 * rolloff = 0.35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		 * SR <= 4.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		 * fc_lpf = 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		 * 4.3 < SR <= 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		 * fc_lpf = SR * (1 + rolloff) / 2 + SR / 2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		 *	SR * 1.175 = SR * (47/40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		 * 10 < SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		 * fc_lpf = SR * (1 + rolloff) / 2 + 5 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		 *	SR * 0.675 + 5 = SR * (27/40) + 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		 * NOTE: The result should be round up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		if (symbol_rate <= 4300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			fc_lpf = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		else if (symbol_rate <= 10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 47, 40000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 27, 40000) + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		/* 5 <= fc_lpf <= 36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		if (fc_lpf > 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			fc_lpf = 36;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	} else if (p->delivery_system == SYS_DVBS2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		 * SR <= 4.5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		 * fc_lpf = 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		 * 4.5 < SR <= 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		 * fc_lpf = SR * (1 + rolloff) / 2 + SR / 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		 * 10 < SR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		 * fc_lpf = SR * (1 + rolloff) / 2 + 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		 * NOTE: The result should be round up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		if (symbol_rate <= 4500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			fc_lpf = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		else if (symbol_rate <= 10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			fc_lpf = (u8)((symbol_rate * 11 + (10000-1)) / 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			fc_lpf = (u8)((symbol_rate * 3 + (5000-1)) / 5000 + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		/* 5 <= fc_lpf <= 36 is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		if (fc_lpf > 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			fc_lpf = 36;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		dev_err(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			"horus3a: invalid delivery system %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			p->delivery_system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	/* 0x00 - 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	data[0] = (u8)((ms >> 7) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	data[1] = (u8)((ms << 1) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	data[2] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	data[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	data[4] = (u8)(mdiv << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	horus3a_write_regs(priv, 0x00, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	/* Write G_CTL, F_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	horus3a_write_reg(priv, 0x09, (u8)((g_ctl << 5) | f_ctl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	/* Write LPF cutoff frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	horus3a_write_reg(priv, 0x37, (u8)(0x80 | (fc_lpf << 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* Start Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	horus3a_write_reg(priv, 0x05, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	/* IQ Generator enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	horus3a_write_reg(priv, 0x2a, 0x7b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	/* tuner stabilization time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	msleep(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	/* Store tuned frequency to the struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	priv->frequency = ms * 2 * 1000 / mixdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int horus3a_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct horus3a_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	*frequency = priv->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct dvb_tuner_ops horus3a_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.name = "Sony Horus3a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.frequency_min_hz  =  950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.frequency_max_hz  = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		.frequency_step_hz =    1 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.init = horus3a_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.release = horus3a_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.sleep = horus3a_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.set_params = horus3a_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.get_frequency = horus3a_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct dvb_frontend *horus3a_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 				    const struct horus3a_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 				    struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	u8 buf[3], val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	struct horus3a_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	priv = kzalloc(sizeof(struct horus3a_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	priv->i2c_address = (config->i2c_address >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	priv->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	priv->set_tuner_data = config->set_tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	priv->set_tuner = config->set_tuner_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	/* wait 4ms after power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	usleep_range(4000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	/* IQ Generator disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	horus3a_write_reg(priv, 0x2a, 0x79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	/* REF_R = Xtal Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	buf[0] = config->xtal_freq_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	buf[1] = config->xtal_freq_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	buf[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	/* 0x6 - 0x8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	horus3a_write_regs(priv, 0x6, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	/* IQ Out = Single Ended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	horus3a_write_reg(priv, 0x0a, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	switch (config->xtal_freq_mhz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	case 27:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		val = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		val = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		val = 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		dev_warn(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			"horus3a: invalid xtal frequency %dMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			config->xtal_freq_mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	val <<= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	horus3a_write_reg(priv, 0x0e, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	horus3a_enter_power_save(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	memcpy(&fe->ops.tuner_ops, &horus3a_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 				sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	dev_info(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		"Sony HORUS3A attached on addr=%x at I2C adapter %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		priv->i2c_address, priv->i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) EXPORT_SYMBOL(horus3a_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MODULE_DESCRIPTION("Sony HORUS3A satellite tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MODULE_LICENSE("GPL");