Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * gp8psk_fe driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef GP8PSK_FE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define GP8PSK_FE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* gp8psk commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define GET_8PSK_CONFIG                 0x80    /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SET_8PSK_CONFIG                 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define I2C_WRITE			0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define I2C_READ			0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ARM_TRANSFER                    0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TUNE_8PSK                       0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GET_SIGNAL_STRENGTH             0x87    /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LOAD_BCM4500                    0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BOOT_8PSK                       0x89    /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define START_INTERSIL                  0x8A    /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SET_LNB_VOLTAGE                 0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SET_22KHZ_TONE                  0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SEND_DISEQC_COMMAND             0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SET_DVB_MODE                    0x8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SET_DN_SWITCH                   0x8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GET_SIGNAL_LOCK                 0x90    /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GET_FW_VERS			0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GET_SERIAL_NUMBER               0x93    /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define USE_EXTRA_VOLT                  0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GET_FPGA_VERS			0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CW3K_INIT			0x9d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* PSK_configuration bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define bm8pskStarted                   0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define bm8pskFW_Loaded                 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define bmIntersilOn                    0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define bmDVBmode                       0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define bm22kHz                         0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define bmSEL18V                        0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define bmDCtuned                       0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define bmArmed                         0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Satellite modulation modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADV_MOD_DVB_QPSK 0     /* DVB-S QPSK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ADV_MOD_TURBO_QPSK 1   /* Turbo QPSK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADV_MOD_TURBO_8PSK 2   /* Turbo 8PSK (also used for Trellis 8PSK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ADV_MOD_TURBO_16QAM 3  /* Turbo 16QAM (also used for Trellis 8PSK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADV_MOD_DCII_C_QPSK 4  /* Digicipher II Combo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADV_MOD_DCII_I_QPSK 5  /* Digicipher II I-stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADV_MOD_DCII_Q_QPSK 6  /* Digicipher II Q-stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADV_MOD_DCII_C_OQPSK 7 /* Digicipher II offset QPSK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADV_MOD_DSS_QPSK 8     /* DSS (DIRECTV) QPSK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADV_MOD_DVB_BPSK 9     /* DVB-S BPSK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* firmware revision id's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GP8PSK_FW_REV1			0x020604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GP8PSK_FW_REV2			0x020704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GP8PSK_FW_VERS(_fw_vers) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	((_fw_vers)[2]<<0x10 | (_fw_vers)[1]<<0x08 | (_fw_vers)[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct gp8psk_fe_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	int (*in)(void *priv, u8 req, u16 value, u16 index, u8 *b, int blen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	int (*out)(void *priv, u8 req, u16 value, u16 index, u8 *b, int blen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	int (*reload)(void *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct dvb_frontend *gp8psk_fe_attach(const struct gp8psk_fe_ops *ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 				      void *priv, bool is_rev1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif