^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Montage Technology DS3000 - DVBS/S2 Demodulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 2009-2012 TurboSight.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ts2020.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ds3000.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) printk(args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* as of March 2009 current DS3000 firmware version is 1.78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DS3000_SAMPLE_RATE 96000 /* in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Register values to initialise the demod in DVB-S mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static u8 ds3000_dvbs_init_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 0x23, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 0x08, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 0x0c, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 0x21, 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 0x25, 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 0x27, 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 0x30, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 0x31, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 0x32, 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 0x33, 0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 0x35, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 0x3a, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0x37, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 0x38, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0x39, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 0x42, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 0x4a, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 0x4b, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 0x4d, 0x91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 0x5d, 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 0x50, 0x77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 0x51, 0x77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 0x52, 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 0x53, 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0x56, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0x63, 0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0x64, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0x65, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0x68, 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0x69, 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0x70, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0x71, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0x72, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0x73, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0x70, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0x71, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0x72, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0x73, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 0x70, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0x71, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0x72, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0x73, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0x70, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 0x71, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0x72, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 0x73, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 0x70, 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0x71, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 0x72, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 0x73, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 0x70, 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 0x76, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 0x77, 0xd1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0x78, 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 0x79, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0x7f, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0x7c, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0x80, 0x86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0x81, 0xa6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0x85, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0xcd, 0xf4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 0x90, 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0xa0, 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0xc0, 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0xc3, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0xc4, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0xc5, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0xc6, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0xc7, 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0xc8, 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0xc9, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0xfe, 0x92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0xe0, 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0xe6, 0x8b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0xd0, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0xf8, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 0xfa, 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0xfd, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0xad, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 0xae, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 0xb8, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Register values to initialise the demod in DVB-S2 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static u8 ds3000_dvbs2_init_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0x23, 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x08, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x0c, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0x21, 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0x25, 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0x27, 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0x30, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0x31, 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0x32, 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 0x33, 0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 0x35, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0x3a, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 0x37, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 0x38, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0x39, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 0x42, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 0x4a, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0x4b, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 0x4d, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 0x5d, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0x50, 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0x51, 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0x52, 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0x53, 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x63, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 0x64, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 0x65, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0x68, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 0x69, 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 0x70, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 0x71, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 0x72, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 0x73, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 0x70, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 0x71, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 0x72, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 0x73, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0x70, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 0x71, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 0x72, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 0x73, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 0x70, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 0x71, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 0x72, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 0x73, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 0x70, 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 0x71, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 0x72, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 0x73, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0x70, 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 0xa0, 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 0xc0, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 0xc1, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 0xc2, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 0xc3, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 0xc4, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 0xc5, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0xc6, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0xc7, 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 0xc8, 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 0xc9, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 0xca, 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 0xcb, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 0xce, 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 0x90, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 0x76, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 0x77, 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 0x78, 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 0x79, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 0xad, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 0xae, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 0x7f, 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0x7c, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 0x80, 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0x81, 0xda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 0x7c, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0x80, 0xda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 0x81, 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 0x7c, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 0x80, 0xca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 0x81, 0xeb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 0x7c, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 0x80, 0xba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 0x81, 0xdb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 0x85, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0x86, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 0x87, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 0x89, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 0x8b, 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 0x8c, 0xaa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 0x8a, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 0xba, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 0xf5, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 0xfe, 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 0xd2, 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 0xb8, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct ds3000_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const struct ds3000_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* previous uncorrected block counter for DVB-S2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u16 prevUCBS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 buf[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct i2c_msg msg = { .addr = state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .flags = 0, .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) err = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (err != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __func__, err, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int ds3000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ds3000_writereg(state, 0x03, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ds3000_writereg(state, 0x03, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* I2C write for 8k firmware load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int ds3000_writeFW(struct ds3000_state *state, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) const u8 *data, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) buf = kmalloc(33, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *(buf) = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) msg.addr = state->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) msg.len = 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) for (i = 0; i < len; i += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) memcpy(buf + 1, data + i, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) printk(KERN_ERR "%s: write error(err == %i, reg == 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) __func__, ret, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int ds3000_readreg(struct ds3000_state *state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 b0[] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 b1[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .addr = state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .buf = b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .len = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .addr = state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .buf = b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .len = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int ds3000_load_firmware(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) const struct firmware *fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = ds3000_readreg(state, 0xb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Load firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* request the firmware, this will block until someone uploads it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DS3000_DEFAULT_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) state->i2c->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) printk(KERN_ERR "%s: No firmware uploaded (timeout or file not found?)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = ds3000_load_firmware(fe, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) printk("%s: Writing firmware to device failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dprintk("%s: Firmware upload %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret == 0 ? "complete" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int ds3000_load_firmware(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) fw->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) fw->data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) fw->data[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) fw->data[fw->size - 2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) fw->data[fw->size - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Begin the firmware load process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ds3000_writereg(state, 0xb2, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* write the entire firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = ds3000_writeFW(state, 0xb0, fw->data, fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ds3000_writereg(state, 0xb2, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int ds3000_set_voltage(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) enum fe_sec_voltage voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dprintk("%s(%d)\n", __func__, voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) data = ds3000_readreg(state, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) data |= 0x03; /* bit0 V/H, bit1 off/on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) switch (voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case SEC_VOLTAGE_18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) data &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case SEC_VOLTAGE_13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) data &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) data |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case SEC_VOLTAGE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ds3000_writereg(state, 0xa2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int ds3000_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) switch (c->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case SYS_DVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) lock = ds3000_readreg(state, 0xd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if ((lock & 0x07) == 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) FE_HAS_VITERBI | FE_HAS_SYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case SYS_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) lock = ds3000_readreg(state, 0x0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if ((lock & 0x8f) == 0x8f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) FE_HAS_VITERBI | FE_HAS_SYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (state->config->set_lock_led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) state->config->set_lock_led(fe, *status == 0 ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dprintk("%s: status = 0x%02x\n", __func__, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* read DS3000 BER value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 ber_reading, lpdc_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) switch (c->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case SYS_DVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* set the number of bytes checked during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) BER estimation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ds3000_writereg(state, 0xf9, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* read BER estimation status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) data = ds3000_readreg(state, 0xf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* check if BER estimation is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if ((data & 0x10) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* this is the number of error bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) to calculate the bit error rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) divide to 8388608 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) *ber = (ds3000_readreg(state, 0xf7) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ds3000_readreg(state, 0xf6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* start counting error bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* need to be set twice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) otherwise it fails sometimes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) data |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ds3000_writereg(state, 0xf8, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ds3000_writereg(state, 0xf8, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* used to indicate that BER estimation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) is not ready, i.e. BER is unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) *ber = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case SYS_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* read the number of LPDC decoded frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) (ds3000_readreg(state, 0xd6) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ds3000_readreg(state, 0xd5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* read the number of packets with bad CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ds3000_readreg(state, 0xf7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (lpdc_frames > 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* clear LPDC frame counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ds3000_writereg(state, 0xd1, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* clear bad packets counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ds3000_writereg(state, 0xf9, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* enable bad packets counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ds3000_writereg(state, 0xf9, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* enable LPDC frame counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ds3000_writereg(state, 0xd1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) *ber = ber_reading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* used to indicate that BER estimation is not ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) i.e. BER is unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) *ber = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int ds3000_read_signal_strength(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u16 *signal_strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (fe->ops.tuner_ops.get_rf_strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) fe->ops.tuner_ops.get_rf_strength(fe, signal_strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* calculate DS3000 snr value in dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u8 snr_reading, snr_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 0x49e9, 0x4a20, 0x4a57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) switch (c->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case SYS_DVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) snr_reading = ds3000_readreg(state, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) snr_reading /= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (snr_reading == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) *snr = 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (snr_reading > 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) snr_reading = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* cook the value to be suitable for szap-s2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) human readable output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) *snr = snr_value * 8 * 655;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) snr_reading, *snr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case SYS_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) (ds3000_readreg(state, 0x8d) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (tmp == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) *snr = 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (dvbs2_noise_reading == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) snr_value = 0x0013;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* cook the value to be suitable for szap-s2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) human readable output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) *snr = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (tmp > dvbs2_noise_reading) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) snr_reading = tmp / dvbs2_noise_reading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (snr_reading > 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) snr_reading = 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* cook the value to be suitable for szap-s2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) human readable output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) *snr = snr_value * 5 * 655;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) snr_reading = dvbs2_noise_reading / tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (snr_reading > 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) snr_reading = 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) *snr = -(dvbs2_snr_tab[snr_reading - 1] / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) snr_reading, *snr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* read DS3000 uncorrected blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u16 _ucblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) switch (c->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) case SYS_DVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ds3000_readreg(state, 0xf4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) data = ds3000_readreg(state, 0xf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* clear packet counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) data &= ~0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ds3000_writereg(state, 0xf8, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* enable packet counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) data |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ds3000_writereg(state, 0xf8, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) case SYS_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ds3000_readreg(state, 0xe1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (_ucblocks > state->prevUCBS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) *ucblocks = _ucblocks - state->prevUCBS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) *ucblocks = state->prevUCBS2 - _ucblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) state->prevUCBS2 = _ucblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static int ds3000_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dprintk("%s(%d)\n", __func__, tone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) data = ds3000_readreg(state, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) data &= ~0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ds3000_writereg(state, 0xa2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) switch (tone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) case SEC_TONE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dprintk("%s: setting tone on\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) data = ds3000_readreg(state, 0xa1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) data &= ~0x43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) data |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ds3000_writereg(state, 0xa1, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case SEC_TONE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dprintk("%s: setting tone off\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) data = ds3000_readreg(state, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) data |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ds3000_writereg(state, 0xa2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct dvb_diseqc_master_cmd *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Dump DiSEqC message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dprintk("%s(", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) for (i = 0 ; i < d->msg_len;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dprintk("0x%02x", d->msg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (++i < d->msg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dprintk(", ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* enable DiSEqC message send pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) data = ds3000_readreg(state, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) data &= ~0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ds3000_writereg(state, 0xa2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* DiSEqC message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) for (i = 0; i < d->msg_len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ds3000_writereg(state, 0xa3 + i, d->msg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) data = ds3000_readreg(state, 0xa1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* clear DiSEqC message length and status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) enable DiSEqC message send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) data &= ~0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* set DiSEqC mode, modulation active during 33 pulses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) set DiSEqC message length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) data |= ((d->msg_len - 1) << 3) | 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ds3000_writereg(state, 0xa1, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* wait up to 150ms for DiSEqC transmission to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) for (i = 0; i < 15; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) data = ds3000_readreg(state, 0xa1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if ((data & 0x40) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* DiSEqC timeout after 150ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (i == 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) data = ds3000_readreg(state, 0xa1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) data &= ~0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) data |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ds3000_writereg(state, 0xa1, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) data = ds3000_readreg(state, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) data &= ~0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) data |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ds3000_writereg(state, 0xa2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) data = ds3000_readreg(state, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) data &= ~0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) data |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ds3000_writereg(state, 0xa2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Send DiSEqC burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) enum fe_sec_mini_cmd burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) data = ds3000_readreg(state, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) data &= ~0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ds3000_writereg(state, 0xa2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* DiSEqC burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (burst == SEC_MINI_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* Unmodulated tone burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ds3000_writereg(state, 0xa1, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) else if (burst == SEC_MINI_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Modulated tone burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ds3000_writereg(state, 0xa1, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) msleep(13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) data = ds3000_readreg(state, 0xa1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if ((data & 0x40) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (i == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) data = ds3000_readreg(state, 0xa1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) data &= ~0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) data |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ds3000_writereg(state, 0xa1, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) data = ds3000_readreg(state, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) data &= ~0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) data |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ds3000_writereg(state, 0xa2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) data = ds3000_readreg(state, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) data &= ~0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) data |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ds3000_writereg(state, 0xa2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static void ds3000_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (state->config->set_lock_led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) state->config->set_lock_led(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static const struct dvb_frontend_ops ds3000_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct ds3000_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) state->prevUCBS2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* check if the demod is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ret = ds3000_readreg(state, 0x00) & 0xfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (ret != 0xe0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ds3000_readreg(state, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ds3000_readreg(state, 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) memcpy(&state->frontend.ops, &ds3000_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * Some devices like T480 starts with voltage on. Be sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * to turn voltage off during init, as this can otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * interfere with Unicable SCR systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ds3000_set_voltage(&state->frontend, SEC_VOLTAGE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) EXPORT_SYMBOL(ds3000_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) s32 carrier_offset_khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) s32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) tmp = carrier_offset_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) tmp *= 65536;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) tmp += 65536;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ds3000_writereg(state, 0x5f, tmp >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ds3000_writereg(state, 0x5e, tmp & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static int ds3000_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) enum fe_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) s32 offset_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) dprintk("%s() ", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (state->config->set_ts_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) state->config->set_ts_params(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* Tune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (fe->ops.tuner_ops.set_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* ds3000 global reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ds3000_writereg(state, 0x07, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ds3000_writereg(state, 0x07, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* ds3000 built-in uC reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ds3000_writereg(state, 0xb2, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* ds3000 software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ds3000_writereg(state, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) switch (c->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) case SYS_DVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* initialise the demod in DVB-S mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ds3000_writereg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ds3000_dvbs_init_tab[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ds3000_dvbs_init_tab[i + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) value = ds3000_readreg(state, 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) value &= 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) value |= 0x1b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ds3000_writereg(state, 0xfe, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) case SYS_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* initialise the demod in DVB-S2 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ds3000_writereg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ds3000_dvbs2_init_tab[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ds3000_dvbs2_init_tab[i + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (c->symbol_rate >= 30000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ds3000_writereg(state, 0xfe, 0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ds3000_writereg(state, 0xfe, 0x98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* enable 27MHz clock output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ds3000_writereg(state, 0x29, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* enable ac coupling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ds3000_writereg(state, 0x25, 0x8a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if ((c->symbol_rate < ds3000_ops.info.symbol_rate_min) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) (c->symbol_rate > ds3000_ops.info.symbol_rate_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) dprintk("%s() symbol_rate %u out of range (%u ... %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) __func__, c->symbol_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ds3000_ops.info.symbol_rate_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ds3000_ops.info.symbol_rate_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* enhance symbol rate performance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if ((c->symbol_rate / 1000) <= 5000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) value = 29777 / (c->symbol_rate / 1000) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (value % 2 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) value++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ds3000_writereg(state, 0xc3, 0x0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ds3000_writereg(state, 0xc8, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ds3000_writereg(state, 0xc4, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ds3000_writereg(state, 0xc7, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) } else if ((c->symbol_rate / 1000) <= 10000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) value = 92166 / (c->symbol_rate / 1000) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (value % 2 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) value++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ds3000_writereg(state, 0xc3, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ds3000_writereg(state, 0xc8, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ds3000_writereg(state, 0xc4, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ds3000_writereg(state, 0xc7, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) } else if ((c->symbol_rate / 1000) <= 20000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) value = 64516 / (c->symbol_rate / 1000) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ds3000_writereg(state, 0xc3, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ds3000_writereg(state, 0xc8, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ds3000_writereg(state, 0xc4, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ds3000_writereg(state, 0xc7, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) value = 129032 / (c->symbol_rate / 1000) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ds3000_writereg(state, 0xc3, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ds3000_writereg(state, 0xc8, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ds3000_writereg(state, 0xc4, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ds3000_writereg(state, 0xc7, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* normalized symbol rate rounded to the closest integer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) value = (((c->symbol_rate / 1000) << 16) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ds3000_writereg(state, 0x61, value & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* co-channel interference cancellation disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ds3000_writereg(state, 0x56, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* equalizer disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ds3000_writereg(state, 0x76, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /*ds3000_writereg(state, 0x08, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) ds3000_writereg(state, 0xfd, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ds3000_writereg(state, 0x08, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ds3000_writereg(state, 0xfd, 0x42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ds3000_writereg(state, 0x08, 0x07);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (state->config->ci_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) switch (c->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) case SYS_DVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ds3000_writereg(state, 0xfd, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) case SYS_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ds3000_writereg(state, 0xfd, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* ds3000 out of software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ds3000_writereg(state, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* start ds3000 built-in uC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ds3000_writereg(state, 0xb2, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (fe->ops.tuner_ops.get_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) fe->ops.tuner_ops.get_frequency(fe, &frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) offset_khz = frequency - c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ds3000_set_carrier_offset(fe, offset_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) for (i = 0; i < 30 ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ds3000_read_status(fe, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (status & FE_HAS_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static int ds3000_tune(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) bool re_tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) unsigned int mode_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) unsigned int *delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (re_tune) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) int ret = ds3000_set_frontend(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) *delay = HZ / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return ds3000_read_status(fe, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (state->config->set_lock_led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) state->config->set_lock_led(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return DVBFE_ALGO_HW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * Initialise or wake up device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * Power config will reset and load initial firmware if required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static int ds3000_initfe(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct ds3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* hard reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* Load the firmware if required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ret = ds3000_firmware_ondemand(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static const struct dvb_frontend_ops ds3000_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .delsys = { SYS_DVBS, SYS_DVBS2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .name = "Montage Technology DS3000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .frequency_min_hz = 950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .frequency_stepsize_hz = 1011 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .frequency_tolerance_hz = 5 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .symbol_rate_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .symbol_rate_max = 45000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) FE_CAN_2G_MODULATION |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) FE_CAN_QPSK | FE_CAN_RECOVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .release = ds3000_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .init = ds3000_initfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .i2c_gate_ctrl = ds3000_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .read_status = ds3000_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .read_ber = ds3000_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .read_signal_strength = ds3000_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .read_snr = ds3000_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .read_ucblocks = ds3000_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .set_voltage = ds3000_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .set_tone = ds3000_set_tone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .diseqc_send_burst = ds3000_diseqc_send_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .get_frontend_algo = ds3000_get_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .set_frontend = ds3000_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .tune = ds3000_tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) MODULE_DESCRIPTION("DVB Frontend module for Montage Technology DS3000 hardware");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) MODULE_FIRMWARE(DS3000_DEFAULT_FIRMWARE);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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