^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #define AUD_COMM_EXEC__A 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define AUD_COMM_EXEC_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define FEC_COMM_EXEC__A 0x1C00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define FEC_COMM_EXEC_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define FEC_COMM_EXEC_ACTIVE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define FEC_DI_COMM_EXEC__A 0x1C20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define FEC_DI_COMM_EXEC_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define FEC_DI_INPUT_CTL__A 0x1C20016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define FEC_RS_COMM_EXEC__A 0x1C30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define FEC_RS_COMM_EXEC_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define FEC_RS_NR_BIT_ERRORS__A 0x1C30014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FEC_OC_MODE__A 0x1C40011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FEC_OC_MODE_PARITY__M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FEC_OC_DTO_MODE__A 0x1C40014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FEC_OC_DTO_MODE_DYNAMIC__M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FEC_OC_DTO_PERIOD__A 0x1C40015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FEC_OC_DTO_BURST_LEN__A 0x1C40018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FEC_OC_FCT_MODE__A 0x1C4001A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FEC_OC_FCT_MODE__PRE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FEC_OC_FCT_MODE_RAT_ENA__M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FEC_OC_TMD_MODE__A 0x1C4001E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FEC_OC_TMD_COUNT__A 0x1C4001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FEC_OC_TMD_HI_MARGIN__A 0x1C40020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FEC_OC_TMD_LO_MARGIN__A 0x1C40021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FEC_OC_AVR_PARM_A__A 0x1C40026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FEC_OC_AVR_PARM_B__A 0x1C40027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FEC_OC_RCN_GAIN__A 0x1C4002E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FEC_OC_SNC_MODE__A 0x1C40040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FEC_OC_SNC_LWM__A 0x1C40041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FEC_OC_SNC_HWM__A 0x1C40042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FEC_OC_SNC_UNLOCK__A 0x1C40043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FEC_OC_IPR_MODE__A 0x1C40048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FEC_OC_IPR_MODE_SERIAL__M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FEC_OC_IPR_INVERT__A 0x1C40049
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FEC_OC_IPR_INVERT_MD0__M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FEC_OC_IPR_INVERT_MD1__M 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FEC_OC_IPR_INVERT_MD2__M 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FEC_OC_IPR_INVERT_MD3__M 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FEC_OC_IPR_INVERT_MD4__M 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FEC_OC_IPR_INVERT_MD5__M 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FEC_OC_IPR_INVERT_MD6__M 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FEC_OC_IPR_INVERT_MD7__M 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FEC_OC_IPR_INVERT_MERR__M 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FEC_OC_IPR_INVERT_MSTRT__M 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FEC_OC_IPR_INVERT_MVAL__M 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FEC_OC_IPR_INVERT_MCLK__M 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FEC_OC_OCR_INVERT__A 0x1C40052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IQM_COMM_EXEC__A 0x1800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IQM_COMM_EXEC_B_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IQM_COMM_EXEC_B_ACTIVE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IQM_FS_RATE_OFS_LO__A 0x1820010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IQM_FS_ADJ_SEL__A 0x1820014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IQM_FS_ADJ_SEL_B_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IQM_FS_ADJ_SEL_B_QAM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IQM_FS_ADJ_SEL_B_VSB 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IQM_FD_RATESEL__A 0x1830010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IQM_RC_RATE_OFS_LO__A 0x1840010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IQM_RC_RATE_OFS_LO__W 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IQM_RC_RATE_OFS_LO__M 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IQM_RC_RATE_OFS_HI__M 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IQM_RC_ADJ_SEL__A 0x1840014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IQM_RC_ADJ_SEL_B_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IQM_RC_ADJ_SEL_B_QAM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IQM_RC_ADJ_SEL_B_VSB 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IQM_RC_STRETCH__A 0x1840016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IQM_CF_COMM_INT_MSK__A 0x1860006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IQM_CF_SYMMETRIC__A 0x1860010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IQM_CF_MIDTAP__A 0x1860011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IQM_CF_MIDTAP_RE__B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IQM_CF_MIDTAP_IM__B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IQM_CF_OUT_ENA__A 0x1860012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IQM_CF_OUT_ENA_QAM__B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IQM_CF_OUT_ENA_OFDM__M 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IQM_CF_ADJ_SEL__A 0x1860013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IQM_CF_SCALE__A 0x1860014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IQM_CF_SCALE_SH__A 0x1860015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IQM_CF_SCALE_SH__PRE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IQM_CF_POW_MEAS_LEN__A 0x1860017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IQM_CF_DS_ENA__A 0x1860019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IQM_CF_TAP_RE0__A 0x1860020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IQM_CF_TAP_IM0__A 0x1860040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IQM_CF_CLP_VAL__A 0x1860060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IQM_CF_DATATH__A 0x1860061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IQM_CF_PKDTH__A 0x1860062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IQM_CF_WND_LEN__A 0x1860063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IQM_CF_DET_LCT__A 0x1860064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IQM_CF_BYPASSDET__A 0x1860067
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IQM_AF_COMM_EXEC__A 0x1870000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IQM_AF_COMM_EXEC_ACTIVE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IQM_AF_CLKNEG__A 0x1870012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IQM_AF_START_LOCK__A 0x187001B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IQM_AF_PHASE0__A 0x187001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IQM_AF_PHASE1__A 0x187001D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IQM_AF_PHASE2__A 0x187001E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IQM_AF_CLP_LEN__A 0x1870023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IQM_AF_CLP_TH__A 0x1870024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IQM_AF_SNS_LEN__A 0x1870026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IQM_AF_AGC_IF__A 0x1870028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IQM_AF_AGC_RF__A 0x1870029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IQM_AF_PDREF__A 0x187002B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IQM_AF_PDREF__M 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IQM_AF_STDBY__A 0x187002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IQM_AF_AMUX__A 0x187002D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IQM_AF_AMUX_SIGNAL2ADC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IQM_AF_UPD_SEL__A 0x187002F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IQM_AF_INC_LCT__A 0x1870034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IQM_AF_INC_BYPASS__A 0x1870036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OFDM_CP_COMM_EXEC__A 0x2800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OFDM_CP_COMM_EXEC_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OFDM_EC_SB_PRIOR__A 0x3410013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OFDM_EC_SB_PRIOR_HI 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OFDM_EC_SB_PRIOR_LO 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OFDM_LC_COMM_EXEC__A 0x3800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OFDM_LC_COMM_EXEC_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OFDM_SC_COMM_EXEC__A 0x3C00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OFDM_SC_COMM_EXEC_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OFDM_SC_COMM_STATE__A 0x3C00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OFDM_SC_RA_RAM_CMD__A 0x3C20043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OFDM_SC_RA_RAM_CMD_NULL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OFDM_SC_RA_RAM_CMD_PROC_START 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OFDM_SC_RA_RAM_CMD_USER_IO 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define QAM_COMM_EXEC__A 0x1400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define QAM_COMM_EXEC_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define QAM_COMM_EXEC_ACTIVE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define QAM_TOP_ANNEX_A 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define QAM_TOP_ANNEX_C 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define QAM_SL_ERR_POWER__A 0x1430017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define QAM_DQ_QUAL_FUN0__A 0x1440018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define QAM_DQ_QUAL_FUN1__A 0x1440019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define QAM_DQ_QUAL_FUN2__A 0x144001A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define QAM_DQ_QUAL_FUN3__A 0x144001B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define QAM_DQ_QUAL_FUN4__A 0x144001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define QAM_DQ_QUAL_FUN5__A 0x144001D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define QAM_LC_MODE__A 0x1450010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define QAM_LC_QUAL_TAB0__A 0x1450018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define QAM_LC_QUAL_TAB1__A 0x1450019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define QAM_LC_QUAL_TAB2__A 0x145001A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define QAM_LC_QUAL_TAB3__A 0x145001B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define QAM_LC_QUAL_TAB4__A 0x145001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define QAM_LC_QUAL_TAB5__A 0x145001D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define QAM_LC_QUAL_TAB6__A 0x145001E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define QAM_LC_QUAL_TAB8__A 0x145001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define QAM_LC_QUAL_TAB9__A 0x1450020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define QAM_LC_QUAL_TAB10__A 0x1450021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define QAM_LC_QUAL_TAB12__A 0x1450022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define QAM_LC_QUAL_TAB15__A 0x1450023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define QAM_LC_QUAL_TAB16__A 0x1450024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define QAM_LC_QUAL_TAB20__A 0x1450025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define QAM_LC_QUAL_TAB25__A 0x1450026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define QAM_LC_LPF_FACTORP__A 0x1450028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define QAM_LC_LPF_FACTORI__A 0x1450029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define QAM_LC_RATE_LIMIT__A 0x145002A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define QAM_LC_SYMBOL_FREQ__A 0x145002B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define QAM_SY_TIMEOUT__A 0x1470011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define QAM_SY_TIMEOUT__PRE 0x3A98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define QAM_SY_SYNC_LWM__A 0x1470012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define QAM_SY_SYNC_AWM__A 0x1470013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define QAM_SY_SYNC_HWM__A 0x1470014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define QAM_SY_SP_INV__A 0x1470017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SCU_COMM_EXEC__A 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SCU_COMM_EXEC_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SCU_COMM_EXEC_ACTIVE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SCU_COMM_EXEC_HOLD 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SCU_RAM_DRIVER_DEBUG__A 0x831EBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SCU_RAM_GPIO__A 0x831EC7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SCU_RAM_AGC_RF_MAX__A 0x831F1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SCU_RAM_AGC_CONFIG__A 0x831F24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SCU_RAM_AGC_KI__A 0x831F25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SCU_RAM_AGC_KI_RF__B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SCU_RAM_AGC_KI_RF__M 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SCU_RAM_AGC_KI_IF__B 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SCU_RAM_AGC_KI_IF__M 0xF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SCU_RAM_AGC_KI_RED__A 0x831F26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SCU_RAM_AGC_KI_MIN__A 0x831F2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SCU_RAM_AGC_KI_MAX__A 0x831F2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SCU_RAM_AGC_CLP_SUM__A 0x831F2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SCU_RAM_AGC_SNS_SUM__A 0x831F35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SCU_RAM_QAM_FSM_RTH__A 0x831F8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SCU_RAM_QAM_FSM_FTH__A 0x831F8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SCU_RAM_QAM_FSM_PTH__A 0x831F90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SCU_RAM_QAM_FSM_MTH__A 0x831F91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SCU_RAM_QAM_FSM_CTH__A 0x831F92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SCU_RAM_QAM_FSM_QTH__A 0x831F93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SCU_RAM_DRIVER_VER_HI__A 0x831FEB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SCU_RAM_DRIVER_VER_LO__A 0x831FEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SCU_RAM_PARAM_15__A 0x831FED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SCU_RAM_PARAM_0__A 0x831FFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SCU_RAM_COMMAND__A 0x831FFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SCU_RAM_COMMAND_STANDARD_QAM 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SCU_RAM_COMMAND_STANDARD_OFDM 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SIO_TOP_COMM_KEY__A 0x41000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SIO_TOP_COMM_KEY_KEY 0xFABA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SIO_TOP_JTAGID_LO__A 0x410012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SIO_HI_RA_RAM_RES__A 0x420031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SIO_HI_RA_RAM_CMD__A 0x420032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SIO_HI_RA_RAM_CMD_RESET 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SIO_HI_RA_RAM_CMD_CONFIG 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SIO_HI_RA_RAM_PAR_1__A 0x420033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SIO_HI_RA_RAM_PAR_2__A 0x420034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SIO_HI_RA_RAM_PAR_3__A 0x420035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SIO_HI_RA_RAM_PAR_4__A 0x420036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SIO_HI_RA_RAM_PAR_5__A 0x420037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SIO_HI_RA_RAM_PAR_6__A 0x420038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SIO_CC_PLL_LOCK__A 0x450012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SIO_CC_PWD_MODE__A 0x450015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SIO_CC_PWD_MODE_LEVEL_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SIO_CC_PWD_MODE_LEVEL_PLL 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define SIO_CC_PWD_MODE_LEVEL_OSC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define SIO_CC_SOFT_RST__A 0x450016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SIO_CC_SOFT_RST_OFDM__M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SIO_CC_SOFT_RST_SYS__M 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define SIO_CC_SOFT_RST_OSC__M 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SIO_CC_UPDATE__A 0x450017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SIO_CC_UPDATE_KEY 0xFABA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SIO_BL_COMM_EXEC__A 0x480000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define SIO_BL_COMM_EXEC_ACTIVE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SIO_BL_STATUS__A 0x480010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SIO_BL_MODE__A 0x480011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define SIO_BL_MODE_DIRECT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define SIO_BL_MODE_CHAIN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define SIO_BL_ENABLE__A 0x480012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define SIO_BL_ENABLE_ON 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SIO_BL_TGT_HDR__A 0x480014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define SIO_BL_TGT_ADDR__A 0x480015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define SIO_BL_SRC_ADDR__A 0x480016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define SIO_BL_SRC_LEN__A 0x480017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SIO_BL_CHAIN_ADDR__A 0x480018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SIO_BL_CHAIN_LEN__A 0x480019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define SIO_PDR_MON_CFG__A 0x7F0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define SIO_PDR_UIO_IN_HI__A 0x7F0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SIO_PDR_UIO_OUT_LO__A 0x7F0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define SIO_PDR_OHW_CFG__A 0x7F001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define SIO_PDR_GPIO_CFG__A 0x7F0021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SIO_PDR_MSTRT_CFG__A 0x7F0025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SIO_PDR_MERR_CFG__A 0x7F0026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SIO_PDR_MCLK_CFG__A 0x7F0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SIO_PDR_MCLK_CFG_DRIVE__B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SIO_PDR_MVAL_CFG__A 0x7F0029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SIO_PDR_MD0_CFG__A 0x7F002A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SIO_PDR_MD0_CFG_DRIVE__B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SIO_PDR_MD1_CFG__A 0x7F002B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SIO_PDR_MD2_CFG__A 0x7F002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SIO_PDR_MD3_CFG__A 0x7F002D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SIO_PDR_MD4_CFG__A 0x7F002F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SIO_PDR_MD5_CFG__A 0x7F0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define SIO_PDR_MD6_CFG__A 0x7F0031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SIO_PDR_MD7_CFG__A 0x7F0032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SIO_PDR_SMA_RX_CFG__A 0x7F0037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define SIO_PDR_SMA_TX_CFG__A 0x7F0038
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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