Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #include "drxk_map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #define DRXK_VERSION_MAJOR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #define DRXK_VERSION_MINOR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define DRXK_VERSION_PATCH 4300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define HI_I2C_DELAY        42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define HI_I2C_BRIDGE_DELAY 350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define DRXK_MAX_RETRIES    100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define DRIVER_4400 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define DRXX_JTAGID   0x039210D9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DRXX_J_JTAGID 0x239310D9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DRXX_K_JTAGID 0x039210D9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DRX_UNKNOWN     254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define DRX_AUTO        255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DRX_SCU_READY   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DRXK_MAX_WAITTIME (200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SCU_RESULT_OK      0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SCU_RESULT_SIZE   -4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SCU_RESULT_INVPAR -3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SCU_RESULT_UNKSTD -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SCU_RESULT_UNKCMD -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DRXK_8VSB_MPEG_BIT_RATE     19392658UL  /*bps*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DRXK_DVBT_MPEG_BIT_RATE     32000000UL  /*bps*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DRXK_QAM16_MPEG_BIT_RATE    27000000UL  /*bps*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DRXK_QAM32_MPEG_BIT_RATE    33000000UL  /*bps*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DRXK_QAM64_MPEG_BIT_RATE    40000000UL  /*bps*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DRXK_QAM128_MPEG_BIT_RATE   46000000UL  /*bps*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DRXK_QAM256_MPEG_BIT_RATE   52000000UL  /*bps*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DRXK_MAX_MPEG_BIT_RATE      52000000UL  /*bps*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define   IQM_CF_OUT_ENA_OFDM__M                                            0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define     IQM_FS_ADJ_SEL_B_QAM                                            0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define     IQM_FS_ADJ_SEL_B_OFF                                            0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define     IQM_FS_ADJ_SEL_B_VSB                                            0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define     IQM_RC_ADJ_SEL_B_OFF                                            0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define     IQM_RC_ADJ_SEL_B_QAM                                            0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define     IQM_RC_ADJ_SEL_B_VSB                                            0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) enum operation_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	OM_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	OM_QAM_ITU_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	OM_QAM_ITU_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	OM_QAM_ITU_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	OM_DVBT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) enum drx_power_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	DRX_POWER_UP = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	DRX_POWER_MODE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	DRX_POWER_MODE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	DRX_POWER_MODE_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	DRX_POWER_MODE_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	DRX_POWER_MODE_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	DRX_POWER_MODE_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	DRX_POWER_MODE_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	DRX_POWER_MODE_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	DRX_POWER_MODE_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	DRX_POWER_MODE_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	DRX_POWER_MODE_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	DRX_POWER_MODE_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	DRX_POWER_MODE_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	DRX_POWER_MODE_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	DRX_POWER_MODE_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	DRX_POWER_MODE_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	DRX_POWER_DOWN = 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* Intermediate power mode for DRXK, power down OFDM clock domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #ifndef DRXK_POWER_DOWN_OFDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define DRXK_POWER_DOWN_OFDM        DRX_POWER_MODE_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* Intermediate power mode for DRXK, power down core (sysclk) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #ifndef DRXK_POWER_DOWN_CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define DRXK_POWER_DOWN_CORE        DRX_POWER_MODE_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* Intermediate power mode for DRXK, power down pll (only osc runs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #ifndef DRXK_POWER_DOWN_PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define DRXK_POWER_DOWN_PLL         DRX_POWER_MODE_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) enum agc_ctrl_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	DRXK_AGC_CTRL_AUTO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	DRXK_AGC_CTRL_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	DRXK_AGC_CTRL_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum e_drxk_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	DRXK_UNINITIALIZED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	DRXK_STOPPED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	DRXK_DTV_STARTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	DRXK_ATV_STARTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	DRXK_POWERED_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	DRXK_NO_DEV			/* If drxk init failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum e_drxk_coef_array_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	DRXK_COEF_IDX_MN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	DRXK_COEF_IDX_FM    ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	DRXK_COEF_IDX_L     ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	DRXK_COEF_IDX_LP    ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	DRXK_COEF_IDX_BG    ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	DRXK_COEF_IDX_DK    ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	DRXK_COEF_IDX_I     ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	DRXK_COEF_IDX_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum e_drxk_sif_attenuation {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	DRXK_SIF_ATTENUATION_0DB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	DRXK_SIF_ATTENUATION_3DB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	DRXK_SIF_ATTENUATION_6DB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	DRXK_SIF_ATTENUATION_9DB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) enum e_drxk_constellation {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	DRX_CONSTELLATION_BPSK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	DRX_CONSTELLATION_QPSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	DRX_CONSTELLATION_PSK8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	DRX_CONSTELLATION_QAM16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	DRX_CONSTELLATION_QAM32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	DRX_CONSTELLATION_QAM64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	DRX_CONSTELLATION_QAM128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	DRX_CONSTELLATION_QAM256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	DRX_CONSTELLATION_QAM512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	DRX_CONSTELLATION_QAM1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	DRX_CONSTELLATION_AUTO    = DRX_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) enum e_drxk_interleave_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	DRXK_QAM_I12_J17    = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	DRXK_QAM_I_UNKNOWN  = DRX_UNKNOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	DRXK_SPIN_A1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	DRXK_SPIN_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	DRXK_SPIN_A3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	DRXK_SPIN_UNKNOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) enum drxk_cfg_dvbt_sqi_speed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	DRXK_DVBT_SQI_SPEED_FAST = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	DRXK_DVBT_SQI_SPEED_MEDIUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	DRXK_DVBT_SQI_SPEED_SLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) enum drx_fftmode_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	DRX_FFTMODE_2K = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	DRX_FFTMODE_4K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	DRX_FFTMODE_8K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	DRX_FFTMODE_AUTO    = DRX_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) enum drxmpeg_str_width_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	DRX_MPEG_STR_WIDTH_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	DRX_MPEG_STR_WIDTH_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) enum drx_qam_lock_range_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	DRX_QAM_LOCKRANGE_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	DRX_QAM_LOCKRANGE_EXTENDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct drxk_cfg_dvbt_echo_thres_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u16             threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	enum drx_fftmode_t      fft_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct s_cfg_agc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	enum agc_ctrl_mode     ctrl_mode;        /* off, user, auto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u16            output_level;     /* range dependent on AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u16            min_output_level;  /* range dependent on AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	u16            max_output_level;  /* range dependent on AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	u16            speed;           /* range dependent on AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	u16            top;             /* rf-agc take over point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	u16            cut_off_current;   /* rf-agc is accelerated if output current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 					   is below cut-off current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	u16            ingain_tgt_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	u16            fast_clip_ctrl_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct s_cfg_pre_saw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u16        reference; /* pre SAW reference value, range 0 .. 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	bool          use_pre_saw; /* TRUE algorithms must use pre SAW sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct drxk_ofdm_sc_cmd_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u16 cmd;        /* Command number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	u16 subcmd;     /* Sub-command parameter*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	u16 param0;     /* General purpous param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u16 param1;     /* General purpous param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u16 param2;     /* General purpous param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u16 param3;     /* General purpous param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	u16 param4;     /* General purpous param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct drxk_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct dtv_frontend_properties props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	u8     demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	void  *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	u32    m_instance;           /* Channel 1,2,3 or 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int    m_chunk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	u8 chunk[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	bool   m_has_lna;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	bool   m_has_dvbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	bool   m_has_dvbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	bool   m_has_audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	bool   m_has_atv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	bool   m_has_oob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	bool   m_has_sawsw;         /* TRUE if mat_tx is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	bool   m_has_gpio1;         /* TRUE if mat_rx is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	bool   m_has_gpio2;         /* TRUE if GPIO is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	bool   m_has_irqn;          /* TRUE if IRQN is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	u16    m_osc_clock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	u16    m_hi_cfg_timing_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	u16    m_hi_cfg_bridge_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	u16    m_hi_cfg_wake_up_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	u16    m_hi_cfg_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	u16    m_hi_cfg_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	s32    m_sys_clock_freq;      /* system clock frequency in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	enum e_drxk_state    m_drxk_state;      /* State of Drxk (init,stopped,started) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	enum operation_mode m_operation_mode;  /* digital standards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct s_cfg_agc     m_vsb_rf_agc_cfg;    /* settings for VSB RF-AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct s_cfg_agc     m_vsb_if_agc_cfg;    /* settings for VSB IF-AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	u16                m_vsb_pga_cfg;      /* settings for VSB PGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct s_cfg_pre_saw  m_vsb_pre_saw_cfg;   /* settings for pre SAW sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	s32    m_Quality83percent;  /* MER level (*0.1 dB) for 83% quality indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	s32    m_Quality93percent;  /* MER level (*0.1 dB) for 93% quality indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	bool   m_smart_ant_inverted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	bool   m_b_debug_enable_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	bool   m_b_p_down_open_bridge;  /* only open DRXK bridge before power-down once it has been accessed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	bool   m_b_power_down;        /* Power down when not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	u32    m_iqm_fs_rate_ofs;      /* frequency shift as written to DRXK register (28bit fixpoint) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	bool   m_enable_mpeg_output;  /* If TRUE, enable MPEG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	bool   m_insert_rs_byte;      /* If TRUE, insert RS byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	bool   m_enable_parallel;    /* If TRUE, parallel out otherwise serial */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	bool   m_invert_data;        /* If TRUE, invert DATA signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	bool   m_invert_err;         /* If TRUE, invert ERR signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	bool   m_invert_str;         /* If TRUE, invert STR signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	bool   m_invert_val;         /* If TRUE, invert VAL signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	bool   m_invert_clk;         /* If TRUE, invert CLK signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	bool   m_dvbc_static_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	bool   m_dvbt_static_clk;     /* If TRUE, static MPEG clockrate will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 					 be used, otherwise clockrate will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 					 adapt to the bitrate of the TS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	u32    m_dvbt_bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	u32    m_dvbc_bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	u8     m_ts_data_strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	u8     m_ts_clockk_strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	bool   m_itut_annex_c;      /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	enum drxmpeg_str_width_t  m_width_str;    /* MPEG start width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	u32    m_mpeg_ts_static_bitrate;          /* Maximum bitrate in b/s in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 						    static clockrate is selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/* LARGE_INTEGER   m_startTime; */     /* Contains the time of the last demod start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	s32    m_mpeg_lock_time_out;      /* WaitForLockStatus Timeout (counts from start time) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	s32    m_demod_lock_time_out;     /* WaitForLockStatus Timeout (counts from start time) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	bool   m_disable_te_ihandling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	bool   m_rf_agc_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	bool   m_if_agc_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct s_cfg_agc    m_atv_rf_agc_cfg;  /* settings for ATV RF-AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct s_cfg_agc    m_atv_if_agc_cfg;  /* settings for ATV IF-AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	struct s_cfg_pre_saw m_atv_pre_saw_cfg; /* settings for ATV pre SAW sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	bool              m_phase_correction_bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	s16               m_atv_top_vid_peak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	u16               m_atv_top_noise_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	enum e_drxk_sif_attenuation m_sif_attenuation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	bool              m_enable_cvbs_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	bool              m_enable_sif_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	bool              m_b_mirror_freq_spect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	enum e_drxk_constellation  m_constellation; /* constellation type of the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	u32               m_curr_symbol_rate;       /* Current QAM symbol rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	struct s_cfg_agc    m_qam_rf_agc_cfg;          /* settings for QAM RF-AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct s_cfg_agc    m_qam_if_agc_cfg;          /* settings for QAM IF-AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	u16               m_qam_pga_cfg;            /* settings for QAM PGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct s_cfg_pre_saw m_qam_pre_saw_cfg;         /* settings for QAM pre SAW sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	enum e_drxk_interleave_mode m_qam_interleave_mode; /* QAM Interleave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	u16               m_fec_rs_plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	u16               m_fec_rs_prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	enum drxk_cfg_dvbt_sqi_speed m_sqi_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	u16               m_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	u16               m_gpio_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	struct s_cfg_agc    m_dvbt_rf_agc_cfg;     /* settings for QAM RF-AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	struct s_cfg_agc    m_dvbt_if_agc_cfg;     /* settings for QAM IF-AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	struct s_cfg_pre_saw m_dvbt_pre_saw_cfg;    /* settings for QAM pre SAW sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	u16               m_agcfast_clip_ctrl_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	bool              m_adc_comp_passed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	u16               m_adcCompCoef[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	u16               m_adc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	u8               *m_microcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	int               m_microcode_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	bool		  m_drxk_a3_rom_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	bool              m_drxk_a3_patch_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	bool              m_rfmirror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	u8                m_device_spin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	u32               m_iqm_rc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	enum drx_power_mode m_current_power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	/* when true, avoids other devices to use the I2C bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	bool		  drxk_i2c_exclusive_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	 * Configurable parameters at the driver. They stores the values found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	 * at struct drxk_config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	u16	uio_mask;	/* Bits used by UIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	bool	enable_merr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	bool	single_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	bool	no_i2c_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	bool	antenna_dvbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	u16	antenna_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	enum fe_status fe_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	/* Firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	const char *microcode_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	struct completion fw_wait_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	int qam_demod_parameter_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define NEVER_LOCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define NOT_LOCKED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DEMOD_LOCK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define FEC_LOCK   3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define MPEG_LOCK  4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)