^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003-2007 Micronas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "drxd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "drxd_firm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CHUNK_SIZE 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRX_I2C_RMW 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRX_I2C_BROADCAST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRX_I2C_CLEARCRC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRX_I2C_SINGLE_MASTER 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRX_I2C_MODEFLAGS 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRX_I2C_FLAGS 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DEFAULT_LOCK_TIMEOUT 1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRX_CHANNEL_AUTO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRX_CHANNEL_HIGH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRX_CHANNEL_LOW 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRX_LOCK_MPEG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRX_LOCK_FEC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRX_LOCK_DEMOD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum CSCDState {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) CSCD_INIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CSCD_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CSCD_SAVED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum CDrxdState {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DRXD_UNINITIALIZED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DRXD_STOPPED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DRXD_STARTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum AGC_CTRL_MODE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) AGC_CTRL_AUTO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) AGC_CTRL_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) AGC_CTRL_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum OperationMode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) OM_Default,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) OM_DVBT_Diversity_Front,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) OM_DVBT_Diversity_End
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct SCfgAgc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum AGC_CTRL_MODE ctrlMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 R1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u16 R2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u16 R3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct SNoiseCal {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int cpOpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) short cpNexpOfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) short tdCal2k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) short tdCal8k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) enum app_env {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) APPENV_STATIC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) APPENV_PORTABLE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) APPENV_MOBILE = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) enum EIFFilter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) IFFILTER_SAW = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) IFFILTER_DISCRETE = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct drxd_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct dvb_frontend_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct dtv_frontend_properties props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct drxd_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int i2c_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int init_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 chip_adr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u16 hi_cfg_timing_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u16 hi_cfg_bridge_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u16 hi_cfg_wakeup_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u16 hi_cfg_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u16 intermediate_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u16 osc_clock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum CSCDState cscd_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) enum CDrxdState drxd_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u16 sys_clock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) s16 osc_clock_deviation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u16 expected_sys_clock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u16 insert_rs_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u16 enable_parallel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int operation_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct SCfgAgc if_agc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct SCfgAgc rf_agc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct SNoiseCal noise_cal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 fe_fs_add_incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 org_fe_fs_add_incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u16 current_fe_if_incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u16 m_FeAgRegAgPwd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u16 m_FeAgRegAgAgcSio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u16 m_EcOcRegOcModeLop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u16 m_EcOcRegSncSncLvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 *m_InitAtomicRead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 *m_HiI2cPatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 *m_ResetCEFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 *m_InitFE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u8 *m_InitFE_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 *m_InitCP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 *m_InitCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 *m_InitEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 *m_InitSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u8 *m_InitEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 *m_ResetECRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 *m_InitDiversityFront;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 *m_InitDiversityEnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 *m_DisableDiversity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 *m_StartDiversityFront;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u8 *m_StartDiversityEnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 *m_DiversityDelay8MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 *m_DiversityDelay6MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 *microcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 microcode_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int type_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int PGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int diversity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int tuner_mirrors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) enum app_env app_env_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) enum app_env app_env_diversity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* I2C **********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (i2c_transfer(adap, &msg, 1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int i2c_read(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 adr, u8 *msg, int len, u8 *answ, int alen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct i2c_msg msgs[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .addr = adr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .buf = msg, .len = len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .addr = adr, .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .buf = answ, .len = alen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (i2c_transfer(adap, msgs, 2) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static inline u32 MulDiv32(u32 a, u32 b, u32 c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u64 tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tmp64 = (u64)a * (u64)b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) do_div(tmp64, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return (u32) tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u8 adr = state->config.demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 mm2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *data = mm2[0] | (mm2[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return mm2[0] | (mm2[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u8 adr = state->config.demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u8 mm2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u8 adr = state->config.demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) data & 0xff, (data >> 8) & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (i2c_write(state->i2c, adr, mm, 6) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 adr = state->config.demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) data & 0xff, (data >> 8) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) (data >> 16) & 0xff, (data >> 24) & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (i2c_write(state->i2c, adr, mm, 8) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int write_chunk(struct drxd_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 reg, u8 *data, u32 len, u8 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 adr = state->config.demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mm[4 + i] = data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) printk(KERN_ERR "error in write_chunk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int WriteBlock(struct drxd_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) while (BlockSize > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pBlock += Chunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) Address += (Chunk >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) BlockSize -= Chunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int WriteTable(struct drxd_state *state, u8 * pTable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (!pTable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) while (!status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u16 Length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 Address = pTable[0] | (pTable[1] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) (pTable[2] << 16) | (pTable[3] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (Address == 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pTable += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) Length = pTable[0] | (pTable[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pTable += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!Length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) status = WriteBlock(state, Address, Length * 2, pTable, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pTable += (Length * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int ResetCEFR(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return WriteTable(state, state->m_ResetCEFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int InitCP(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return WriteTable(state, state->m_InitCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int InitCE(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) enum app_env AppEnv = state->app_env_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) status = WriteTable(state, state->m_InitCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (state->operation_mode == OM_DVBT_Diversity_Front ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) state->operation_mode == OM_DVBT_Diversity_End) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) AppEnv = state->app_env_diversity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (AppEnv == APPENV_STATIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } else if (AppEnv == APPENV_PORTABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) } else if (AppEnv == APPENV_MOBILE && state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* start ce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int StopOC(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u16 ocSyncLvl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u16 ocModeLop = state->m_EcOcRegOcModeLop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u16 dtoIncLop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u16 dtoIncHip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Store output configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) state->m_EcOcRegSncSncLvl = ocSyncLvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* m_EcOcRegOcModeLop = ocModeLop; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Flush FIFO (byte-boundary) at fixed rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Output pins to '0' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Force the OC out of sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ocModeLop |= 0x2; /* Magically-out-of-sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int StartOC(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Stop OC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Restore output configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Output pins active again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Start OC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int InitEQ(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return WriteTable(state, state->m_InitEQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int InitEC(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return WriteTable(state, state->m_InitEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int InitSC(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return WriteTable(state, state->m_InitSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int InitAtomicRead(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return WriteTable(state, state->m_InitAtomicRead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int CorrectSysClockDeviation(struct drxd_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u16 ScRaRamLock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) SC_RA_RAM_LOCK_FEC__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) SC_RA_RAM_LOCK_DEMOD__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) SC_RA_RAM_LOCK_DEMOD__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) *pLockStatus = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (state->drxd_state != DRXD_STARTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) *pLockStatus |= DRX_LOCK_MPEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) CorrectSysClockDeviation(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) *pLockStatus |= DRX_LOCK_FEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) *pLockStatus |= DRX_LOCK_DEMOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (cfg->ctrlMode == AGC_CTRL_USER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u16 FeAgRegPm1AgcWri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u16 FeAgRegAgModeLop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) FE_AG_REG_PM1_AGC_WRI__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u16 FeAgRegAgModeLop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u16 FeAgRegEgcSetLvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u16 slope, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* == Mode == */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) FeAgRegAgModeLop |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* == Settle level == */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) FE_AG_REG_EGC_SET_LVL__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* == Min/Max == */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) slope = (u16) ((cfg->maxOutputLevel -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) cfg->minOutputLevel) / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) offset = (u16) ((cfg->maxOutputLevel +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) cfg->minOutputLevel) / 2 - 511);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* == Speed == */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) const u16 maxRur = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const u16 slowIncrDecLUT[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 3, 4, 4, 5, 6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const u16 fastIncrDecLUT[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 14, 15, 15, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 17, 18, 18, 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 20, 21, 22, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 24, 26, 27, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 29, 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) (maxRur + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u16 fineSpeed = (u16) (cfg->speed -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ((cfg->speed /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) fineSteps) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) fineSteps));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u16 invRurCount = (u16) (cfg->speed /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) fineSteps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u16 rurCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (invRurCount > maxRur) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) rurCount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) fineSpeed += fineSteps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) rurCount = maxRur - invRurCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) fastInc = default *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) (2^(fineSpeed/fineSteps))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) => range[default...2*default>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) slowInc = default *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) (2^(fineSpeed/fineSteps))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u16 fastIncrDec =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) fastIncrDecLUT[fineSpeed /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ((fineSteps /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) (14 + 1)) + 1)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u16 slowIncrDec =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) slowIncrDecLUT[fineSpeed /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) (fineSteps /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) (3 + 1))];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* No OFF mode for IF control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (cfg->ctrlMode == AGC_CTRL_USER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u16 AgModeLop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u16 level = (cfg->outputLevel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (level == DRXD_FE_CTRL_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) level++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /*==== Mode ====*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Powerdown PD2, WRI source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) state->m_FeAgRegAgPwd |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) FE_AG_REG_AG_MODE_LOP_MODE_E__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* enable AGC2 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u16 FeAgRegAgAgcSio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) FeAgRegAgAgcSio &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) FeAgRegAgAgcSio |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u16 AgModeLop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u16 level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Automatic control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Powerup PD2, AGC2 as output, TGC source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) (state->m_FeAgRegAgPwd) &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) (state->m_FeAgRegAgPwd) |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) FE_AG_REG_AG_MODE_LOP_MODE_E__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Settle level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) level = (((cfg->settleLevel) >> 4) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) FE_AG_REG_TGC_SET_LVL__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* Min/max: don't care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* Speed: TODO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* enable AGC2 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) u16 FeAgRegAgAgcSio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) FeAgRegAgAgcSio &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) FeAgRegAgAgcSio |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u16 AgModeLop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* No RF AGC control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* Powerdown PD2, AGC2 as output, WRI source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) (state->m_FeAgRegAgPwd) &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) (state->m_FeAgRegAgPwd) |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) FE_AG_REG_AG_MODE_LOP_MODE_E__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* set FeAgRegAgAgcSio AGC2 (RF) as input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u16 FeAgRegAgAgcSio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) FeAgRegAgAgcSio &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) FeAgRegAgAgcSio |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) *pValue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u16 Value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) Value &= FE_AG_REG_GC1_AGC_DAT__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* 3.3V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) R1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) Vin - R3 - * -- Vout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) R2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) GND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 R1 = state->if_agc_cfg.R1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u32 R2 = state->if_agc_cfg.R2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u32 R3 = state->if_agc_cfg.R3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u32 Vmax, Rpar, Vmin, Vout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (R2 == 0 && (R1 == 0 || R3 == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) Vmax = (3300 * R2) / (R1 + R2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) Rpar = (R2 * R3) / (R3 + R2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) Vmin = (3300 * Rpar) / (R1 + Rpar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) *pValue = Vout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int load_firmware(struct drxd_state *state, const char *fw_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (request_firmware(&fw, fw_name, state->dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (!state->microcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) state->microcode_length = fw->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static int DownloadMicrocode(struct drxd_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) const u8 *pMCImage, u32 Length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u8 *pSrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) u32 Address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) u16 nBlocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u16 BlockSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) u32 offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int i, status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) pSrc = (u8 *) pMCImage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* We're not using Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* Flags = (pSrc[0] << 8) | pSrc[1]; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) pSrc += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) offset += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) nBlocks = (pSrc[0] << 8) | pSrc[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) pSrc += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) offset += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) for (i = 0; i < nBlocks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) (pSrc[2] << 8) | pSrc[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) pSrc += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) offset += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) pSrc += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) offset += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* We're not using Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) pSrc += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) offset += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* We're not using BlockCRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) pSrc += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) offset += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) status = WriteBlock(state, Address, BlockSize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) pSrc, DRX_I2C_CLEARCRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) pSrc += BlockSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) offset += BlockSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) u32 nrRetries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) nrRetries += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (nrRetries > DRXD_MAX_RETRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) } while (status != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (status >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static int HI_CfgCommand(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) status = Write16(state, HI_RA_RAM_SRV_CMD__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) HI_RA_RAM_SRV_CMD_CONFIG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static int InitHI(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) state->hi_cfg_wakeup_key = (state->chip_adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* port/bridge/power down ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return HI_CfgCommand(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static int HI_ResetCommand(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) HI_RA_RAM_SRV_RST_KEY_ACT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (bEnableBridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return HI_CfgCommand(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define HI_TR_WRITE 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define HI_TR_READ 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define HI_TR_READ_WRITE 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define HI_TR_BROADCAST 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int AtomicReadBlock(struct drxd_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Parameter check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if ((!pData) || ((DataSize & 1) != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* Instruct HI to read n bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* TODO use proper names forthese egisters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) for (i = 0; i < (DataSize / 2); i += 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) u16 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) &word, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) pData[2 * i] = (u8) (word & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) pData[(2 * i) + 1] = (u8) (word >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static int AtomicReadReg32(struct drxd_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) u32 Addr, u32 *pData, u8 Flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) u8 buf[sizeof(u32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (!pData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) *pData = (((u32) buf[0]) << 0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) (((u32) buf[1]) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static int StopAllProcessors(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return Write16(state, HI_COMM_EXEC__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static int EnableAndResetMB(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* disable? monitor bus observe @ EC_OC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* do inverse broadcast, followed by explicit write to HI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static int InitCC(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (state->osc_clock_freq == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) state->osc_clock_freq > 20000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) (state->osc_clock_freq % 4000) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) status |= Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) status |= Write16(state, CC_REG_PLL_MODE__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) CC_REG_PLL_MODE_BYPASS_PLL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) CC_REG_PLL_MODE_PUMP_CUR_12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) status |= Write16(state, CC_REG_REF_DIVIDE__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) state->osc_clock_freq / 4000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) status |= Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) status |= Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static int ResetECOD(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (state->type_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (!(status < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) status = WriteTable(state, state->m_ResetECRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (!(status < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* Configure PGA switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) u16 AgModeLop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) u16 AgModeHip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (pgaSwitch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* PGA on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* fine gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* coarse gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* enable fine and coarse gain, enable AAF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) no ext resistor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* PGA off, bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* fine gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* coarse gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* disable fine and coarse gain, enable AAF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) no ext resistor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static int InitFE(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) status = WriteTable(state, state->m_InitFE_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (state->PGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) status = SetCfgPga(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) status = WriteTable(state, state->m_InitFE_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static int InitFT(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) SC stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static int SC_WaitForReady(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static int SC_SendCommand(struct drxd_state *state, u16 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) int status = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) u16 errCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) status = Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) SC_WaitForReady(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ret = Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (ret < 0 || errCode == 0xFFFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) printk(KERN_ERR "Command Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) static int SC_ProcStartCommand(struct drxd_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) u16 subCmd, u16 param0, u16 param1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) int ret, status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) u16 scExec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ret = Read16(state, SC_COMM_EXEC__A, &scExec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (ret < 0 || scExec != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) SC_WaitForReady(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) status |= Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) status |= Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) status |= Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static int SC_SetPrefParamCommand(struct drxd_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) u16 subCmd, u16 param0, u16 param1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) status = SC_WaitForReady(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) status = SC_WaitForReady(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) u16 EcOcRegIprInvMpg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) u16 EcOcRegOcModeLop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) u16 EcOcRegOcModeHip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) u16 EcOcRegOcMpgSio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (state->operation_mode == OM_DVBT_Diversity_Front) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (bEnableOutput) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) EcOcRegOcModeHip |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) EcOcRegOcModeLop |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (bEnableOutput)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* Don't Insert RS Byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (state->insert_rs_byte) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) EcOcRegOcModeLop &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) EcOcRegOcModeHip &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) EcOcRegOcModeHip |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) EcOcRegOcModeLop |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) EcOcRegOcModeHip &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) EcOcRegOcModeHip |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /* Mode = Parallel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (state->enable_parallel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) EcOcRegOcModeLop &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) EcOcRegOcModeLop |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* Invert Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) /* EcOcRegIprInvMpg |= 0x00FF; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) EcOcRegIprInvMpg &= (~(0x00FF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /* Invert Error ( we don't use the pin ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /* EcOcRegIprInvMpg |= 0x0100; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) EcOcRegIprInvMpg &= (~(0x0100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /* Invert Start ( we don't use the pin ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* EcOcRegIprInvMpg |= 0x0200; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) EcOcRegIprInvMpg &= (~(0x0200));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* Invert Valid ( we don't use the pin ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* EcOcRegIprInvMpg |= 0x0400; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) EcOcRegIprInvMpg &= (~(0x0400));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* Invert Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /* EcOcRegIprInvMpg |= 0x0800; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) EcOcRegIprInvMpg &= (~(0x0800));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* EcOcRegOcModeLop =0x05; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static int SetDeviceTypeId(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) u16 deviceId = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* TODO: why twice? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) state->type_A = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) state->PGA = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) state->diversity = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (deviceId == 0) { /* on A2 only 3975 available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) state->type_A = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) printk(KERN_INFO "DRX3975D-A2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) deviceId >>= 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) switch (deviceId) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) state->diversity = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) state->PGA = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) state->diversity = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* Init Table selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) state->m_InitAtomicRead = DRXD_InitAtomicRead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) state->m_InitSC = DRXD_InitSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) state->m_ResetECRAM = DRXD_ResetECRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) state->m_ResetCEFR = DRXD_ResetCEFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) state->m_InitFE_1 = DRXD_InitFEA2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) state->m_InitFE_2 = DRXD_InitFEA2_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) state->m_InitCP = DRXD_InitCPA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) state->m_InitCE = DRXD_InitCEA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) state->m_InitEQ = DRXD_InitEQA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) state->m_InitEC = DRXD_InitECA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (load_firmware(state, DRX_FW_FILENAME_A2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) state->m_ResetCEFR = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) state->m_InitFE_1 = DRXD_InitFEB1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) state->m_InitFE_2 = DRXD_InitFEB1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) state->m_InitCP = DRXD_InitCPB1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) state->m_InitCE = DRXD_InitCEB1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) state->m_InitEQ = DRXD_InitEQB1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) state->m_InitEC = DRXD_InitECB1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (load_firmware(state, DRX_FW_FILENAME_B1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (state->diversity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) state->m_InitDiversityFront = DRXD_InitDiversityFront;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) state->m_DisableDiversity = DRXD_DisableDiversity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) state->m_StartDiversityFront = DRXD_StartDiversityFront;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) state->m_InitDiversityFront = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) state->m_InitDiversityEnd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) state->m_DisableDiversity = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) state->m_StartDiversityFront = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) state->m_StartDiversityEnd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) state->m_DiversityDelay8MHZ = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) state->m_DiversityDelay6MHZ = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static int CorrectSysClockDeviation(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) s32 incr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) s32 nomincr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) u32 bandwidth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) u32 sysClockInHz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) u32 sysClockFreq = 0; /* in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) s16 oscClockDeviation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) s16 Diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /* Retrieve bandwidth and incr, sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /* These accesses should be AtomicReadReg32, but that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) causes trouble (at least for diversity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if ((nomincr - incr < -500) || (nomincr - incr > 500))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) switch (state->props.bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) /* Compute new sysclock value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) incr += (1 << 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) sysClockFreq = (u32) (sysClockInHz / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) /* rounding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if ((sysClockInHz % 1000) > 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) sysClockFreq++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /* Compute clock deviation in ppm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) (s32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) (state->expected_sys_clock_freq)) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) 1000000L) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) (s32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) (state->expected_sys_clock_freq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) Diff = oscClockDeviation - state->osc_clock_deviation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (Diff >= -200 && Diff <= 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) state->sys_clock_freq = (u16) sysClockFreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (oscClockDeviation != state->osc_clock_deviation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (state->config.osc_deviation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) state->config.osc_deviation(state->priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) oscClockDeviation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) state->osc_clock_deviation =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) oscClockDeviation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* switch OFF SRMM scan in SC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) /* overrule FE_IF internal value for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) proper re-locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) state->cscd_state = CSCD_SAVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static int DRX_Stop(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if (state->drxd_state != DRXD_STARTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (state->cscd_state != CSCD_SAVED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) u32 lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) status = DRX_GetLockStatus(state, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) status = StopOC(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) state->drxd_state = DRXD_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) status = ConfigureMPEGOutput(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /* Stop relevant processors off the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* Stop all processors except HI & CC & FE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #if 0 /* Currently unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) static int SetOperationMode(struct drxd_state *state, int oMode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if (state->drxd_state != DRXD_STOPPED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) if (oMode == state->operation_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) if (oMode != OM_Default && !state->diversity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) switch (oMode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) case OM_DVBT_Diversity_Front:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) status = WriteTable(state, state->m_InitDiversityFront);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) case OM_DVBT_Diversity_End:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) status = WriteTable(state, state->m_InitDiversityEnd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) case OM_Default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) /* We need to check how to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) get DRXD out of diversity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) status = WriteTable(state, state->m_DisableDiversity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) state->operation_mode = oMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static int StartDiversity(struct drxd_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) u16 rcControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) if (state->operation_mode == OM_DVBT_Diversity_Front) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) status = WriteTable(state, state->m_StartDiversityFront);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) } else if (state->operation_mode == OM_DVBT_Diversity_End) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) status = WriteTable(state, state->m_StartDiversityEnd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (state->props.bandwidth_hz == 8000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) status = WriteTable(state, state->m_DiversityDelay8MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) status = WriteTable(state, state->m_DiversityDelay6MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) /* combining enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) static int SetFrequencyShift(struct drxd_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) u32 offsetFreq, int channelMirrored)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) int negativeShift = (state->tuner_mirrors == channelMirrored);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* Handle all mirroring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) * Note: ADC mirroring (aliasing) is implictly handled by limiting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) * feFsRegAddInc to 28 bits below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) * (if the result before masking is more than 28 bits, this means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) * that the ADC is mirroring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) * The masking is in fact the aliasing of the ADC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /* Compute register value, unsigned computation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) offsetFreq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) 1 << 28, state->sys_clock_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) /* Remove integer part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) state->fe_fs_add_incr &= 0x0FFFFFFFL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (negativeShift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) /* Save the frequency shift without tunerOffset compensation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) for CtrlGetChannel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) 1 << 28, state->sys_clock_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) /* Remove integer part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (negativeShift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) state->org_fe_fs_add_incr = ((1L << 28) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) state->org_fe_fs_add_incr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) state->fe_fs_add_incr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) static int SetCfgNoiseCalibration(struct drxd_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) struct SNoiseCal *noiseCal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) u16 beOptEna;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (noiseCal->cpOpt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) if (!state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static int DRX_Start(struct drxd_state *state, s32 off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) struct dtv_frontend_properties *p = &state->props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) u16 transmissionParams = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) u16 operationMode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) u16 qpskTdTpsPwr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) u16 qam16TdTpsPwr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) u16 qam64TdTpsPwr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) u32 feIfIncr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) u32 bandwidth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) int mirrorFreqSpect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) u16 qpskSnCeGain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) u16 qam16SnCeGain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) u16 qam64SnCeGain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) u16 qpskIsGainMan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) u16 qam16IsGainMan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) u16 qam64IsGainMan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) u16 qpskIsGainExp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) u16 qam16IsGainExp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) u16 qam64IsGainExp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) u16 bandwidthParam = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (off < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) off = (off - 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) off = (off + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (state->drxd_state != DRXD_STOPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) status = ResetECOD(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) status = InitSC(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) status = InitFT(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) status = InitCP(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) status = InitCE(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) status = InitEQ(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) status = InitSC(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) /* Restore current IF & RF AGC settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) status = SetCfgIfAgc(state, &state->if_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) status = SetCfgRfAgc(state, &state->rf_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) switch (p->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) default: /* Not set, detect it automatically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) fallthrough; /* try first guess DRX_FFTMODE_8K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) case TRANSMISSION_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) qpskSnCeGain = 99;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) qam16SnCeGain = 83;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) qam64SnCeGain = 67;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) case TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) qpskSnCeGain = 97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) qam16SnCeGain = 71;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) qam64SnCeGain = 65;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) switch (p->guard_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) case GUARD_INTERVAL_1_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) case GUARD_INTERVAL_1_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) case GUARD_INTERVAL_1_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) case GUARD_INTERVAL_1_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) default: /* Not set, detect it automatically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) /* try first guess 1/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) switch (p->hierarchy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) case HIERARCHY_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) qpskIsGainMan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) qam16IsGainMan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) qam64IsGainMan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) qpskIsGainExp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) qam16IsGainExp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) qam64IsGainExp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) case HIERARCHY_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) qpskIsGainMan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) qam16IsGainMan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) qam64IsGainMan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) qpskIsGainExp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) qam16IsGainExp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) qam64IsGainExp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) case HIERARCHY_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) qpskIsGainMan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) qam16IsGainMan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) qam64IsGainMan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) qpskIsGainExp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) qam16IsGainExp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) qam64IsGainExp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) case HIERARCHY_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) /* Not set, detect it automatically, start with none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) qpskIsGainMan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) qam16IsGainMan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) qam64IsGainMan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) qpskIsGainExp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) qam16IsGainExp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) qam64IsGainExp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) switch (p->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) fallthrough; /* try first guess DRX_CONSTELLATION_QAM64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) case QPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) switch (DRX_CHANNEL_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) case DRX_CHANNEL_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) case DRX_CHANNEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) case DRX_CHANNEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) switch (p->code_rate_HP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) if (state->type_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (state->type_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) if (state->type_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (state->type_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) if (state->type_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) /* First determine real bandwidth (Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) /* Also set delay for impulse noise cruncher (only A2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) /* Also set parameters for EC_OC fix, note
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) EC_OC_REG_TMD_HIL_MAR is changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) by SC for fix for some 8K,1/8 guard but is restored by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) InitEC and ResetEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) switch (p->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) p->bandwidth_hz = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) /* (64/7)*(8/8)*1000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) bandwidthParam = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) status = Write16(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) FE_AG_REG_IND_DEL__A, 50, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) /* (64/7)*(7/8)*1000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) status = Write16(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) FE_AG_REG_IND_DEL__A, 59, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) /* (64/7)*(6/8)*1000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) status = Write16(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) FE_AG_REG_IND_DEL__A, 71, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) u16 sc_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) /* enable SLAVE mode in 2k 1/32 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) prevent timing change glitches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) (p->guard_interval == GUARD_INTERVAL_1_32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) /* enable slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) /* disable slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) status = SetCfgNoiseCalibration(state, &state->noise_cal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) if (state->cscd_state == CSCD_INIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) /* switch on SRMM scan in SC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) /* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) state->cscd_state = CSCD_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) /* Now compute FE_IF_REG_INCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) (1ULL << 21), bandwidth) - (1 << 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) /* Bandwidth setting done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) /* Mirror & frequency offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) SetFrequencyShift(state, off, mirrorFreqSpect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) /* Start SC, write channel settings to SC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) /* Enable SC after setting all other parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) /* Write SC parameter registers, operation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) SC_RA_RAM_OP_AUTO_GUARD__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) SC_RA_RAM_OP_AUTO_CONST__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) SC_RA_RAM_OP_AUTO_HIER__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) SC_RA_RAM_OP_AUTO_RATE__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) /* Start correct processes to get in lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) status = StartOC(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) if (state->operation_mode != OM_Default) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) status = StartDiversity(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) state->drxd_state = DRXD_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) u32 ulRfAgcOutputLevel = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) u32 ulRfAgcMinLevel = 0; /* Currently unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) u32 ulRfAgcSpeed = 0; /* Currently unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) u32 ulRfAgcMode = 0; /*2; Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) u32 ulRfAgcR1 = 820;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) u32 ulRfAgcR2 = 2200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) u32 ulRfAgcR3 = 150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) u32 ulIfAgcMode = 0; /* Auto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) u32 ulIfAgcOutputLevel = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) u32 ulIfAgcSettleLevel = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) u32 ulIfAgcMinLevel = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) u32 ulIfAgcMaxLevel = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) u32 ulIfAgcSpeed = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) u32 ulIfAgcR1 = 820;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) u32 ulIfAgcR2 = 2200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) u32 ulIfAgcR3 = 150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) u32 ulClock = state->config.clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) u32 ulSerialMode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) u32 ulHiI2cDelay = HI_I2C_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) u32 ulHiI2cPatch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) u32 ulEnvironment = APPENV_PORTABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) u32 ulEnvironmentDiversity = APPENV_MOBILE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) u32 ulIFFilter = IFFILTER_SAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) state->if_agc_cfg.outputLevel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) state->if_agc_cfg.settleLevel = 140;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) state->if_agc_cfg.minOutputLevel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) state->if_agc_cfg.maxOutputLevel = 1023;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) state->if_agc_cfg.speed = 904;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) if (ulIfAgcMode == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) /* rest of the RFAgcCfg structure currently unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) if (ulRfAgcMode == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) if (ulRfAgcMode == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) if (ulEnvironment <= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) state->app_env_default = (enum app_env)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) (ulEnvironment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) if (ulEnvironmentDiversity <= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) state->app_env_diversity = (enum app_env)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) (ulEnvironmentDiversity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) if (ulIFFilter == IFFILTER_DISCRETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) /* discrete filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) state->noise_cal.cpOpt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) state->noise_cal.cpNexpOfs = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) state->noise_cal.tdCal2k = -40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) state->noise_cal.tdCal8k = -24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) /* SAW filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) state->noise_cal.cpOpt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) state->noise_cal.cpNexpOfs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) state->noise_cal.tdCal2k = -21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) state->noise_cal.tdCal8k = -24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) state->chip_adr = (state->config.demod_address << 1) | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) switch (ulHiI2cPatch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) state->m_HiI2cPatch = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) /* modify tuner and clock attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) /* expected system clock frequency in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) state->expected_sys_clock_freq = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) /* real system clock frequency in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) state->sys_clock_freq = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) state->osc_clock_freq = (u16) ulClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) state->osc_clock_deviation = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) state->cscd_state = CSCD_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) state->drxd_state = DRXD_UNINITIALIZED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) state->PGA = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) state->type_A = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) state->tuner_mirrors = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) /* modify MPEG output attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) state->insert_rs_byte = state->config.insert_rs_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) state->enable_parallel = (ulSerialMode != 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) /* Timing div, 250ns/Psys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) ulHiI2cDelay) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) /* Bridge delay, uses oscilator clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) ulHiI2cBridgeDelay) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) u32 driverVersion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) if (state->init_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) CDRXD(state, state->config.IF ? state->config.IF : 36000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) state->operation_mode = OM_Default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) status = SetDeviceTypeId(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) /* Apply I2c address patch to B1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) if (!state->type_A && state->m_HiI2cPatch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) status = WriteTable(state, state->m_HiI2cPatch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) /* HI firmware patch for UIO readout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) avoid clearing of result register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) status = Write16(state, 0x43012D, 0x047f, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) status = HI_ResetCommand(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) status = StopAllProcessors(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) status = InitCC(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) state->osc_clock_deviation = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) if (state->config.osc_deviation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) state->osc_clock_deviation =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) state->config.osc_deviation(state->priv, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) /* Handle clock deviation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) s32 devB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) s32 devA = (s32) (state->osc_clock_deviation) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) (s32) (state->expected_sys_clock_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) /* deviation in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) s32 deviation = (devA / (1000000L));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) /* rounding, signed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) if (devA > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) devB = (2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) devB = (-2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) if ((devB * (devA % 1000000L) > 1000000L)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) /* add +1 or -1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) deviation += (devB / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) state->sys_clock_freq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) (u16) ((state->expected_sys_clock_freq) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) deviation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) status = InitHI(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) status = InitAtomicRead(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) status = EnableAndResetMB(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) if (state->type_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) status = ResetCEFR(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) if (fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) status = DownloadMicrocode(state, fw, fw_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) status = DownloadMicrocode(state, state->microcode, state->microcode_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) if (state->PGA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) SetCfgPga(state, 0); /* PGA = 0 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) status = InitFE(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) status = InitFT(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) status = InitCP(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) status = InitCE(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) status = InitEQ(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) status = InitEC(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) status = InitSC(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) status = SetCfgIfAgc(state, &state->if_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) status = SetCfgRfAgc(state, &state->rf_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) state->cscd_state = CSCD_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) driverVersion = (((VERSION_MAJOR / 10) << 4) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) (VERSION_MAJOR % 10)) << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) driverVersion += (((VERSION_MINOR / 10) << 4) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) (VERSION_MINOR % 10)) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) driverVersion += ((VERSION_PATCH / 1000) << 12) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) ((VERSION_PATCH / 100) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) status = StopOC(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) state->drxd_state = DRXD_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) state->init_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) static int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) DRX_GetLockStatus(state, pLockStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) /*if (*pLockStatus&DRX_LOCK_MPEG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) if (*pLockStatus & DRX_LOCK_FEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) ConfigureMPEGOutput(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) /* Get status again, in case we have MPEG lock now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) /*DRX_GetLockStatus(state, pLockStatus); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) struct drxd_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) res = ReadIFAgc(state, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) *strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) *strength = 0xffff - (value << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) struct drxd_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) u32 lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) DRXD_status(state, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) /* No MPEG lock in V255 firmware, bug ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) if (lock & DRX_LOCK_MPEG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) if (lock & DRX_LOCK_FEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) if (lock & DRX_LOCK_FEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) if (lock & DRX_LOCK_DEMOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) static int drxd_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) struct drxd_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) return DRXD_init(state, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) static int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) struct drxd_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) if (state->config.disable_i2c_gate_ctrl == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) return DRX_ConfigureI2CBridge(state, onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) static int drxd_get_tune_settings(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) struct dvb_frontend_tune_settings *sets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) sets->min_delay_ms = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) sets->max_drift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) sets->step_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) *ber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) *snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) *ucblocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) static int drxd_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) struct drxd_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) ConfigureMPEGOutput(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) return drxd_config_i2c(fe, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) static int drxd_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) struct drxd_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) s32 off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) state->props = *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) DRX_Stop(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) return DRX_Start(state, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) static void drxd_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) struct drxd_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) static const struct dvb_frontend_ops drxd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .delsys = { SYS_DVBT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) .name = "Micronas DRXD DVB-T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) .frequency_min_hz = 47125 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .frequency_max_hz = 855250 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) .frequency_stepsize_hz = 166667,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) FE_CAN_QAM_16 | FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) FE_CAN_TRANSMISSION_MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) FE_CAN_GUARD_INTERVAL_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) .release = drxd_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) .init = drxd_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) .sleep = drxd_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) .set_frontend = drxd_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .get_tune_settings = drxd_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) .read_status = drxd_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) .read_ber = drxd_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) .read_signal_strength = drxd_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) .read_snr = drxd_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) .read_ucblocks = drxd_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) struct dvb_frontend *drxd_attach(const struct drxd_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) void *priv, struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) struct drxd_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) state->ops = drxd_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) state->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) state->config = *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) state->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) mutex_init(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) if (Read16(state, 0, NULL, 0) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) state->frontend.ops = drxd_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) ConfigureMPEGOutput(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) /* add few initialization to allow gate control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) CDRXD(state, state->config.IF ? state->config.IF : 36000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) InitHI(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) printk(KERN_ERR "drxd: not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) EXPORT_SYMBOL(drxd_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) MODULE_DESCRIPTION("DRXD driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) MODULE_AUTHOR("Micronas");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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