^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drxd_firm.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006-2007 Micronas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _DRXD_FIRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _DRXD_FIRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "drxd_map_firm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define VERSION_MAJOR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define VERSION_MINOR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define VERSION_PATCH 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DRXD_MAX_RETRIES (1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HI_I2C_DELAY 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HI_I2C_BRIDGE_DELAY 750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EQ_TD_TPS_PWR_QPSK 0x016a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EQ_TD_TPS_PWR_QAM16_ALPHA2 0x011E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EQ_TD_TPS_PWR_QAM16_ALPHA4 0x01CE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EQ_TD_TPS_PWR_QAM64_ALPHAN 0x019F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EQ_TD_TPS_PWR_QAM64_ALPHA1 0x019F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EQ_TD_TPS_PWR_QAM64_ALPHA2 0x00F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EQ_TD_TPS_PWR_QAM64_ALPHA4 0x014D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRXD_DEF_AG_PWD_CONSUMER 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRXD_DEF_AG_PWD_PRO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRXD_DEF_AG_AGC_SIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRXD_FE_CTRL_MAX 1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRXD_OSCDEV_DO_SCAN (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRXD_OSCDEV_DONT_SCAN (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRXD_OSCDEV_STEP (275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRXD_SCAN_TIMEOUT (650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IRLEN_COARSE_8K (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IRLEN_FINE_8K (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IRLEN_COARSE_2K (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IRLEN_FINE_2K (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DIFF_INVALID (511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DIFF_TARGET (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DIFF_MARGIN (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) extern u8 DRXD_InitAtomicRead[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) extern u8 DRXD_HiI2cPatch_1[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) extern u8 DRXD_HiI2cPatch_3[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) extern u8 DRXD_InitSC[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) extern u8 DRXD_ResetCEFR[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) extern u8 DRXD_InitFEA2_1[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern u8 DRXD_InitFEA2_2[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern u8 DRXD_InitCPA2[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern u8 DRXD_InitCEA2[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) extern u8 DRXD_InitEQA2[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) extern u8 DRXD_InitECA2[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) extern u8 DRXD_ResetECA2[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) extern u8 DRXD_ResetECRAM[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) extern u8 DRXD_A2_microcode[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) extern u32 DRXD_A2_microcode_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern u8 DRXD_InitFEB1_1[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) extern u8 DRXD_InitFEB1_2[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) extern u8 DRXD_InitCPB1[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) extern u8 DRXD_InitCEB1[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) extern u8 DRXD_InitEQB1[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern u8 DRXD_InitECB1[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) extern u8 DRXD_InitDiversityFront[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) extern u8 DRXD_InitDiversityEnd[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) extern u8 DRXD_DisableDiversity[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) extern u8 DRXD_StartDiversityFront[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) extern u8 DRXD_StartDiversityEnd[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) extern u8 DRXD_DiversityDelay8MHZ[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) extern u8 DRXD_DiversityDelay6MHZ[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) extern u8 DRXD_B1_microcode[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) extern u32 DRXD_B1_microcode_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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