^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drxd_firm.c : DRXD firmware tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006-2007 Micronas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* TODO: generate this file with a script from a settings file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Contains A2 firmware version: 1.4.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Contains B1 firmware version: 3.3.33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Contains settings from driver 1.4.23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "drxd_firm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ADDRESS(x) ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LENGTH(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Is written via block write, must be little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DATA16(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WRBLOCK(a, l) ADDRESS(a), LENGTH(l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WR16(a, d) ADDRESS(a), LENGTH(1), DATA16(d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define END_OF_TABLE 0xFF, 0xFF, 0xFF, 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* HI firmware patches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 DRXD_InitAtomicRead[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 0x26, 0x00, /* 0 -> ring.rdy; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 0x60, 0x04, /* r0rami.dt -> ring.xba; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 0x61, 0x04, /* r0rami.dt -> ring.xad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 0x40, 0x00, /* (long immediate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 0x64, 0x04, /* r0rami.dt -> ring.len; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 0x65, 0x04, /* r0rami.dt -> ring.ctl; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 0x26, 0x00, /* 0 -> ring.rdy; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 0x38, 0x00, /* 0 -> jumps.ad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Pins D0 and D1 of the parallel MPEG output can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) to set the I2C address of a device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HI_RST_FUNC_ADDR (HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* D0 Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 DRXD_HiI2cPatch_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 0x23, 0x00, /* &data -> ring.iad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0x24, 0x00, /* 0 -> ring.len; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0x26, 0x00, /* 0 -> ring.rdy; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0x42, 0x00, /* &data+1 -> w0ram.ad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0x63, 0x00, /* &data+1 -> ring.iad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0x26, 0x00, /* 0 -> ring.rdy; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0x26, 0x00, /* 0 -> ring.rdy; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0x23, 0x00, /* &data -> ring.iad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 0x26, 0x00, /* 0 -> ring.rdy; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0x42, 0x00, /* &data+1 -> w0ram.ad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0x0F, 0x04, /* r0ram.dt -> and.op; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0x1C, 0x06, /* reg0.dt -> and.tr; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0xCF, 0x04, /* and.rs -> add.op; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0xD0, 0x04, /* add.rs -> add.tr; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 0xC8, 0x04, /* add.rs -> reg0.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 0x01, 0x00, /* 0 -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 0x01, 0x00, /* 0 -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 0x01, 0x00, /* 0 -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0x01, 0x00, /* 0 -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0x01, 0x00, /* 0 -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Force quick and dirty reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) WR16(B_HI_CT_REG_COMM_STATE__A, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* D0,D1 Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 DRXD_HiI2cPatch_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x23, 0x00, /* &data -> ring.iad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0x24, 0x00, /* 0 -> ring.len; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x26, 0x00, /* 0 -> ring.rdy; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0x42, 0x00, /* &data+1 -> w0ram.ad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0x63, 0x00, /* &data+1 -> ring.iad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0x26, 0x00, /* 0 -> ring.rdy; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 0x26, 0x00, /* 0 -> ring.rdy; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 0x23, 0x00, /* &data -> ring.iad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0x26, 0x00, /* 0 -> ring.rdy; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 0x42, 0x00, /* &data+1 -> w0ram.ad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 0x0F, 0x04, /* r0ram.dt -> and.op; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0x1C, 0x06, /* reg0.dt -> and.tr; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 0xCF, 0x04, /* and.rs -> add.op; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0xD0, 0x04, /* add.rs -> add.tr; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0xC8, 0x04, /* add.rs -> reg0.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x01, 0x00, /* 0 -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0x01, 0x00, /* 0 -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 0x01, 0x00, /* 0 -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 0x01, 0x00, /* 0 -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 0x01, 0x00, /* 0 -> w0rami.dt; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Force quick and dirty reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) WR16(B_HI_CT_REG_COMM_STATE__A, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 DRXD_ResetCEFR[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) WRBLOCK(CE_REG_FR_TREAL00__A, 57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 0x52, 0x00, /* CE_REG_FR_TREAL00__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 0x00, 0x00, /* CE_REG_FR_TIMAG00__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0x52, 0x00, /* CE_REG_FR_TREAL01__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0x00, 0x00, /* CE_REG_FR_TIMAG01__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 0x52, 0x00, /* CE_REG_FR_TREAL02__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 0x00, 0x00, /* CE_REG_FR_TIMAG02__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 0x52, 0x00, /* CE_REG_FR_TREAL03__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 0x00, 0x00, /* CE_REG_FR_TIMAG03__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 0x52, 0x00, /* CE_REG_FR_TREAL04__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 0x00, 0x00, /* CE_REG_FR_TIMAG04__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 0x52, 0x00, /* CE_REG_FR_TREAL05__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 0x00, 0x00, /* CE_REG_FR_TIMAG05__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 0x52, 0x00, /* CE_REG_FR_TREAL06__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 0x00, 0x00, /* CE_REG_FR_TIMAG06__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 0x52, 0x00, /* CE_REG_FR_TREAL07__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 0x00, 0x00, /* CE_REG_FR_TIMAG07__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 0x52, 0x00, /* CE_REG_FR_TREAL08__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0x00, 0x00, /* CE_REG_FR_TIMAG08__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 0x52, 0x00, /* CE_REG_FR_TREAL09__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0x00, 0x00, /* CE_REG_FR_TIMAG09__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 0x52, 0x00, /* CE_REG_FR_TREAL10__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0x00, 0x00, /* CE_REG_FR_TIMAG10__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 0x52, 0x00, /* CE_REG_FR_TREAL11__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 0x00, 0x00, /* CE_REG_FR_TIMAG11__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 0x52, 0x00, /* CE_REG_FR_MID_TAP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 0x0B, 0x00, /* CE_REG_FR_SQS_G00__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 0x0B, 0x00, /* CE_REG_FR_SQS_G01__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 0x0B, 0x00, /* CE_REG_FR_SQS_G02__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0x0B, 0x00, /* CE_REG_FR_SQS_G03__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 0x0B, 0x00, /* CE_REG_FR_SQS_G04__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 0x0B, 0x00, /* CE_REG_FR_SQS_G05__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 0x0B, 0x00, /* CE_REG_FR_SQS_G06__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 0x0B, 0x00, /* CE_REG_FR_SQS_G07__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 0x0B, 0x00, /* CE_REG_FR_SQS_G08__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 0x0B, 0x00, /* CE_REG_FR_SQS_G09__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 0x0B, 0x00, /* CE_REG_FR_SQS_G10__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 0x0B, 0x00, /* CE_REG_FR_SQS_G11__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 0x0B, 0x00, /* CE_REG_FR_SQS_G12__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 0xFF, 0x01, /* CE_REG_FR_RIO_G00__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 0x90, 0x01, /* CE_REG_FR_RIO_G01__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 0x0B, 0x01, /* CE_REG_FR_RIO_G02__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 0xC8, 0x00, /* CE_REG_FR_RIO_G03__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 0xA0, 0x00, /* CE_REG_FR_RIO_G04__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 0x85, 0x00, /* CE_REG_FR_RIO_G05__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0x72, 0x00, /* CE_REG_FR_RIO_G06__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 0x64, 0x00, /* CE_REG_FR_RIO_G07__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 0x59, 0x00, /* CE_REG_FR_RIO_G08__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0x50, 0x00, /* CE_REG_FR_RIO_G09__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 0x49, 0x00, /* CE_REG_FR_RIO_G10__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0x10, 0x00, /* CE_REG_FR_MODE__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 0x78, 0x00, /* CE_REG_FR_SQS_TRH__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 0x00, 0x00, /* CE_REG_FR_RIO_GAIN__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 0x00, 0x02, /* CE_REG_FR_BYPASS__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 0x0D, 0x00, /* CE_REG_FR_PM_SET__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 0x07, 0x00, /* CE_REG_FR_ERR_SH__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 0x04, 0x00, /* CE_REG_FR_MAN_SH__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 0x06, 0x00, /* CE_REG_FR_TAP_SH__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 DRXD_InitFEA2_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) WRBLOCK(FE_AD_REG_PD__A, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0x00, 0x00, /* FE_AD_REG_PD__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 0x01, 0x00, /* FE_AD_REG_INVEXT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 0x00, 0x00, /* FE_AD_REG_CLKNEG__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 0x10, 0x00, /* FE_AG_REG_DCE_AUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0x10, 0x00, /* FE_AG_REG_DCE_RUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 0x0E, 0x00, /* FE_AG_REG_ACE_AUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0x00, 0x00, /* FE_AG_REG_ACE_RUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 0x04, 0x00, /* FE_AG_REG_EGC_FLA_RGN__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 0x1F, 0x00, /* FE_AG_REG_EGC_SLO_RGN__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0x00, 0x00, /* FE_AG_REG_EGC_JMP_PSN__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0x00, 0x00, /* FE_AG_REG_EGC_FLA_INC__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0x00, 0x00, /* FE_AG_REG_EGC_FLA_DEC__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0xFF, 0x01, /* FE_AG_REG_GC1_AGC_MAX__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 0x00, 0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) WRBLOCK(FE_AG_REG_IND_WIN__A, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0x00, 0x00, /* FE_AG_REG_IND_WIN__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 0x05, 0x00, /* FE_AG_REG_IND_THD_LOL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 0x0F, 0x00, /* FE_AG_REG_IND_THD_HIL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0x00, 0x00, /* FE_AG_REG_IND_DEL__A don't care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0x1E, 0x00, /* FE_AG_REG_IND_PD1_WRI__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0x0C, 0x00, /* FE_AG_REG_PDA_AUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0x00, 0x00, /* FE_AG_REG_PDA_RUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 0x00, 0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0x00, 0x00, /* FE_AG_REG_PDC_RUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 0x01, 0x00, /* FE_AG_REG_PDC_SET_LVL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 0x02, 0x00, /* FE_AG_REG_PDC_FLA_RGN__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0x00, 0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 0xFF, 0xFF, /* FE_AG_REG_PDC_FLA_STP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 0xFF, 0xFF, /* FE_AG_REG_PDC_SLO_STP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0x00, 0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 0x00, 0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0x02, 0x00, /* FE_AG_REG_PDC_MAX__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 0x0C, 0x00, /* FE_AG_REG_TGA_AUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0x00, 0x00, /* FE_AG_REG_TGA_RUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 0x00, 0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0x00, 0x00, /* FE_AG_REG_TGC_RUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 0x22, 0x00, /* FE_AG_REG_TGC_SET_LVL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 0x15, 0x00, /* FE_AG_REG_TGC_FLA_RGN__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0x00, 0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 0x01, 0x00, /* FE_AG_REG_TGC_FLA_STP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 0x0A, 0x00, /* FE_AG_REG_TGC_SLO_STP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 0x00, 0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x10, 0x00, /* FE_AG_REG_FGA_AUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0x10, 0x00, /* FE_AG_REG_FGA_RUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0x00, 0x00, /* FE_AG_REG_BGC_FGC_WRI__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x00, 0x00, /* FE_AG_REG_BGC_CGC_WRI__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) WRBLOCK(FE_FD_REG_SCL__A, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0x05, 0x00, /* FE_FD_REG_SCL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0x03, 0x00, /* FE_FD_REG_MAX_LEV__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 0x05, 0x00, /* FE_FD_REG_NR__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) WRBLOCK(FE_CF_REG_SCL__A, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0x16, 0x00, /* FE_CF_REG_SCL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 0x04, 0x00, /* FE_CF_REG_MAX_LEV__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0x06, 0x00, /* FE_CF_REG_NR__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0x00, 0x00, /* FE_CF_REG_IMP_VAL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0x01, 0x00, /* FE_CF_REG_MEAS_VAL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) WRBLOCK(FE_CU_REG_FRM_CNT_RST__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 0x00, 0x08, /* FE_CU_REG_FRM_CNT_RST__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0x00, 0x00, /* FE_CU_REG_FRM_CNT_STR__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* with PGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0004), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* without PGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0001), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 DRXD_InitFEA2_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) WR16(FE_AG_REG_FGM_WRI__A, 48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Activate measurement, activate scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) WR16(FE_FD_REG_MEAS_VAL__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) WR16(FE_CU_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) WR16(FE_CF_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) WR16(FE_IF_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) WR16(FE_FD_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) WR16(FE_FS_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) WR16(FE_AD_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) WR16(FE_AG_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) WR16(FE_AG_REG_AG_MODE_LOP__A, 0x895E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u8 DRXD_InitFEB1_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) WR16(B_FE_AD_REG_PD__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) WR16(B_FE_AG_REG_BGC_CGC_WRI__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) WR16(B_FE_AG_REG_AG_MODE_LOP__A, 0x000a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) WR16(B_FE_AG_REG_IND_PD1_WRI__A, 35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) WR16(B_FE_AG_REG_IND_WIN__A, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) WR16(B_FE_AG_REG_IND_THD_LOL__A, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) WR16(B_FE_AG_REG_IND_THD_HIL__A, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) WR16(B_FE_CF_REG_IMP_VAL__A, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* with PGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* without PGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* WR16(B_FE_AG_REG_AG_PGA_MODE__A ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 DRXD_InitFEB1_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) WR16(B_FE_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* RF-AGC setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) WR16(B_FE_AG_REG_PDA_AUR_CNT__A, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) WR16(B_FE_AG_REG_PDC_SET_LVL__A, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) WR16(B_FE_AG_REG_PDC_FLA_RGN__A, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) WR16(B_FE_AG_REG_PDC_FLA_STP__A, 0xFFFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) WR16(B_FE_AG_REG_PDC_SLO_STP__A, 0xFFFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) WR16(B_FE_AG_REG_PDC_MAX__A, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) WR16(B_FE_AG_REG_TGA_AUR_CNT__A, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) WR16(B_FE_AG_REG_TGC_SET_LVL__A, 0x22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) WR16(B_FE_AG_REG_TGC_FLA_RGN__A, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) WR16(B_FE_AG_REG_TGC_FLA_STP__A, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) WR16(B_FE_AG_REG_TGC_SLO_STP__A, 0x0A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) WR16(B_FE_CU_REG_DIV_NFC_CLP__A, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) WR16(B_FE_CU_REG_CTR_NFC_OCR__A, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) WR16(B_FE_CU_REG_CTR_NFC_ICR__A, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 DRXD_InitCPA2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) WRBLOCK(CP_REG_RT_ANG_INC0__A, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x00, 0x00, /* CP_REG_RT_ANG_INC0__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 0x00, 0x00, /* CP_REG_RT_ANG_INC1__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0x03, 0x00, /* CP_REG_RT_DETECT_ENA__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 0x03, 0x00, /* CP_REG_RT_DETECT_TRH__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) WRBLOCK(CP_REG_AC_NEXP_OFFS__A, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0x32, 0x00, /* CP_REG_AC_NEXP_OFFS__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 0x62, 0x00, /* CP_REG_AC_AVER_POW__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 0x82, 0x00, /* CP_REG_AC_MAX_POW__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 0x26, 0x00, /* CP_REG_AC_WEIGHT_MAN__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0x0F, 0x00, /* CP_REG_AC_WEIGHT_EXP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) WRBLOCK(CP_REG_AC_AMP_MODE__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 0x02, 0x00, /* CP_REG_AC_AMP_MODE__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 0x01, 0x00, /* CP_REG_AC_AMP_FIX__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) WR16(CP_REG_INTERVAL__A, 0x0005),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) WR16(CP_REG_RT_EXP_MARG__A, 0x0004),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) WR16(CP_REG_AC_ANG_MODE__A, 0x0003),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) WR16(CP_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u8 DRXD_InitCPB1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) WR16(B_CP_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u8 DRXD_InitCEA2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) WRBLOCK(CE_REG_AVG_POW__A, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0x62, 0x00, /* CE_REG_AVG_POW__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 0x78, 0x00, /* CE_REG_MAX_POW__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x62, 0x00, /* CE_REG_ATT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 0x17, 0x00, /* CE_REG_NRED__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) WRBLOCK(CE_REG_NE_ERR_SELECT__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0x07, 0x00, /* CE_REG_NE_ERR_SELECT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 0xEB, 0xFF, /* CE_REG_NE_TD_CAL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) WRBLOCK(CE_REG_NE_MIXAVG__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 0x06, 0x00, /* CE_REG_NE_MIXAVG__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 0x00, 0x00, /* CE_REG_NE_NUPD_OFS__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) WRBLOCK(CE_REG_PE_NEXP_OFFS__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 0x00, 0x00, /* CE_REG_PE_NEXP_OFFS__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 0x00, 0x00, /* CE_REG_PE_TIMESHIFT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) WRBLOCK(CE_REG_TP_A0_TAP_NEW__A, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 0x00, 0x01, /* CE_REG_TP_A0_TAP_NEW__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 0x01, 0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 0x0E, 0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) WRBLOCK(CE_REG_TP_A1_TAP_NEW__A, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 0x00, 0x00, /* CE_REG_TP_A1_TAP_NEW__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 0x01, 0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 0x0A, 0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) WRBLOCK(CE_REG_FI_SHT_INCR__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 0x12, 0x00, /* CE_REG_FI_SHT_INCR__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 0x0C, 0x00, /* CE_REG_FI_EXP_NORM__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) WRBLOCK(CE_REG_IR_INPUTSEL__A, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 0x00, 0x00, /* CE_REG_IR_INPUTSEL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 0x00, 0x00, /* CE_REG_IR_STARTPOS__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 0xFF, 0x00, /* CE_REG_IR_NEXP_THRES__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u8 DRXD_InitCEB1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) WR16(B_CE_REG_FR_PM_SET__A, 0x000D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u8 DRXD_InitEQA2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 0x06, 0x00, /* EQ_REG_OT_CSI_STEP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 0x02, 0x00, /* EQ_REG_OT_CSI_OFFSET__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) WR16(EQ_REG_SN_OFFSET__A, (u16) (-7)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) WR16(EQ_REG_RC_SEL_CAR__A, 0x0002),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) WR16(EQ_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u8 DRXD_InitEQB1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) WR16(B_EQ_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u8 DRXD_ResetECRAM[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Reset packet sync bytes in EC_VD ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Reset packet sync bytes in EC_RS ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) WR16(EC_RS_EC_RAM__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) WR16(EC_RS_EC_RAM__A + 204, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u8 DRXD_InitECA2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) WRBLOCK(EC_SB_REG_CSI_HI__A, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 0x01, 0x00, /* EC_SB_REG_SMB_TGL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 0x7F, 0x00, /* EC_SB_REG_SNR_HI__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 0x7F, 0x00, /* EC_SB_REG_SNR_MID__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 0x7F, 0x00, /* EC_SB_REG_SNR_LO__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) WRBLOCK(EC_RS_REG_REQ_PCK_CNT__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 0x00, 0x10, /* EC_RS_REG_REQ_PCK_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) WR16(EC_SB_REG_CSI_OFS__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) WR16(EC_VD_REG_FORCE__A, 0x0002),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) WR16(EC_VD_REG_REQ_SMB_CNT__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) WR16(EC_VD_REG_RLK_ENA__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) WR16(EC_OD_REG_SYNC__A, 0x0664),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Output zero on monitorbus pads, power saving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) WR16(EC_OC_REG_OCR_MON_UOS__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) WR16(EC_OC_REG_OCR_MON_WRI__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) EC_OC_REG_OCR_MON_WRI_INIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* CHK_ERROR(ResetECRAM(demod)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Reset packet sync bytes in EC_VD ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Reset packet sync bytes in EC_RS ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) WR16(EC_RS_EC_RAM__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) WR16(EC_RS_EC_RAM__A + 204, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) WR16(EC_SB_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) WR16(EC_VD_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) WR16(EC_RS_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u8 DRXD_InitECB1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) WR16(B_EC_SB_REG_CSI_LO__A, 0x000c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) WR16(B_EC_SB_REG_CSI_HI__A, 0x0018),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) WR16(B_EC_SB_REG_SNR_HI__A, 0x007f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) WR16(B_EC_SB_REG_SNR_MID__A, 0x007f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) WR16(B_EC_SB_REG_SNR_LO__A, 0x007f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) WR16(B_EC_OC_REG_DTO_CLKMODE__A, 0x0002),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) WR16(B_EC_OC_REG_DTO_PER__A, 0x0006),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) WR16(B_EC_OC_REG_DTO_BUR__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) WR16(B_EC_OC_REG_RCR_CLKMODE__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) WR16(B_EC_OC_REG_RCN_GAI_LVL__A, 0x000D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) WR16(B_EC_OC_REG_OC_MPG_SIO__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Needed because shadow registers do not have correct default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) WR16(B_EC_OC_REG_RCN_CST_LOP__A, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) WR16(B_EC_OC_REG_RCN_CST_HIP__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) WR16(B_EC_OC_REG_RCN_CRA_LOP__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) WR16(B_EC_OC_REG_RCN_CRA_HIP__A, 0x00C0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) WR16(B_EC_OC_REG_RCN_CLP_LOP__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) WR16(B_EC_OC_REG_RCN_CLP_HIP__A, 0x00C0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) WR16(B_EC_OC_REG_DTO_INC_LOP__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) WR16(B_EC_OC_REG_DTO_INC_HIP__A, 0x00C0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) WR16(B_EC_OD_REG_SYNC__A, 0x0664),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) WR16(B_EC_RS_REG_REQ_PCK_CNT__A, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* CHK_ERROR(ResetECRAM(demod)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Reset packet sync bytes in EC_VD ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Reset packet sync bytes in EC_RS ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) WR16(EC_RS_EC_RAM__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) WR16(EC_RS_EC_RAM__A + 204, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) WR16(B_EC_SB_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) WR16(B_EC_VD_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) WR16(B_EC_OD_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) WR16(B_EC_RS_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u8 DRXD_ResetECA2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) WR16(EC_OC_REG_COMM_EXEC__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) WR16(EC_OD_REG_COMM_EXEC__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) WR16(EC_OD_REG_SYNC__A, 0x0664),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Output zero on monitorbus pads, power saving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) WR16(EC_OC_REG_OCR_MON_UOS__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) WR16(EC_OC_REG_OCR_MON_WRI__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) EC_OC_REG_OCR_MON_WRI_INIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* CHK_ERROR(ResetECRAM(demod)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* Reset packet sync bytes in EC_VD ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Reset packet sync bytes in EC_RS ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) WR16(EC_RS_EC_RAM__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) WR16(EC_RS_EC_RAM__A + 204, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u8 DRXD_InitSC[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) WR16(SC_COMM_EXEC__A, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) WR16(SC_COMM_STATE__A, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #ifdef COMPILE_FOR_QT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* SC is not started, this is done in SetChannels() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* Diversity settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u8 DRXD_InitDiversityFront[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Start demod ********* RF in , diversity out **************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) B_SC_RA_RAM_CONFIG_FREQSCAN__M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) WR16(B_SC_RA_RAM_LC_ABS_2K__A, 0x7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) WR16(B_SC_RA_RAM_LC_ABS_8K__A, 0x7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) WR16(B_CC_REG_DIVERSITY__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* 0x2a ), *//* CE to PASS mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u8 DRXD_InitDiversityEnd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* End demod *********** combining RF in and diversity in, MPEG TS out **** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* disable near/far; switch on timing slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) B_SC_RA_RAM_CONFIG_FREQSCAN__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) B_SC_RA_RAM_CONFIG_SLAVE__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* MV from CtrlDiversity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #ifdef DRXDDIV_SRMM_SLAVING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) WR16(SC_RA_RAM_LC_ABS_2K__A, 0x3c7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) WR16(SC_RA_RAM_LC_ABS_8K__A, 0x3c7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) WR16(SC_RA_RAM_LC_ABS_2K__A, 0x7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) WR16(SC_RA_RAM_LC_ABS_8K__A, 0x7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) WR16(B_CC_REG_DIVERSITY__A, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u8 DRXD_DisableDiversity[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) WR16(B_CC_REG_DIVERSITY__A, 0x0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT), /* combining disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u8 DRXD_StartDiversityFront[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* Start demod, RF in and diversity out, no combining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) WR16(B_FE_AD_REG_FDB_IN__A, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) WR16(B_FE_AD_REG_INVEXT__A, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) WR16(B_EQ_REG_COMM_MB__A, 0x12), /* EQ to MB out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u8 DRXD_StartDiversityEnd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* End demod, combining RF in and diversity in, MPEG TS out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) WR16(B_CP_REG_BR_STR_DEL__A, 10), /* apparently no mb delay matching is best */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) u8 DRXD_DiversityDelay8MHZ[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 800 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4800 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 4000 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u8 DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 900 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 600 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4500 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 3500 - 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) END_OF_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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