^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) modification, are permitted provided that the following conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Redistributions of source code must retain the above copyright notice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Redistributions in binary form must reproduce the above copyright notice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) this list of conditions and the following disclaimer in the documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Neither the name of Trident Microsystems nor Hauppauge Computer Works
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) nor the names of its contributors may be used to endorse or promote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) products derived from this software without specific prior written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DRXJ specific header file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #ifndef __DRXJ_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define __DRXJ_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*-------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) INCLUDES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) -------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "drx_driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "drx_dap_fasi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Check DRX-J specific dap condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Multi master mode and short addr format only will not work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RMW, CRC reset, broadcast and switching back to single master mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) cannot be done with short addr only in multi master mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #if ((DRXDAP_SINGLE_MASTER == 0) && (DRXDAPFASI_LONG_ADDR_ALLOWED == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #error "Multi master mode and short addressing only is an illegal combination"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *; /* Generate a fatal compiler error to make sure it stops here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) this is necessary because not all compilers stop after a #error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*-------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) TYPEDEFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) -------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*== code support ============================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*== SCU cmd if =============================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct drxjscu_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*< Command number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u16 parameter_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*< Data length in byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u16 result_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*< result length in byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 *parameter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*< General purpous param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u16 *result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*< General purpous param */};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*== CTRL CFG related data structures ========================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* extra intermediate lock state for VSB,QAM,NTSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* OOB lock states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Intermediate powermodes for DRXJ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* supstition for GPIO FNC mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define APP_O (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*#define DRX_CTRL_BASE (0x0000)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DRXJ_CTRL_CFG_BASE (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum drxj_cfg_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DRXJ_CFG_AGC_IF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DRXJ_CFG_AGC_INTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DRXJ_CFG_PRE_SAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DRXJ_CFG_AFE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DRXJ_CFG_SYMBOL_CLK_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DRXJ_CFG_ACCUM_CR_RS_CW_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DRXJ_CFG_FEC_MERS_SEQ_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DRXJ_CFG_OOB_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DRXJ_CFG_SMART_ANT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DRXJ_CFG_OOB_PRE_SAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DRXJ_CFG_VSB_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DRXJ_CFG_RESET_PACKET_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* ATV (FM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DRXJ_CFG_ATV_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DRXJ_CFG_ATV_EQU_COEF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DRXJ_CFG_MPEG_OUTPUT_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DRXJ_CFG_HW_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DRXJ_CFG_OOB_LO_POW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DRXJ_CFG_MAX /* dummy, never to be used */};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * /struct enum drxj_cfg_smart_ant_io * smart antenna i/o.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) enum drxj_cfg_smart_ant_io {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DRXJ_SMT_ANT_OUTPUT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DRXJ_SMT_ANT_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * /struct struct drxj_cfg_smart_ant * Set smart antenna.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct drxj_cfg_smart_ant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) enum drxj_cfg_smart_ant_io io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u16 ctrl_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * /struct DRXJAGCSTATUS_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * AGC status information from the DRXJ-IQM-AF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct drxj_agc_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u16 IFAGC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u16 RFAGC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u16 digital_agc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * /struct enum drxj_agc_ctrl_mode * Available AGCs modes in the DRXJ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) enum drxj_agc_ctrl_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DRX_AGC_CTRL_AUTO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DRX_AGC_CTRL_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DRX_AGC_CTRL_OFF};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * /struct struct drxj_cfg_agc * Generic interface for all AGCs present on the DRXJ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct drxj_cfg_agc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) enum drx_standard standard; /* standard for which these settings apply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) enum drxj_agc_ctrl_mode ctrl_mode; /* off, user, auto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u16 output_level; /* range dependent on AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u16 min_output_level; /* range dependent on AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u16 max_output_level; /* range dependent on AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u16 speed; /* range dependent on AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u16 top; /* rf-agc take over point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u16 cut_off_current; /* rf-agc is accelerated if output current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) is below cut-off current */};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* DRXJ_CFG_PRE_SAW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * /struct struct drxj_cfg_pre_saw * Interface to configure pre SAW sense.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct drxj_cfg_pre_saw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) enum drx_standard standard; /* standard to which these settings apply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u16 reference; /* pre SAW reference value, range 0 .. 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) bool use_pre_saw; /* true algorithms must use pre SAW sense */};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* DRXJ_CFG_AFE_GAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * /struct struct drxj_cfg_afe_gain * Interface to configure gain of AFE (LNA + PGA).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct drxj_cfg_afe_gain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) enum drx_standard standard; /* standard to which these settings apply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * /struct drxjrs_errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Available failure information in DRXJ_FEC_RS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Container for errors that are received in the most recently finished measurement period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct drxjrs_errors {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u16 nr_bit_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*< no of pre RS bit errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u16 nr_symbol_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*< no of pre RS symbol errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u16 nr_packet_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*< no of pre RS packet errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u16 nr_failures;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*< no of post RS failures to decode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u16 nr_snc_par_fail_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*< no of post RS bit erros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * /struct struct drxj_cfg_vsb_misc * symbol error rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct drxj_cfg_vsb_misc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 symb_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*< symbol error rate sps */};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) enum drxj_mpeg_start_width {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) DRXJ_MPEG_START_WIDTH_1CLKCYC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) DRXJ_MPEG_START_WIDTH_8CLKCYC};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) enum drxj_mpeg_output_clock_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * /struct DRXJCfgMisc_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * Change TEI bit of MPEG output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * reverse MPEG output bit order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * set MPEG output clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct drxj_cfg_mpeg_output_misc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) bool disable_tei_handling; /*< if true pass (not change) TEI bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) bool bit_reverse_mpeg_outout; /*< if true, parallel: msb on MD0; serial: lsb out first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*< set MPEG output clock rate that overwirtes the derived one from symbol rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) enum drxj_mpeg_start_width mpeg_start_width; /*< set MPEG output start width */};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * /enum enum drxj_xtal_freq * Supported external crystal reference frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) enum drxj_xtal_freq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) DRXJ_XTAL_FREQ_RSVD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DRXJ_XTAL_FREQ_27MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DRXJ_XTAL_FREQ_20P25MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DRXJ_XTAL_FREQ_4MHZ};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * /enum enum drxj_xtal_freq * Supported external crystal reference frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) enum drxji2c_speed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DRXJ_I2C_SPEED_400KBPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DRXJ_I2C_SPEED_100KBPS};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * /struct struct drxj_cfg_hw_cfg * Get hw configuration, such as crystal reference frequency, I2C speed, etc...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct drxj_cfg_hw_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) enum drxj_xtal_freq xtal_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*< crystal reference frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) enum drxji2c_speed i2c_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*< 100 or 400 kbps */};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * DRXJ_CFG_ATV_MISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct drxj_cfg_atv_misc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) s16 peak_filter; /* -8 .. 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u16 noise_filter; /* 0 .. 15 */};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * struct drxj_cfg_oob_misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define DRXJ_OOB_STATE_RESET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DRXJ_OOB_STATE_AGN_HUNT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DRXJ_OOB_STATE_DGN_HUNT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DRXJ_OOB_STATE_AGC_HUNT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DRXJ_OOB_STATE_FRQ_HUNT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DRXJ_OOB_STATE_PHA_HUNT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DRXJ_OOB_STATE_TIM_HUNT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DRXJ_OOB_STATE_EQU_HUNT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DRXJ_OOB_STATE_EQT_HUNT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DRXJ_OOB_STATE_SYNC 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct drxj_cfg_oob_misc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct drxj_agc_status agc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) bool eq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) bool sym_timing_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) bool phase_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) bool freq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) bool dig_gain_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) bool ana_gain_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u8 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Index of in array of coef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) enum drxj_cfg_oob_lo_power {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) DRXJ_OOB_LO_POW_MINUS0DB = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DRXJ_OOB_LO_POW_MINUS5DB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) DRXJ_OOB_LO_POW_MINUS10DB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) DRXJ_OOB_LO_POW_MINUS15DB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) DRXJ_OOB_LO_POW_MAX};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * DRXJ_CFG_ATV_EQU_COEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct drxj_cfg_atv_equ_coef {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) s16 coef0; /* -256 .. 255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) s16 coef1; /* -256 .. 255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) s16 coef2; /* -256 .. 255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) s16 coef3; /* -256 .. 255 */};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Index of in array of coef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) enum drxj_coef_array_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) DRXJ_COEF_IDX_MN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) DRXJ_COEF_IDX_FM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) DRXJ_COEF_IDX_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) DRXJ_COEF_IDX_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) DRXJ_COEF_IDX_BG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) DRXJ_COEF_IDX_DK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DRXJ_COEF_IDX_I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DRXJ_COEF_IDX_MAX};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * DRXJ_CFG_ATV_OUTPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * /enum DRXJAttenuation_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Attenuation setting for SIF AGC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) enum drxjsif_attenuation {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) DRXJ_SIF_ATTENUATION_0DB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) DRXJ_SIF_ATTENUATION_3DB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DRXJ_SIF_ATTENUATION_6DB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DRXJ_SIF_ATTENUATION_9DB};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * /struct struct drxj_cfg_atv_output * SIF attenuation setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct drxj_cfg_atv_output {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) bool enable_cvbs_output; /* true= enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) bool enable_sif_output; /* true= enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) enum drxjsif_attenuation sif_attenuation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DRXJ_CFG_ATV_AGC_STATUS (get only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* TODO : AFE interface not yet finished, subject to change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct drxj_cfg_atv_agc_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u16 rf_agc_gain; /* 0 .. 877 uA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u16 if_agc_gain; /* 0 .. 877 uA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) s16 video_agc_gain; /* -75 .. 1972 in 0.1 dB steps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) s16 audio_agc_gain; /* -4 .. 1020 in 0.1 dB steps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u16 rf_agc_loop_gain; /* 0 .. 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u16 if_agc_loop_gain; /* 0 .. 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u16 video_agc_loop_gain; /* 0 .. 7 */};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*== CTRL related data structures ============================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* NONE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*========================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * /struct struct drxj_data * DRXJ specific attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * Global data container for DRXJ specific data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct drxj_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* device capabilities (determined during drx_open()) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) bool has_lna; /*< true if LNA (aka PGA) present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) bool has_oob; /*< true if OOB supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) bool has_ntsc; /*< true if NTSC supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) bool has_btsc; /*< true if BTSC supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) bool has_smatx; /*< true if mat_tx is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bool has_smarx; /*< true if mat_rx is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) bool has_gpio; /*< true if GPIO is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) bool has_irqn; /*< true if IRQN is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* A1/A2/A... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u8 mfx; /*< metal fix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* tuner settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) bool mirror_freq_spect_oob;/*< tuner inversion (true = tuner mirrors the signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* standard/channel settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) enum drx_standard standard; /*< current standard information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) enum drx_modulation constellation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*< current constellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) s32 frequency; /*< center signal frequency in KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) enum drx_bandwidth curr_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*< current channel bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) enum drx_mirror mirror; /*< current channel mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* signal quality information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 fec_bits_desired; /*< BER accounting period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u16 fec_vd_plen; /*< no of trellis symbols: VD SER measurement period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u16 qam_vd_prescale; /*< Viterbi Measurement Prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u16 qam_vd_period; /*< Viterbi Measurement period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u16 fec_rs_plen; /*< defines RS BER measurement period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u16 fec_rs_prescale; /*< ReedSolomon Measurement Prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u16 fec_rs_period; /*< ReedSolomon Measurement period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) bool reset_pkt_err_acc; /*< Set a flag to reset accumulated packet error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u16 pkt_err_acc_start; /*< Set a flag to reset accumulated packet error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* HI configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u16 hi_cfg_timing_div; /*< HI Configure() parameter 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u16 hi_cfg_bridge_delay; /*< HI Configure() parameter 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u16 hi_cfg_wake_up_key; /*< HI Configure() parameter 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u16 hi_cfg_ctrl; /*< HI Configure() parameter 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u16 hi_cfg_transmit; /*< HI Configure() parameter 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* UIO configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) enum drxuio_mode uio_sma_rx_mode;/*< current mode of SmaRx pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) enum drxuio_mode uio_sma_tx_mode;/*< current mode of SmaTx pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) enum drxuio_mode uio_gpio_mode; /*< current mode of ASEL pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) enum drxuio_mode uio_irqn_mode; /*< current mode of IRQN pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* IQM fs frequecy shift and inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 iqm_fs_rate_ofs; /*< frequency shifter setting after setchannel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) bool pos_image; /*< True: positive image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* IQM RC frequecy shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u32 iqm_rc_rate_ofs; /*< frequency shifter setting after setchannel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* ATV configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 atv_cfg_changed_flags; /*< flag: flags cfg changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU0__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU1__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU2__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU3__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bool phase_correction_bypass;/*< flag: true=bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) s16 atv_top_vid_peak; /*< shadow of ATV_TOP_VID_PEAK__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u16 atv_top_noise_th; /*< shadow of ATV_TOP_NOISE_TH__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) bool enable_cvbs_output; /*< flag CVBS output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) bool enable_sif_output; /*< flag SIF output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) enum drxjsif_attenuation sif_attenuation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*< current SIF att setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Agc configuration for QAM and VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct drxj_cfg_agc qam_rf_agc_cfg; /*< qam RF AGC config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct drxj_cfg_agc qam_if_agc_cfg; /*< qam IF AGC config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct drxj_cfg_agc vsb_rf_agc_cfg; /*< vsb RF AGC config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct drxj_cfg_agc vsb_if_agc_cfg; /*< vsb IF AGC config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* PGA gain configuration for QAM and VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u16 qam_pga_cfg; /*< qam PGA config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u16 vsb_pga_cfg; /*< vsb PGA config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Pre SAW configuration for QAM and VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct drxj_cfg_pre_saw qam_pre_saw_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*< qam pre SAW config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct drxj_cfg_pre_saw vsb_pre_saw_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*< qam pre SAW config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Version information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) char v_text[2][12]; /*< allocated text versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct drx_version v_version[2]; /*< allocated versions structs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct drx_version_list v_list_elements[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*< allocated version list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* smart antenna configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) bool smart_ant_inverted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Tracking filter setting for OOB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u16 oob_trk_filter_cfg[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) bool oob_power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* MPEG static bitrate setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 mpeg_ts_static_bitrate; /*< bitrate static MPEG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) bool disable_te_ihandling; /*< MPEG TS TEI handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) bool bit_reverse_mpeg_outout;/*< MPEG output bit order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*< MPEG output clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) enum drxj_mpeg_start_width mpeg_start_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /*< MPEG Start width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Pre SAW & Agc configuration for ATV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct drxj_cfg_pre_saw atv_pre_saw_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /*< atv pre SAW config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct drxj_cfg_agc atv_rf_agc_cfg; /*< atv RF AGC config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct drxj_cfg_agc atv_if_agc_cfg; /*< atv IF AGC config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u16 atv_pga_cfg; /*< atv pga config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 curr_symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* pin-safe mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) bool pdr_safe_mode; /*< PDR safe mode activated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u16 pdr_safe_restore_val_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u16 pdr_safe_restore_val_v_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u16 pdr_safe_restore_val_sma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u16 pdr_safe_restore_val_sma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* OOB pre-saw value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u16 oob_pre_saw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) enum drxj_cfg_oob_lo_power oob_lo_pow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct drx_aud_data aud_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*< audio storage */};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*-------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) Access MACROS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) -------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * \brief Compilable references to attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * \param d pointer to demod instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * Used as main reference to an attribute field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * Can be used by both macro implementation and function implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * These macros are defined to avoid duplication of code in macro and function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * definitions that handle access of demod common or extended attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define DRXJ_ATTR_BTSC_DETECT(d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) (((struct drxj_data *)(d)->my_ext_attr)->aud_data.btsc_detect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /*-------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) DEFINES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) -------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * \def DRXJ_NTSC_CARRIER_FREQ_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * \brief Offset from picture carrier to centre frequency in kHz, in RF domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * For NTSC standard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * NTSC channels are listed by their picture carrier frequency (Fpc).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * In case the tuner module is not used the DRX-J requires that the tuner is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * tuned to the centre frequency of the channel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * \brief Offset from picture carrier to centre frequency in kHz, in RF domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * For PAL/SECAM - BG standard. This define is needed in case the tuner module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * The DRX-J requires that the tuner is tuned to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * In case the tuner module is used the drxdriver takes care of this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * In case the tuner module is NOT used the application programmer must take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * care of this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * \brief Offset from picture carrier to centre frequency in kHz, in RF domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * The DRX-J requires that the tuner is tuned to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * In case the tuner module is used the drxdriver takes care of this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * In case the tuner module is NOT used the application programmer must take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * care of this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * \brief Offset from picture carrier to centre frequency in kHz, in RF domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * For PAL/SECAM - LP standard. This define is needed in case the tuner module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * The DRX-J requires that the tuner is tuned to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * In case the tuner module is used the drxdriver takes care of this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * In case the tuner module is NOT used the application programmer must take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * care of this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * \def DRXJ_FM_CARRIER_FREQ_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * \brief Offset from sound carrier to centre frequency in kHz, in RF domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * For FM standard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * FM channels are listed by their sound carrier frequency (Fsc).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * In case the tuner module is not used the DRX-J requires that the tuner is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * tuned to the Ffm frequency of the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define DRXJ_FM_CARRIER_FREQ_OFFSET ((s32)(-3000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Revision types -------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define DRXJ_TYPE_ID (0x3946000DUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Macros ---------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Convert OOB lock status to string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define DRXJ_STR_OOB_LOCKSTATUS(x) ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) (x == DRX_NEVER_LOCK) ? "Never" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) (x == DRX_NOT_LOCKED) ? "No" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) (x == DRX_LOCKED) ? "Locked" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) (x == DRX_LOCK_STATE_1) ? "AGC lock" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) (x == DRX_LOCK_STATE_2) ? "sync lock" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) "(Invalid)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #endif /* __DRXJ_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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