^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) modification, are permitted provided that the following conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Redistributions of source code must retain the above copyright notice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Redistributions in binary form must reproduce the above copyright notice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) this list of conditions and the following disclaimer in the documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Neither the name of Trident Microsystems nor Hauppauge Computer Works
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) nor the names of its contributors may be used to endorse or promote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) products derived from this software without specific prior written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DRXJ specific implementation of DRX driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) The Linux DVB Driver for Micronas DRX39xx family (drx3933j) was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) INCLUDE FILES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include "drx39xxj.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include "drxj.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include "drxj_map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*=== DEFINES ================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * \brief Maximum u32 value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #ifndef MAX_U32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MAX_U32 ((u32) (0xFFFFFFFFL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Customer configurable hardware settings, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #ifndef OOB_CRX_DRIVE_STRENGTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OOB_CRX_DRIVE_STRENGTH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #ifndef OOB_DRX_DRIVE_STRENGTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OOB_DRX_DRIVE_STRENGTH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*** START DJCOMBO patches to DRXJ registermap constants *********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*** registermap 200706071303 from drxj **************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ATV_TOP_CR_AMP_TH_FM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ATV_TOP_CR_AMP_TH_L 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ATV_TOP_CR_AMP_TH_LP 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ATV_TOP_CR_AMP_TH_BG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ATV_TOP_CR_AMP_TH_DK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ATV_TOP_CR_AMP_TH_I 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ATV_TOP_CR_CONT_CR_D_MN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ATV_TOP_CR_CONT_CR_D_FM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ATV_TOP_CR_CONT_CR_D_L 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ATV_TOP_CR_CONT_CR_D_LP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ATV_TOP_CR_CONT_CR_D_BG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ATV_TOP_CR_CONT_CR_D_DK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ATV_TOP_CR_CONT_CR_D_I 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ATV_TOP_CR_CONT_CR_I_MN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ATV_TOP_CR_CONT_CR_I_FM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ATV_TOP_CR_CONT_CR_I_L 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ATV_TOP_CR_CONT_CR_I_LP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ATV_TOP_CR_CONT_CR_I_BG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ATV_TOP_CR_CONT_CR_I_DK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ATV_TOP_CR_CONT_CR_I_I 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ATV_TOP_CR_CONT_CR_P_MN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ATV_TOP_CR_CONT_CR_P_FM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ATV_TOP_CR_CONT_CR_P_L 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ATV_TOP_CR_CONT_CR_P_LP 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ATV_TOP_CR_CONT_CR_P_BG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ATV_TOP_CR_CONT_CR_P_DK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ATV_TOP_CR_CONT_CR_P_I 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ATV_TOP_CR_OVM_TH_MN 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ATV_TOP_CR_OVM_TH_FM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ATV_TOP_CR_OVM_TH_L 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ATV_TOP_CR_OVM_TH_LP 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ATV_TOP_CR_OVM_TH_BG 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ATV_TOP_CR_OVM_TH_DK 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ATV_TOP_CR_OVM_TH_I 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ATV_TOP_EQU0_EQU_C0_FM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ATV_TOP_EQU0_EQU_C0_L 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ATV_TOP_EQU0_EQU_C0_LP 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ATV_TOP_EQU0_EQU_C0_BG 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ATV_TOP_EQU0_EQU_C0_DK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ATV_TOP_EQU0_EQU_C0_I 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ATV_TOP_EQU1_EQU_C1_FM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ATV_TOP_EQU1_EQU_C1_L 0x1F6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ATV_TOP_EQU1_EQU_C1_LP 0x1F6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ATV_TOP_EQU1_EQU_C1_BG 0x197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ATV_TOP_EQU1_EQU_C1_DK 0x198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ATV_TOP_EQU1_EQU_C1_I 0x1F6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ATV_TOP_EQU2_EQU_C2_FM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ATV_TOP_EQU2_EQU_C2_L 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ATV_TOP_EQU2_EQU_C2_LP 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ATV_TOP_EQU2_EQU_C2_BG 0xC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ATV_TOP_EQU2_EQU_C2_DK 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ATV_TOP_EQU2_EQU_C2_I 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ATV_TOP_EQU3_EQU_C3_FM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ATV_TOP_EQU3_EQU_C3_L 0x192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ATV_TOP_EQU3_EQU_C3_LP 0x192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ATV_TOP_EQU3_EQU_C3_BG 0x12E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ATV_TOP_EQU3_EQU_C3_DK 0x18E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ATV_TOP_EQU3_EQU_C3_I 0x192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ATV_TOP_STD_MODE_MN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ATV_TOP_STD_MODE_FM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ATV_TOP_STD_MODE_L 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ATV_TOP_STD_MODE_LP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ATV_TOP_STD_MODE_BG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ATV_TOP_STD_MODE_DK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ATV_TOP_STD_MODE_I 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ATV_TOP_STD_VID_POL_MN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ATV_TOP_STD_VID_POL_FM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ATV_TOP_STD_VID_POL_L 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ATV_TOP_STD_VID_POL_LP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ATV_TOP_STD_VID_POL_BG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ATV_TOP_STD_VID_POL_DK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ATV_TOP_STD_VID_POL_I 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ATV_TOP_VID_AMP_MN 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ATV_TOP_VID_AMP_FM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ATV_TOP_VID_AMP_L 0xF50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ATV_TOP_VID_AMP_LP 0xF50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ATV_TOP_VID_AMP_BG 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ATV_TOP_VID_AMP_DK 0x394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ATV_TOP_VID_AMP_I 0x3D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IQM_CF_OUT_ENA_OFDM__M 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IQM_FS_ADJ_SEL_B_QAM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IQM_FS_ADJ_SEL_B_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IQM_FS_ADJ_SEL_B_VSB 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IQM_RC_ADJ_SEL_B_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IQM_RC_ADJ_SEL_B_QAM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IQM_RC_ADJ_SEL_B_VSB 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*** END DJCOMBO patches to DRXJ registermap *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #include "drx_driver_version.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* #define DRX_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #ifdef DRX_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #include <stdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ENUMS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) DEFINES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #ifndef DRXJ_WAKE_UP_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * \def DRXJ_DEF_I2C_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * \brief Default I2C address of a demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DRXJ_DEF_I2C_ADDR (0x52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * \def DRXJ_DEF_DEMOD_DEV_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * \brief Default device identifier of a demodultor instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DRXJ_DEF_DEMOD_DEV_ID (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * \def DRXJ_SCAN_TIMEOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * \brief Timeout value for waiting on demod lock during channel scan (millisec).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DRXJ_SCAN_TIMEOUT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * \def HI_I2C_DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * \brief HI timing delay for I2C timing (in nano seconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Used to compute HI_CFG_DIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define HI_I2C_DELAY 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * \def HI_I2C_BRIDGE_DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * \brief HI timing delay for I2C timing (in nano seconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Used to compute HI_CFG_BDL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define HI_I2C_BRIDGE_DELAY 750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * \brief Time Window for MER and SER Measurement in Units of Segment duration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define VSB_TOP_MEASUREMENT_PERIOD 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SYMBOLS_PER_SEGMENT 832
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * \brief bit rate and segment rate constants used for SER and BER.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* values taken from the QAM microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DRXJ_QAM_SL_SIG_POWER_QPSK 32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DRXJ_QAM_SL_SIG_POWER_QAM8 24576
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DRXJ_QAM_SL_SIG_POWER_QAM16 40960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DRXJ_QAM_SL_SIG_POWER_QAM32 20480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DRXJ_QAM_SL_SIG_POWER_QAM64 43008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DRXJ_QAM_SL_SIG_POWER_QAM128 20992
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DRXJ_QAM_SL_SIG_POWER_QAM256 43520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * \brief Min supported symbolrates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #ifndef DRXJ_QAM_SYMBOLRATE_MIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DRXJ_QAM_SYMBOLRATE_MIN (520000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * \brief Max supported symbolrates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #ifndef DRXJ_QAM_SYMBOLRATE_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DRXJ_QAM_SYMBOLRATE_MAX (7233000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * \def DRXJ_QAM_MAX_WAITTIME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * \brief Maximal wait time for QAM auto constellation in ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #ifndef DRXJ_QAM_MAX_WAITTIME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DRXJ_QAM_MAX_WAITTIME 900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #ifndef DRXJ_QAM_FEC_LOCK_WAITTIME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DRXJ_QAM_FEC_LOCK_WAITTIME 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * \def SCU status and results
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * \brief SCU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define DRX_SCU_READY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DRXJ_MAX_WAITTIME 100 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * \def DRX_AUD_MAX_DEVIATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * \brief Needed for calculation of prescale feature in AUD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #ifndef DRXJ_AUD_MAX_FM_DEVIATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * \brief Needed for calculation of NICAM prescale feature in AUD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #ifndef DRXJ_AUD_MAX_NICAM_PRESCALE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * \brief Needed for calculation of NICAM prescale feature in AUD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #ifndef DRXJ_AUD_MAX_WAITTIME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define DRXJ_AUD_MAX_WAITTIME 250 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* ATV config changed flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DRXJ_ATV_CHANGED_COEF (0x00000001UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define DRXJ_ATV_CHANGED_PEAK_FLT (0x00000008UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define DRXJ_ATV_CHANGED_NOISE_FLT (0x00000010UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DRXJ_ATV_CHANGED_OUTPUT (0x00000020UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DRXJ_ATV_CHANGED_SIF_ATT (0x00000040UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* UIO define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * MICROCODE RELATED DEFINES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Magic word for checking correct Endianness of microcode data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DRX_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L'))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* CRC flag in ucode header, flags field. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DRX_UCODE_CRC_FLAG (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * Maximum size of buffer used to verify the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Must be an even number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #if DRX_UCODE_MAX_BUF_SIZE & 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #error DRX_UCODE_MAX_BUF_SIZE must be an even number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * Power mode macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) (mode == DRX_POWER_MODE_10) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) (mode == DRX_POWER_MODE_11) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) (mode == DRX_POWER_MODE_12) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) (mode == DRX_POWER_MODE_13) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) (mode == DRX_POWER_MODE_14) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) (mode == DRX_POWER_MODE_15) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) (mode == DRX_POWER_MODE_16) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) (mode == DRX_POWER_DOWN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Pin safe mode macro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define DRXJ_PIN_SAFE_MODE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*=== GLOBAL VARIABLEs =======================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * \brief Temporary register definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * (register definitions that are not yet available in register master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Audio block 0x103 is write only. To avoid shadowing in driver accessing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* RAM addresses directly. This must be READ ONLY to avoid problems. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Writing to the interface addresses are more than only writing the RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* locations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * \brief RAM location of MODUS registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define AUD_DEM_RAM_MODUS_HI__A 0x10204A3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define AUD_DEM_RAM_MODUS_HI__M 0xF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define AUD_DEM_RAM_MODUS_LO__A 0x10204A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define AUD_DEM_RAM_MODUS_LO__M 0x0FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * \brief RAM location of I2S config registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * \brief RAM location of DCO config registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define AUD_DEM_RAM_DCO_B_HI__A 0x1020461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define AUD_DEM_RAM_DCO_B_LO__A 0x1020462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define AUD_DEM_RAM_DCO_A_HI__A 0x1020463
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define AUD_DEM_RAM_DCO_A_LO__A 0x1020464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * \brief RAM location of Threshold registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * \brief RAM location of Carrier Threshold registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * \brief FM Matrix register fix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #ifdef AUD_DEM_WR_FM_MATRIX__A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #undef AUD_DEM_WR_FM_MATRIX__A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define AUD_DEM_WR_FM_MATRIX__A 0x105006F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * \brief Defines required for audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define AUD_VOLUME_ZERO_DB 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define AUD_VOLUME_DB_MIN -60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define AUD_VOLUME_DB_MAX 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define AUD_CARRIER_STRENGTH_QP_0DB 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define AUD_MAX_AVC_REF_LEVEL 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define AUD_I2S_FREQUENCY_MAX 48000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define AUD_I2S_FREQUENCY_MIN 12000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define AUD_RDS_ARRAY_SIZE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * \brief Needed for calculation of prescale feature in AUD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #ifndef DRX_AUD_MAX_FM_DEVIATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * \brief Needed for calculation of NICAM prescale feature in AUD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #ifndef DRX_AUD_MAX_NICAM_PRESCALE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define DRX_AUD_MAX_NICAM_PRESCALE (9) /* dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Values for I2S Master/Slave pin configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define SIO_PDR_I2S_CL_CFG_MODE__MASTER 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SIO_PDR_I2S_CL_CFG_MODE__SLAVE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SIO_PDR_I2S_DA_CFG_MODE__MASTER 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SIO_PDR_I2S_DA_CFG_MODE__SLAVE 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SIO_PDR_I2S_WS_CFG_MODE__MASTER 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define SIO_PDR_I2S_WS_CFG_MODE__SLAVE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*=== REGISTER ACCESS MACROS =================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * This macro is used to create byte arrays for block writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * Block writes speed up I2C traffic between host and demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * The macro takes care of the required byte order in a 16 bits word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * x -> lowbyte(x), highbyte(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ((u8)((((u16)x)>>8)&0xFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * This macro is used to convert byte array to 16 bit register value for block read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * Block read speed up I2C traffic between host and demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * The macro takes care of the required byte order in a 16 bits word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*=== MISC DEFINES ===========================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*=== HI COMMAND RELATED DEFINES =============================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * \brief General maximum number of retries for ucode command interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define DRXJ_MAX_RETRIES (100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*=== STANDARD RELATED MACROS ================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define DRXJ_ISATVSTD(std) ((std == DRX_STANDARD_PAL_SECAM_BG) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) (std == DRX_STANDARD_PAL_SECAM_DK) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) (std == DRX_STANDARD_PAL_SECAM_I) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) (std == DRX_STANDARD_PAL_SECAM_L) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) (std == DRX_STANDARD_PAL_SECAM_LP) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) (std == DRX_STANDARD_NTSC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) (std == DRX_STANDARD_FM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define DRXJ_ISQAMSTD(std) ((std == DRX_STANDARD_ITU_A) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) (std == DRX_STANDARD_ITU_B) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) (std == DRX_STANDARD_ITU_C) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) (std == DRX_STANDARD_ITU_D))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GLOBAL VARIABLES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * DRXJ DAP structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u16 datasize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u8 *data, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 waddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 raddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u16 wdata, u16 *rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u16 *data, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 *data, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u16 datasize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u8 *data, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u16 data, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u32 data, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static struct drxj_data drxj_data_g = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) false, /* has_lna : true if LNA (aka PGA) present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) false, /* has_oob : true if OOB supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) false, /* has_ntsc: true if NTSC supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) false, /* has_btsc: true if BTSC supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) false, /* has_smatx: true if SMA_TX pin is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) false, /* has_smarx: true if SMA_RX pin is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) false, /* has_gpio : true if GPIO pin is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) false, /* has_irqn : true if IRQN pin is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 0, /* mfx A1/A2/A... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* tuner settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) false, /* tuner mirrors RF signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* standard/channel settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) DRX_STANDARD_UNKNOWN, /* current standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) DRX_CONSTELLATION_AUTO, /* constellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 0, /* frequency in KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) DRX_BANDWIDTH_UNKNOWN, /* curr_bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) DRX_MIRROR_NO, /* mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* signal quality information: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* default values taken from the QAM Programming guide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* fec_bits_desired should not be less than 4000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 4000000, /* fec_bits_desired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 5, /* fec_vd_plen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 4, /* qam_vd_prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 0xFFFF, /* qamVDPeriod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 204 * 8, /* fec_rs_plen annex A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 1, /* fec_rs_prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) FEC_RS_MEASUREMENT_PERIOD, /* fec_rs_period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) true, /* reset_pkt_err_acc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 0, /* pkt_err_acc_start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* HI configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 0, /* hi_cfg_timing_div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 0, /* hi_cfg_bridge_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 0, /* hi_cfg_wake_up_key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 0, /* hi_cfg_ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 0, /* HICfgTimeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* UIO configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DRX_UIO_MODE_DISABLE, /* uio_sma_rx_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) DRX_UIO_MODE_DISABLE, /* uio_sma_tx_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) DRX_UIO_MODE_DISABLE, /* uioASELMode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) DRX_UIO_MODE_DISABLE, /* uio_irqn_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* FS setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 0UL, /* iqm_fs_rate_ofs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) false, /* pos_image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* RC setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 0UL, /* iqm_rc_rate_ofs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* AUD information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* false, * flagSetAUDdone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* false, * detectedRDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* true, * flagASDRequest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* false, * flagHDevClear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* false, * flagHDevSet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* (u16) 0xFFF, * rdsLastCount */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* ATV configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 0UL, /* flags cfg changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* shadow of ATV_TOP_EQU0__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {-5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ATV_TOP_EQU0_EQU_C0_FM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ATV_TOP_EQU0_EQU_C0_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ATV_TOP_EQU0_EQU_C0_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ATV_TOP_EQU0_EQU_C0_BG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ATV_TOP_EQU0_EQU_C0_DK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ATV_TOP_EQU0_EQU_C0_I},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* shadow of ATV_TOP_EQU1__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {-50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ATV_TOP_EQU1_EQU_C1_FM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ATV_TOP_EQU1_EQU_C1_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ATV_TOP_EQU1_EQU_C1_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ATV_TOP_EQU1_EQU_C1_BG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ATV_TOP_EQU1_EQU_C1_DK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ATV_TOP_EQU1_EQU_C1_I},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* shadow of ATV_TOP_EQU2__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ATV_TOP_EQU2_EQU_C2_FM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ATV_TOP_EQU2_EQU_C2_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ATV_TOP_EQU2_EQU_C2_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ATV_TOP_EQU2_EQU_C2_BG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ATV_TOP_EQU2_EQU_C2_DK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ATV_TOP_EQU2_EQU_C2_I},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* shadow of ATV_TOP_EQU3__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {-160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ATV_TOP_EQU3_EQU_C3_FM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ATV_TOP_EQU3_EQU_C3_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ATV_TOP_EQU3_EQU_C3_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ATV_TOP_EQU3_EQU_C3_BG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ATV_TOP_EQU3_EQU_C3_DK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ATV_TOP_EQU3_EQU_C3_I},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) false, /* flag: true=bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) true, /* flag CVBS output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) false, /* flag SIF output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { /* qam_rf_agc_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) DRX_STANDARD_ITU_B, /* standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) DRX_AGC_CTRL_AUTO, /* ctrl_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 0, /* output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 0, /* min_output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 0xFFFF, /* max_output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 0x0000, /* speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 0x0000, /* top */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 0x0000 /* c.o.c. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { /* qam_if_agc_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) DRX_STANDARD_ITU_B, /* standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) DRX_AGC_CTRL_AUTO, /* ctrl_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 0, /* output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 0, /* min_output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 0xFFFF, /* max_output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 0x0000, /* speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 0x0000, /* top (don't care) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 0x0000 /* c.o.c. (don't care) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) { /* vsb_rf_agc_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) DRX_STANDARD_8VSB, /* standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) DRX_AGC_CTRL_AUTO, /* ctrl_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 0, /* output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 0, /* min_output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 0xFFFF, /* max_output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 0x0000, /* speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 0x0000, /* top (don't care) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 0x0000 /* c.o.c. (don't care) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) { /* vsb_if_agc_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) DRX_STANDARD_8VSB, /* standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) DRX_AGC_CTRL_AUTO, /* ctrl_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 0, /* output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 0, /* min_output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 0xFFFF, /* max_output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 0x0000, /* speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 0x0000, /* top (don't care) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 0x0000 /* c.o.c. (don't care) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 0, /* qam_pga_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 0, /* vsb_pga_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { /* qam_pre_saw_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) DRX_STANDARD_ITU_B, /* standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 0, /* reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) false /* use_pre_saw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { /* vsb_pre_saw_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) DRX_STANDARD_8VSB, /* standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 0, /* reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) false /* use_pre_saw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Version information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #ifndef _CH_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) "01234567890", /* human readable version microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) "01234567890" /* human readable version device specific code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) { /* struct drx_version for microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) DRX_MODULE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) (char *)(NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) (char *)(NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) { /* struct drx_version for device specific code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) DRX_MODULE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) (char *)(NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) (char *)(NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) { /* struct drx_version_list for microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) (struct drx_version *) (NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) (struct drx_version_list *) (NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) { /* struct drx_version_list for device specific code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) (struct drx_version *) (NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) (struct drx_version_list *) (NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) false, /* smart_ant_inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* Tracking filter setting for OOB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 12000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 9300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 6600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 5280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 3700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) false, /* oob_power_on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 0, /* mpeg_ts_static_bitrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) false, /* disable_te_ihandling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) false, /* bit_reverse_mpeg_outout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpeg_output_clock_rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpeg_start_width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* Pre SAW & Agc configuration for ATV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) DRX_STANDARD_NTSC, /* standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 7, /* reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) true /* use_pre_saw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) { /* ATV RF-AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) DRX_STANDARD_NTSC, /* standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) DRX_AGC_CTRL_AUTO, /* ctrl_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 0, /* output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 0, /* min_output_level (d.c.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 0, /* max_output_level (d.c.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 3, /* speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 9500, /* top */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 4000 /* cut-off current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) { /* ATV IF-AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) DRX_STANDARD_NTSC, /* standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) DRX_AGC_CTRL_AUTO, /* ctrl_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 0, /* output_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 0, /* min_output_level (d.c.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 0, /* max_output_level (d.c.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 3, /* speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 2400, /* top */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 0 /* c.o.c. (d.c.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 140, /* ATV PGA config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 0, /* curr_symbol_rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) false, /* pdr_safe_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) SIO_PDR_GPIO_CFG__PRE, /* pdr_safe_restore_val_gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) SIO_PDR_VSYNC_CFG__PRE, /* pdr_safe_restore_val_v_sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) SIO_PDR_SMA_RX_CFG__PRE, /* pdr_safe_restore_val_sma_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) SIO_PDR_SMA_TX_CFG__PRE, /* pdr_safe_restore_val_sma_tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 4, /* oob_pre_saw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) DRXJ_OOB_LO_POW_MINUS10DB, /* oob_lo_pow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) false /* aud_data, only first member */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * \var drxj_default_addr_g
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * \brief Default I2C address and device identifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static struct i2c_device_addr drxj_default_addr_g = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) DRXJ_DEF_I2C_ADDR, /* i2c address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) DRXJ_DEF_DEMOD_DEV_ID /* device id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * \var drxj_default_comm_attr_g
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * \brief Default common attributes of a drxj demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static struct drx_common_attr drxj_default_comm_attr_g = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) NULL, /* ucode file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) true, /* ucode verify switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {0}, /* version record */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) 44000, /* IF in kHz in case no tuner instance is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) (151875 - 0), /* system clock frequency in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) 0, /* oscillator frequency kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) 0, /* oscillator deviation in ppm, signed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) false, /* If true mirror frequency spectrum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* MPEG output configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) true, /* If true, enable MPEG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) false, /* If true, insert RS byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) false, /* If true, parallel out otherwise serial */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) false, /* If true, invert DATA signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) false, /* If true, invert ERR signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) false, /* If true, invert STR signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) false, /* If true, invert VAL signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) false, /* If true, invert CLK signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) true, /* If true, static MPEG clockrate will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) be used, otherwise clockrate will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) adapt to the bitrate of the TS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) 19392658UL, /* Maximum bitrate in b/s in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static clockrate is selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Initilisations below can be omitted, they require no user input and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) are initially 0, NULL or false. The compiler will initialize them to these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) values when omitted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) false, /* is_opened */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* SCAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) NULL, /* no scan params yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) 0, /* current scan index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) 0, /* next scan frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) false, /* scan ready flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) 0, /* max channels to scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) 0, /* nr of channels scanned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) NULL, /* default scan function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) NULL, /* default context pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) 0, /* millisec to wait for demod lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) DRXJ_DEMOD_LOCK, /* desired lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* Power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) DRX_POWER_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) 1, /* nr of I2C port to which tuner is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) 0L, /* minimum RF input frequency, in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) 0L, /* maximum RF input frequency, in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) false, /* Rf Agc Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) false, /* If Agc Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) false, /* tuner slow mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) { /* current channel (all 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) 0UL /* channel.frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) DRX_STANDARD_UNKNOWN, /* current standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) DRX_STANDARD_UNKNOWN, /* previous standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) DRX_STANDARD_UNKNOWN, /* di_cache_standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) false, /* use_bootloader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) 0UL, /* capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) 0 /* mfx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * \var drxj_default_demod_g
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * \brief Default drxj demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static struct drx_demod_instance drxj_default_demod_g = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) &drxj_default_addr_g, /* i2c address & device id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) &drxj_default_comm_attr_g, /* demod common attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) &drxj_data_g /* demod device specific attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * \brief Default audio data structure for DRK demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * This structure is DRXK specific.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static struct drx_aud_data drxj_default_aud_data_g = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) false, /* audio_is_active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) DRX_AUD_STANDARD_AUTO, /* audio_standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* i2sdata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) false, /* output_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) 48000, /* frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) DRX_I2S_MODE_MASTER, /* mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) DRX_I2S_WORDLENGTH_32, /* word_length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) DRX_I2S_POLARITY_RIGHT, /* polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) DRX_I2S_FORMAT_WS_WITH_DATA /* format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) true, /* mute; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) 0, /* volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) DRX_AUD_AVC_OFF, /* avc_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) 0, /* avc_ref_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) DRX_AUD_AVC_MAX_GAIN_12DB, /* avc_max_gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) DRX_AUD_AVC_MAX_ATTEN_24DB, /* avc_max_atten */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) 0, /* strength_left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) 0 /* strength_right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, /* auto_sound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* ass_thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) 440, /* A2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) 12, /* BTSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) 700, /* NICAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* carrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) 42, /* thres */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) DRX_NO_CARRIER_NOISE, /* opt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) 0, /* shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) 0 /* dco */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) 42, /* thres */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) DRX_NO_CARRIER_MUTE, /* opt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) 0, /* shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) 0 /* dco */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) DRX_AUD_SRC_STEREO_OR_A, /* source_i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) DRX_AUD_I2S_MATRIX_STEREO, /* matrix_i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) DRX_AUD_FM_MATRIX_SOUND_A /* matrix_fm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) DRX_AUD_DEVIATION_NORMAL, /* deviation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) DRX_AUD_AVSYNC_OFF, /* av_sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) DRX_AUD_MAX_FM_DEVIATION, /* fm_deviation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) DRX_AUD_MAX_NICAM_PRESCALE /* nicam_gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) DRX_AUD_FM_DEEMPH_75US, /* deemph */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) DRX_BTSC_STEREO, /* btsc_detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) 0, /* rds_data_counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) false /* rds_data_present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /*-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) STRUCTURES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct drxjeq_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u16 eq_mse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) u8 eq_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u8 eq_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) u8 eq_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* HI command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct drxj_hi_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) u16 param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u16 param2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) u16 param3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) u16 param4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u16 param5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) u16 param6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /*=== MICROCODE RELATED STRUCTURES ===========================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * struct drxu_code_block_hdr - Structure of the microcode block headers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * @addr: Destination address of the data in this block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * @size: Size of the block data following this header counted in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * 16 bits words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * @CRC: CRC value of the data block, only valid if CRC flag is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct drxu_code_block_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) u16 CRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /*-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) FUNCTIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* Some prototypes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) hi_command(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) const struct drxj_hi_cmd *cmd, u16 *result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static int power_down_aud(struct drx_demod_instance *demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /*== HELPER FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * \fn u32 frac28(u32 N, u32 D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * \brief Compute: (1<<28)*N/D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * \param N 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * \param D 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * \return (1<<28)*N/D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * This function is used to avoid floating-point calculations as they may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * not be present on the target platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * frac28 performs an unsigned 28/28 bits division to 32-bit fixed point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * fraction used for setting the Frequency Shifter registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * N and D can hold numbers up to width: 28-bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * The 4 bits integer part and the 28 bits fractional part are calculated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * N: 0...(1<<28)-1 = 268435454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * D: 0...(1<<28)-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * Q: 0...(1<<32)-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static u32 frac28(u32 N, u32 D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u32 Q1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u32 R0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) Q1 = N / D; /* integer part, only the 4 least significant bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) will be visible in the result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* division using radix 16, 7 nibbles in the result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) for (i = 0; i < 7; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) Q1 = (Q1 << 4) | R0 / D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) R0 = (R0 % D) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* rounding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if ((R0 >> 3) >= D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) Q1++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return Q1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * \fn u32 log1_times100( u32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * \brief Compute: 100*log10(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * \param x 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * \return 100*log10(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * 100*log10(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * = 100*(log2(x)/log2(10)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * = (100*(2^15)*log2(x))/((2^15)*log2(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * = ((200*(2^15)*log2(x))/((2^15)*log2(10)))/2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * = ((200*(2^15)*(log2(x/y)+log2(y)))/((2^15)*log2(10)))/2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * = ((200*(2^15)*log2(x/y))+(200*(2^15)*log2(y)))/((2^15)*log2(10)))/2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * where y = 2^k and 1<= (x/y) < 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static u32 log1_times100(u32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static const u8 scale = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static const u8 index_width = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) log2lut[n] = (1<<scale) * 200 * log2( 1.0 + ( (1.0/(1<<INDEXWIDTH)) * n ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) 0 <= n < ((1<<INDEXWIDTH)+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static const u32 log2lut[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) 0, /* 0.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) 290941, /* 290941.300628 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) 573196, /* 573196.476418 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) 847269, /* 847269.179851 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) 1113620, /* 1113620.489452 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) 1372674, /* 1372673.576986 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) 1624818, /* 1624817.752104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) 1870412, /* 1870411.981536 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) 2109788, /* 2109787.962654 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) 2343253, /* 2343252.817465 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) 2571091, /* 2571091.461923 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) 2793569, /* 2793568.696416 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) 3010931, /* 3010931.055901 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) 3223408, /* 3223408.452106 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) 3431216, /* 3431215.635215 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) 3634553, /* 3634553.498355 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) 3833610, /* 3833610.244726 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) 4028562, /* 4028562.434393 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) 4219576, /* 4219575.925308 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) 4406807, /* 4406806.721144 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) 4590402, /* 4590401.736809 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) 4770499, /* 4770499.491025 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) 4947231, /* 4947230.734179 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) 5120719, /* 5120719.018555 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) 5291081, /* 5291081.217197 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) 5458428, /* 5458427.996830 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) 5622864, /* 5622864.249668 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) 5784489, /* 5784489.488298 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) 5943398, /* 5943398.207380 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) 6099680, /* 6099680.215452 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) 6253421, /* 6253420.939751 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) 6404702, /* 6404701.706649 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) 6553600, /* 6553600.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) u8 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) u32 y = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) u32 d = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u32 k = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) u32 r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (x == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Scale x (normalize) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* computing y in log(x/y) = log(x) - log(y) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if ((x & (((u32) (-1)) << (scale + 1))) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) for (k = scale; k > 0; k--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (x & (((u32) 1) << scale))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) x <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) for (k = scale; k < 31; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if ((x & (((u32) (-1)) << (scale + 1))) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) x >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) Now x has binary point between bit[scale] and bit[scale-1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) and 1.0 <= x < 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* correction for division: log(x) = log(x/y)+log(y) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) y = k * ((((u32) 1) << scale) * 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* remove integer part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) x &= ((((u32) 1) << scale) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* get index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) i = (u8) (x >> (scale - index_width));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* compute delta (x-a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) d = x & ((((u32) 1) << (scale - index_width)) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* compute log, multiplication ( d* (.. )) must be within range ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) y += log2lut[i] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* Conver to log10() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) y /= 108853; /* (log2(10) << scale) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) r = (y >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* rounding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (y & ((u32)1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) r++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * \fn u32 frac_times1e6( u16 N, u32 D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * \brief Compute: (N/D) * 1000000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * \param N nominator 16-bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * \param D denominator 32-bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * \return u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * \retval ((N/D) * 1000000), 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * No check on D=0!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static u32 frac_times1e6(u32 N, u32 D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) u32 remainder = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) u32 frac = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) frac = (N * 1000000) / D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) To let it fit in a 32 bits computation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) frac = (N * (1000000 >> 4)) / (D >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) This would result in a problem in case D < 16 (div by 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) So we do it more elaborate as shown below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) frac = (((u32) N) * (1000000 >> 4)) / D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) frac <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) remainder = (((u32) N) * (1000000 >> 4)) % D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) remainder <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) frac += remainder / D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) remainder = remainder % D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if ((remainder * 2) > D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) frac++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * \brief Values for NICAM prescaler gain. Computed from dB to integer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /* Currently, unused as we lack support for analog TV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static const u16 nicam_presc_table_val[43] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) 5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) 18, 20, 23, 25, 28, 32, 36, 40, 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) 51, 57, 64, 71, 80, 90, 101, 113, 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /*== END HELPER FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /*== DRXJ DAP FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) This layer takes care of some device specific register access protocols:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) -conversion to short address format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) -access to audio block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) This layer is placed between the drx_dap_fasi and the rest of the drxj
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) specific implementation. This layer can use address map knowledge whereas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dap_fasi may not use memory map knowledge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * For audio currently only 16 bits read and write register access is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) supported. More is not needed. RMW and 32 or 8 bit access on audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) single/multi master) will be ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) TODO: check ignoring single/multimaster is ok for AUD access ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * \fn bool is_handled_by_aud_tr_if( u32 addr )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * \brief Check if this address is handled by the audio token ring interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * \param addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * \return bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * \retval true Yes, handled by audio token ring interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * \retval false No, not handled by audio token ring interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) bool is_handled_by_aud_tr_if(u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) bool retval = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) (DRXDAP_FASI_ADDR2BANK(addr) > 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) (DRXDAP_FASI_ADDR2BANK(addr) < 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) retval = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) u16 w_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) u8 *wData,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct i2c_device_addr *r_dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) u16 r_count, u8 *r_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct drx39xxj_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) unsigned int num_msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (w_dev_addr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* Read only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) state = r_dev_addr->user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) msg[0].addr = r_dev_addr->i2c_addr >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) msg[0].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) msg[0].buf = r_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) msg[0].len = r_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) num_msgs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) } else if (r_dev_addr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* Write only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) state = w_dev_addr->user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) msg[0].addr = w_dev_addr->i2c_addr >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) msg[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) msg[0].buf = wData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) msg[0].len = w_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) num_msgs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* Both write and read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) state = w_dev_addr->user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) msg[0].addr = w_dev_addr->i2c_addr >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) msg[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) msg[0].buf = wData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) msg[0].len = w_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) msg[1].addr = r_dev_addr->i2c_addr >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) msg[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) msg[1].buf = r_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) msg[1].len = r_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) num_msgs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (state->i2c == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) pr_err("i2c was zero, aborting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) pr_warn("drx3933: I2C write/read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #ifdef DJH_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (w_dev_addr == NULL || r_dev_addr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) state = w_dev_addr->user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (state->i2c == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) msg[0].addr = w_dev_addr->i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) msg[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) msg[0].buf = wData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) msg[0].len = w_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) msg[1].addr = r_dev_addr->i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) msg[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) msg[1].buf = r_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) msg[1].len = r_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) num_msgs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) w_dev_addr->i2c_addr, state->i2c, w_count, r_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (i2c_transfer(state->i2c, msg, 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) pr_warn("drx3933: I2C write/read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /*****************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * int drxdap_fasi_read_block (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * struct i2c_device_addr *dev_addr, -- address of I2C device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * u32 addr, -- address of chip register/memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * u16 datasize, -- number of bytes to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * u8 *data, -- data to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * u32 flags) -- special device flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * Read block data from chip address. Because the chip is word oriented,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * the number of bytes to read must be even.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * Make sure that the buffer to receive the data is large enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * Although this function expects an even number of bytes, it is still byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * oriented, and the data read back is NOT translated to the endianness of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * the target platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) * Output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) * - 0 if reading was successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) * in that case: data read is in *data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * - -EIO if anything went wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) u16 datasize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) u8 *data, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) u16 bufx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) u16 overhead_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) /* Check parameters ******************************************************* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (dev_addr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) DRXDAP_FASI_LONG_FORMAT(addr)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* ReadModifyWrite & mode flag bits are not allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #if DRXDAP_SINGLE_MASTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) flags |= DRXDAP_FASI_SINGLE_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* Read block from I2C **************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) datasize : DRXDAP_MAX_RCHUNKSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) bufx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) addr &= ~DRXDAP_FASI_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) addr |= flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /* short format address preferred but long format otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (DRXDAP_FASI_LONG_FORMAT(addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) buf[bufx++] = (u8) ((addr << 1) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) buf[bufx++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) (u8) (((addr >> 16) & 0x0F) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) ((addr >> 18) & 0xF0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #if DRXDAP_SINGLE_MASTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) * In single master mode, split the read and write actions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) * No special action is needed for write chunks here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) rc = drxbsp_i2c_write_read(dev_addr, bufx, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* In multi master mode, do everything in one RW action */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) data += todo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) addr += (todo >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) datasize -= todo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) } while (datasize && rc == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /*****************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * int drxdap_fasi_read_reg16 (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * struct i2c_device_addr *dev_addr, -- address of I2C device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * u32 addr, -- address of chip register/memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * u16 *data, -- data to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * u32 flags) -- special device flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * Read one 16-bit register or memory location. The data received back is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) * converted back to the target platform's endianness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) * Output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) * - 0 if reading was successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) * in that case: read data is at *data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) * - -EIO if anything went wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) u16 *data, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) u8 buf[sizeof(*data)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) *data = buf[0] + (((u16) buf[1]) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /*****************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * int drxdap_fasi_read_reg32 (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * struct i2c_device_addr *dev_addr, -- address of I2C device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * u32 addr, -- address of chip register/memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) * u32 *data, -- data to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * u32 flags) -- special device flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * Read one 32-bit register or memory location. The data received back is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * converted back to the target platform's endianness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * Output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * - 0 if reading was successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * in that case: read data is at *data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * - -EIO if anything went wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) u32 *data, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) u8 buf[sizeof(*data)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) *data = (((u32) buf[0]) << 0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) (((u32) buf[1]) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /*****************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) * int drxdap_fasi_write_block (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) * struct i2c_device_addr *dev_addr, -- address of I2C device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) * u32 addr, -- address of chip register/memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) * u16 datasize, -- number of bytes to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) * u8 *data, -- data to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) * u32 flags) -- special device flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) * Write block data to chip address. Because the chip is word oriented,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) * the number of bytes to write must be even.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) * Although this function expects an even number of bytes, it is still byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * oriented, and the data being written is NOT translated from the endianness of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * the target platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * Output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) * - 0 if writing was successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) * - -EIO if anything went wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) u16 datasize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) u8 *data, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) u8 buf[DRXDAP_MAX_WCHUNKSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) int st = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) int first_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) u16 overhead_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) u16 block_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) /* Check parameters ******************************************************* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (dev_addr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) DRXDAP_FASI_LONG_FORMAT(addr)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) flags &= DRXDAP_FASI_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) flags &= ~DRXDAP_FASI_MODEFLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #if DRXDAP_SINGLE_MASTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) flags |= DRXDAP_FASI_SINGLE_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* Write block to I2C ***************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) u16 todo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) u16 bufx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) /* Buffer device address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) addr &= ~DRXDAP_FASI_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) addr |= flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /* short format address preferred but long format otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (DRXDAP_FASI_LONG_FORMAT(addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) #if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) buf[bufx++] = (u8) ((addr << 1) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) buf[bufx++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) (u8) (((addr >> 16) & 0x0F) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ((addr >> 18) & 0xF0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) In single master mode block_size can be 0. In such a case this I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) sequense will be visible: (1) write address {i2c addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) 4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) (3) write address (4) write data etc...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) Address must be rewritten because HI is reset after data transport and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) expects an address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) todo = (block_size < datasize ? block_size : datasize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (todo == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) u16 overhead_size_i2c_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) u16 data_block_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) overhead_size_i2c_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) data_block_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) /* write device address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) st = drxbsp_i2c_write_read(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) (u16) (bufx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) (struct i2c_device_addr *)(NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) 0, (u8 *)(NULL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if ((st != 0) && (first_err == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) /* at the end, return the first error encountered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) first_err = st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) bufx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) todo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) (data_block_size <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) datasize ? data_block_size : datasize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) memcpy(&buf[bufx], data, todo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) /* write (address if can do and) data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) st = drxbsp_i2c_write_read(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) (u16) (bufx + todo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) (struct i2c_device_addr *)(NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) 0, (u8 *)(NULL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if ((st != 0) && (first_err == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /* at the end, return the first error encountered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) first_err = st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) datasize -= todo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) data += todo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) addr += (todo >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) } while (datasize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) return first_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /*****************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) * int drxdap_fasi_write_reg16 (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) * struct i2c_device_addr *dev_addr, -- address of I2C device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) * u32 addr, -- address of chip register/memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) * u16 data, -- data to send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) * u32 flags) -- special device flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) * Write one 16-bit register or memory location. The data being written is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) * converted from the target platform's endianness to little endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * Output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) * - 0 if writing was successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) * - -EIO if anything went wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) u16 data, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) u8 buf[sizeof(data)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) buf[0] = (u8) ((data >> 0) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) buf[1] = (u8) ((data >> 8) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) /*****************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) * int drxdap_fasi_read_modify_write_reg16 (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) * struct i2c_device_addr *dev_addr, -- address of I2C device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) * u32 waddr, -- address of chip register/memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) * u32 raddr, -- chip address to read back from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) * u16 wdata, -- data to send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) * u16 *rdata) -- data to receive back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) * Write 16-bit data, then read back the original contents of that location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * Requires long addressing format to be allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) * Before sending data, the data is converted to little endian. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) * data received back is converted back to the target platform's endianness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * WARNING: This function is only guaranteed to work if there is one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * master on the I2C bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * Output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * - 0 if reading was successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * in that case: read back data is at *rdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) * - -EIO if anything went wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) u32 waddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) u32 raddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) u16 wdata, u16 *rdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) int rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) if (rdata == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /*****************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) * int drxdap_fasi_write_reg32 (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * struct i2c_device_addr *dev_addr, -- address of I2C device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) * u32 addr, -- address of chip register/memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) * u32 data, -- data to send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * u32 flags) -- special device flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) * Write one 32-bit register or memory location. The data being written is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) * converted from the target platform's endianness to little endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) * Output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) * - 0 if writing was successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * - -EIO if anything went wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) u32 data, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) u8 buf[sizeof(data)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) buf[0] = (u8) ((data >> 0) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) buf[1] = (u8) ((data >> 8) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) buf[2] = (u8) ((data >> 16) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) buf[3] = (u8) ((data >> 24) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) * \fn int drxj_dap_rm_write_reg16short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) * \brief Read modify write 16 bits audio register using short format only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) * \param dev_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) * \param waddr Address to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) * \param raddr Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * \param wdata Data to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) * \param rdata Buffer for data to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * \return int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * \retval 0 Success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * \retval -EIO Timeout, I2C error, illegal bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) * 16 bits register read modify write access using short addressing format only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) * Requires knowledge of the registermap, thus device dependent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) * Using DAP FASI directly to avoid endless recursion of RMWs to audio registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) /* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) See comments drxj_dap_read_modify_write_reg16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) u32 waddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) u32 raddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) u16 wdata, u16 *rdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (rdata == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /* Set RMW flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) rc = drxdap_fasi_write_reg16(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) SIO_HI_RA_RAM_S0_FLG_ACC__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (rc == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) /* Write new data: triggers RMW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (rc == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* Read old data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (rc == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) /* Reset RMW flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) rc = drxdap_fasi_write_reg16(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) SIO_HI_RA_RAM_S0_FLG_ACC__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) 0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) u32 waddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) u32 raddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) u16 wdata, u16 *rdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /* TODO: correct short/long addressing format decision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) now long format has higher prio then short because short also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) needs virt bnks (not impl yet) for certain audio registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) return drxdap_fasi_read_modify_write_reg16(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) waddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) raddr, wdata, rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) return drxj_dap_rm_write_reg16short(dev_addr, waddr, raddr, wdata, rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) * \fn int drxj_dap_read_aud_reg16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) * \brief Read 16 bits audio register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) * \param dev_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) * \param addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) * \param data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) * \return int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) * \retval 0 Success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) * \retval -EIO Timeout, I2C error, illegal bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) * 16 bits register read access via audio token ring interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) u32 addr, u16 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) u32 start_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) u32 current_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) u32 delta_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) u16 tr_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) int stat = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) /* No read possible for bank 3, return with error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (DRXDAP_FASI_ADDR2BANK(addr) == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) stat = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) const u32 write_bit = ((dr_xaddr_t) 1) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) /* Force reset write bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) addr &= (~write_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) /* Set up read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) start_timer = jiffies_to_msecs(jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) /* RMW to aud TR IF until request is granted or timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) stat = drxj_dap_read_modify_write_reg16(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) SIO_HI_RA_RAM_S0_RMWBUF__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) 0x0000, &tr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (stat != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) current_timer = jiffies_to_msecs(jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) delta_timer = current_timer - start_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) stat = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) AUD_TOP_TR_CTR_FIFO_FULL_FULL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) /* Wait for read ready status or timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (stat == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) start_timer = jiffies_to_msecs(jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) stat = drxj_dap_read_reg16(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) AUD_TOP_TR_CTR__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) &tr_status, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (stat != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) current_timer = jiffies_to_msecs(jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) delta_timer = current_timer - start_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) stat = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) } /* while ( ... ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) /* Read value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) if (stat == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) stat = drxj_dap_read_modify_write_reg16(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) AUD_TOP_TR_RD_REG__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) SIO_HI_RA_RAM_S0_RMWBUF__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) 0x0000, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) u16 *data, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) int stat = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) /* Check param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if ((dev_addr == NULL) || (data == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (is_handled_by_aud_tr_if(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) stat = drxj_dap_read_aud_reg16(dev_addr, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) * \fn int drxj_dap_write_aud_reg16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) * \brief Write 16 bits audio register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) * \param dev_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) * \param addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) * \param data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) * \return int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) * \retval 0 Success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) * \retval -EIO Timeout, I2C error, illegal bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * 16 bits register write access via audio token ring interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) u32 addr, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) int stat = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) /* No write possible for bank 2, return with error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if (DRXDAP_FASI_ADDR2BANK(addr) == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) stat = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) u32 start_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) u32 current_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) u32 delta_timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) u16 tr_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) const u32 write_bit = ((dr_xaddr_t) 1) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) /* Force write bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) addr |= write_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) start_timer = jiffies_to_msecs(jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) /* RMW to aud TR IF until request is granted or timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) stat = drxj_dap_read_modify_write_reg16(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) SIO_HI_RA_RAM_S0_RMWBUF__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) data, &tr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) if (stat != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) current_timer = jiffies_to_msecs(jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) delta_timer = current_timer - start_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) stat = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) AUD_TOP_TR_CTR_FIFO_FULL_FULL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) u16 data, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) int stat = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) /* Check param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) if (dev_addr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) if (is_handled_by_aud_tr_if(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) stat = drxj_dap_write_aud_reg16(dev_addr, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) stat = drxdap_fasi_write_reg16(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) addr, data, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) /* Free data ram in SIO HI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) #define SIO_HI_RA_RAM_USR_END__A 0x420060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) #define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) #define DRXJ_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) #define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) #define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) * \fn int drxj_dap_atomic_read_write_block()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) * \brief Basic access routine for atomic read or write access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) * \param dev_addr pointer to i2c dev address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) * \param addr destination/source address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) * \param datasize size of data buffer in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) * \param data pointer to data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) * \return int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) * \retval 0 Success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) * \retval -EIO Timeout, I2C error, illegal bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) u16 datasize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) u8 *data, bool read_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) struct drxj_hi_cmd hi_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) u16 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) u16 dummy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) u16 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) /* Parameter check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) /* Set up HI parameters to read or write n bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) hi_cmd.param1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) (u16) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) hi_cmd.param2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) hi_cmd.param3 = (u16) ((datasize / 2) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if (!read_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) DRXDAP_FASI_ADDR2BANK(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) if (!read_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) /* write data to buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) for (i = 0; i < (datasize / 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) word = ((u16) data[2 * i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) word += (((u16) data[(2 * i) + 1]) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) drxj_dap_write_reg16(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) (DRXJ_HI_ATOMIC_BUF_START + i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) word, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) rc = hi_command(dev_addr, &hi_cmd, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (read_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) /* read data from buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) for (i = 0; i < (datasize / 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) rc = drxj_dap_read_reg16(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) (DRXJ_HI_ATOMIC_BUF_START + i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) &word, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) data[2 * i] = (u8) (word & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) data[(2 * i) + 1] = (u8) (word >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) * \fn int drxj_dap_atomic_read_reg32()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) * \brief Atomic read of 32 bits words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) u32 *data, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) u8 buf[sizeof(*data)] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) u32 word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) rc = drxj_dap_atomic_read_write_block(dev_addr, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) sizeof(*data), buf, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) word = (u32) buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) word <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) word |= (u32) buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) word <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) word |= (u32) buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) word <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) word |= (u32) buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) *data = word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /*== END DRXJ DAP FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) /*== HOST INTERFACE FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) * \fn int hi_cfg_command()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) * \brief Configure HI with settings stored in the demod structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) * \param demod Demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) * This routine was created because to much orthogonal settings have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) * been put into one HI API function (configure). Especially the I2C bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) * enable/disable should not need re-configuration of the HI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) static int hi_cfg_command(const struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) struct drxj_hi_cmd hi_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) u16 result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) hi_cmd.param2 = ext_attr->hi_cfg_timing_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) hi_cmd.param5 = ext_attr->hi_cfg_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) hi_cmd.param6 = ext_attr->hi_cfg_transmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /* Reset power down flag (set one call only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) * \fn int hi_command()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) * \brief Configure HI with settings stored in the demod structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) * \param dev_addr I2C address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) * \param cmd HI command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) * \param result HI command result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) * Sends command to HI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) u16 wait_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) u16 nr_retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) bool powerdown_cmd = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) /* Write parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) switch (cmd->cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) case SIO_HI_RA_RAM_CMD_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) case SIO_HI_RA_RAM_CMD_ATOMIC_COPY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) case SIO_HI_RA_RAM_CMD_BRDCTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) case SIO_HI_RA_RAM_CMD_NULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) /* No parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) /* Write command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) /* Detect power down to omit reading result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) (((cmd->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) == SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) if (!powerdown_cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) /* Wait until command rdy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) nr_retries++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) if (nr_retries > DRXJ_MAX_RETRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) pr_err("timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) } while (wait_cmd != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) /* Read result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) /* if ( powerdown_cmd == true ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) * \fn int init_hi( const struct drx_demod_instance *demod )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) * \brief Initialise and configurate HI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) * \param demod pointer to demod data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) * \return int Return status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) * \retval 0 Success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) * \retval -EIO Failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) * Needs to know Psys (System Clock period) and Posc (Osc Clock period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) * Need to store configuration in driver because of the way I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) * bridging is controlled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) static int init_hi(const struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) common_attr = (struct drx_common_attr *) demod->my_common_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) /* PATCH for bug 5003, HI ucode v3.1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) /* Timing div, 250ns/Psys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) ext_attr->hi_cfg_timing_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) /* Clipping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) /* Bridge delay, uses oscilator clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) /* SDA brdige delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) ext_attr->hi_cfg_bridge_delay =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) /* Clipping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) /* SCL bridge delay, same as SDA for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) /* Wakeup key, setting the read flag (as suggest in the documentation) does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) not always result into a working solution (barebones worked VI2C failed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) Not setting the bit works in all cases . */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) /* port/bridge/power down ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) /* transit mode time out delay and watch dog divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) rc = hi_cfg_command(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) /*== END HOST INTERFACE FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) /*== AUXILIARY FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) * \fn int get_device_capabilities()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) * \brief Get and store device capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) * \param demod Pointer to demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) * \return 0 Success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) * \retval -EIO Failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) * Depending on pulldowns on MDx pins the following internals are set:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) * * common_attr->osc_clock_freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) * * ext_attr->has_lna
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) * * ext_attr->has_ntsc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) * * ext_attr->has_btsc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) * * ext_attr->has_oob
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) static int get_device_capabilities(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) struct drxj_data *ext_attr = (struct drxj_data *) NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) u16 sio_pdr_ohw_cfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) u32 sio_top_jtagid_lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) u16 bid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) common_attr = (struct drx_common_attr *) demod->my_common_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) /* ignore (bypass ?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) /* 27 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) common_attr->osc_clock_freq = 27000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) /* 20.25 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) common_attr->osc_clock_freq = 20250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) /* 4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) common_attr->osc_clock_freq = 4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) Determine device capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) Based on pinning v47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) case 0x31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) bid = (bid >> 10) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) ext_attr->has_lna = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) ext_attr->has_ntsc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) ext_attr->has_btsc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) ext_attr->has_oob = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) ext_attr->has_smatx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) ext_attr->has_smarx = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) ext_attr->has_gpio = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) ext_attr->has_irqn = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) case 0x33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) ext_attr->has_lna = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) ext_attr->has_ntsc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) ext_attr->has_btsc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) ext_attr->has_oob = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) ext_attr->has_smatx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) ext_attr->has_smarx = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) ext_attr->has_gpio = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) ext_attr->has_irqn = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) case 0x45:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) ext_attr->has_lna = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) ext_attr->has_ntsc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) ext_attr->has_btsc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) ext_attr->has_oob = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) ext_attr->has_smatx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) ext_attr->has_smarx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) ext_attr->has_gpio = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) ext_attr->has_irqn = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) case 0x46:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) ext_attr->has_lna = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) ext_attr->has_ntsc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) ext_attr->has_btsc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) ext_attr->has_oob = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) ext_attr->has_smatx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) ext_attr->has_smarx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) ext_attr->has_gpio = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) ext_attr->has_irqn = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) case 0x41:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) ext_attr->has_lna = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) ext_attr->has_ntsc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) ext_attr->has_btsc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) ext_attr->has_oob = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) ext_attr->has_smatx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) ext_attr->has_smarx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) ext_attr->has_gpio = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) ext_attr->has_irqn = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) case 0x43:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) ext_attr->has_lna = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) ext_attr->has_ntsc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) ext_attr->has_btsc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) ext_attr->has_oob = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) ext_attr->has_smatx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) ext_attr->has_smarx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) ext_attr->has_gpio = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) ext_attr->has_irqn = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) case 0x32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) ext_attr->has_lna = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) ext_attr->has_ntsc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) ext_attr->has_btsc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) ext_attr->has_oob = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) ext_attr->has_smatx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) ext_attr->has_smarx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) ext_attr->has_gpio = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) ext_attr->has_irqn = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) case 0x34:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) ext_attr->has_lna = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) ext_attr->has_ntsc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) ext_attr->has_btsc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) ext_attr->has_oob = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) ext_attr->has_smatx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) ext_attr->has_smarx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) ext_attr->has_gpio = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) ext_attr->has_irqn = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) case 0x42:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) ext_attr->has_lna = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) ext_attr->has_ntsc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) ext_attr->has_btsc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) ext_attr->has_oob = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) ext_attr->has_smatx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) ext_attr->has_smarx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) ext_attr->has_gpio = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) ext_attr->has_irqn = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) case 0x44:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) ext_attr->has_lna = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) ext_attr->has_ntsc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) ext_attr->has_btsc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) ext_attr->has_oob = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) ext_attr->has_smatx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) ext_attr->has_smarx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) ext_attr->has_gpio = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) ext_attr->has_irqn = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) /* Unknown device variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) * \fn int power_up_device()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) * \brief Power up device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) * \param demod Pointer to demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) * \return 0 Success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) * \retval -EIO Failure, I2C or max retries reached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) #ifndef DRXJ_MAX_RETRIES_POWERUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) #define DRXJ_MAX_RETRIES_POWERUP 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) static int power_up_device(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) u8 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) u16 retry_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) struct i2c_device_addr wake_up_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) wake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) wake_up_addr.user_data = dev_addr->user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) * I2C access may fail in this case: no ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) * dummy write must be used to wake uop device, dummy read must be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) * reset HI state machine (avoiding actual writes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) drxbsp_i2c_write_read(&wake_up_addr, 1, &data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) (struct i2c_device_addr *)(NULL), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) (u8 *)(NULL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) retry_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) } while ((drxbsp_i2c_write_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) &data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) != 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) /* Need some recovery time .... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) if (retry_count == DRXJ_MAX_RETRIES_POWERUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) /* MPEG Output Configuration Functions - begin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) * \fn int ctrl_set_cfg_mpeg_output()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) * \brief Set MPEG output configuration of the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) * \param devmod Pointer to demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) * \param cfg_data Pointer to mpeg output configuaration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) * Configure MPEG output parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) u16 fec_oc_reg_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) u16 fec_oc_reg_ipr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) u16 fec_oc_reg_ipr_invert = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) u32 max_bit_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) u32 rcn_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) u32 nr_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) u16 sio_pdr_md_cfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) /* data mask for the output data byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) u16 invert_data_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) /* check arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) if ((demod == NULL) || (cfg_data == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) common_attr = (struct drx_common_attr *) demod->my_common_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) if (cfg_data->enable_mpeg_output == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) /* quick and dirty patch to set MPEG in case current std is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) producing MPEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) switch (ext_attr->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) switch (ext_attr->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) } /* 2048 bytes fifo ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) /* Low Water Mark for synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) /* High Water Mark for synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) switch (ext_attr->constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) nr_bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) case DRX_CONSTELLATION_QAM128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) nr_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) nr_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) case DRX_CONSTELLATION_QAM32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) nr_bits = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) case DRX_CONSTELLATION_QAM16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) nr_bits = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) } /* ext_attr->constellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) /* max_bit_rate = symbol_rate * nr_bits * coef */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) /* coef = 188/204 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) max_bit_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) (ext_attr->curr_symbol_rate / 8) * nr_bits * 188;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) fallthrough; /* as b/c Annex A/C need following settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) if (cfg_data->static_clk == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) } /* switch (standard) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) /* Check insertion of the Reed-Solomon parity bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) if (cfg_data->insert_rs_byte == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) /* enable parity symbol forward */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) /* MVAL disable during parity bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) switch (ext_attr->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) rcn_rate = 0x004854D3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) fec_oc_reg_mode |= FEC_OC_MODE_TRANSPARENT__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) switch (ext_attr->constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) rcn_rate = 0x008945E7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) rcn_rate = 0x005F64D4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) rcn_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) (frac28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) (max_bit_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) (u32) (common_attr->sys_clock_freq / 8))) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) 188;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) } /* ext_attr->standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) } else { /* insert_rs_byte == false */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) /* disable parity symbol forward */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) /* MVAL enable during parity bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) switch (ext_attr->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) rcn_rate = 0x0041605C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) fec_oc_reg_mode &= (~FEC_OC_MODE_TRANSPARENT__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) switch (ext_attr->constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) rcn_rate = 0x0082D6A0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) rcn_rate = 0x005AEC1A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) rcn_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) (frac28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) (max_bit_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) (u32) (common_attr->sys_clock_freq / 8))) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) 204;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) } /* ext_attr->standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> clear ipr_mode[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) } else { /* MPEG data output is serial -> set ipr_mode[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) /* Control slective inversion of output bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) if (cfg_data->invert_data == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) fec_oc_reg_ipr_invert |= invert_data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) fec_oc_reg_ipr_invert &= (~(invert_data_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) if (cfg_data->invert_err == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) if (cfg_data->invert_str == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) if (cfg_data->invert_val == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) if (cfg_data->invert_clk == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) if (cfg_data->static_clk == true) { /* Static mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) u32 dto_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) u32 bit_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) u16 fec_oc_dto_burst_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) u16 fec_oc_dto_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) fec_oc_dto_burst_len = FEC_OC_DTO_BURST_LEN__PRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) switch (ext_attr->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) fec_oc_dto_period = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) if (cfg_data->insert_rs_byte == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) fec_oc_dto_burst_len = 208;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) u32 symbol_rate_th = 6400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) if (cfg_data->insert_rs_byte == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) fec_oc_dto_burst_len = 204;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) symbol_rate_th = 5900000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) if (ext_attr->curr_symbol_rate >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) symbol_rate_th) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) fec_oc_dto_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) fec_oc_dto_period = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) fec_oc_dto_period = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) if (cfg_data->insert_rs_byte == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) fec_oc_dto_burst_len = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) fec_oc_dto_period = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) if (cfg_data->insert_rs_byte == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) fec_oc_dto_burst_len = 204;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) bit_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) dto_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) frac28(bit_rate, common_attr->sys_clock_freq * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) dto_rate >>= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) } else { /* Dynamic mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) /* Write appropriate registers with requested configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) /* enabling for both parallel and serial now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) /* Write magic word to enable pdr reg write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) /* Set MPEG TS pads to outputmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) sio_pdr_md_cfg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> set MD1 to MD7 to output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) sio_pdr_md_cfg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) SIO_PDR_MD0_CFG_DRIVE__B | 0x03 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) SIO_PDR_MD0_CFG_MODE__B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) /* Enable Monitor Bus output over MPEG pads and ctl input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) /* Write nomagic word to enable pdr reg write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) /* Write magic word to enable pdr reg write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) /* Set MPEG TS pads to inputmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) /* Enable Monitor Bus output over MPEG pads and ctl input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) /* Write nomagic word to enable pdr reg write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) /* save values for restore after re-acquire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) /* MPEG Output Configuration Functions - end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) /* miscellaneous configurations - begin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) * \fn int set_mpegtei_handling()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) * \brief Activate MPEG TEI handling settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) * \param devmod Pointer to demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) * This routine should be called during a set channel of QAM/VSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) static int set_mpegtei_handling(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) u16 fec_oc_dpr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) u16 fec_oc_snc_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) u16 fec_oc_ems_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) /* reset to default, allow TEI bit to be changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) fec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) fec_oc_snc_mode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) FEC_OC_SNC_MODE_CORR_DISABLE__M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) if (ext_attr->disable_te_ihandling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) /* do not change TEI bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) ((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) * \fn int bit_reverse_mpeg_output()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) * \brief Set MPEG output bit-endian settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) * \param devmod Pointer to demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) * This routine should be called during a set channel of QAM/VSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) static int bit_reverse_mpeg_output(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) u16 fec_oc_ipr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) /* reset to default (normal bit order) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) if (ext_attr->bit_reverse_mpeg_outout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) * \fn int set_mpeg_start_width()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) * \brief Set MPEG start width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) * \param devmod Pointer to demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) * This routine should be called during a set channel of QAM/VSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) static int set_mpeg_start_width(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) u16 fec_oc_comm_mb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) common_attr = demod->my_common_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) if ((common_attr->mpeg_cfg.static_clk == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) && (common_attr->mpeg_cfg.enable_parallel == false)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) /* miscellaneous configurations - end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) /* UIO Configuration Functions - begin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) * \fn int ctrl_set_uio_cfg()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) * \brief Configure modus oprandi UIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) * \param demod Pointer to demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) * \param uio_cfg Pointer to a configuration setting for a certain UIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) if ((uio_cfg == NULL) || (demod == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) /* Write magic word to enable pdr reg write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) switch (uio_cfg->uio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) /*====================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) case DRX_UIO1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) /* DRX_UIO1: SMA_TX UIO-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) if (!ext_attr->has_smatx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) switch (uio_cfg->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) case DRX_UIO_MODE_FIRMWARE_SMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) case DRX_UIO_MODE_FIRMWARE_SAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) case DRX_UIO_MODE_READWRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) ext_attr->uio_sma_tx_mode = uio_cfg->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) case DRX_UIO_MODE_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) ext_attr->uio_sma_tx_mode = uio_cfg->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) /* pad configuration register is set 0 - input mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) } /* switch ( uio_cfg->mode ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) /*====================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) case DRX_UIO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) /* DRX_UIO2: SMA_RX UIO-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) if (!ext_attr->has_smarx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) switch (uio_cfg->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) case DRX_UIO_MODE_FIRMWARE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) case DRX_UIO_MODE_READWRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) ext_attr->uio_sma_rx_mode = uio_cfg->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) case DRX_UIO_MODE_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) ext_attr->uio_sma_rx_mode = uio_cfg->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) /* pad configuration register is set 0 - input mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) } /* switch ( uio_cfg->mode ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) /*====================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) case DRX_UIO3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) /* DRX_UIO3: GPIO UIO-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) if (!ext_attr->has_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) switch (uio_cfg->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) case DRX_UIO_MODE_FIRMWARE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) case DRX_UIO_MODE_READWRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) ext_attr->uio_gpio_mode = uio_cfg->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) case DRX_UIO_MODE_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) ext_attr->uio_gpio_mode = uio_cfg->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) /* pad configuration register is set 0 - input mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) } /* switch ( uio_cfg->mode ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) /*====================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) case DRX_UIO4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) /* DRX_UIO4: IRQN UIO-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) if (!ext_attr->has_irqn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) switch (uio_cfg->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) case DRX_UIO_MODE_READWRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) ext_attr->uio_irqn_mode = uio_cfg->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) case DRX_UIO_MODE_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) /* pad configuration register is set 0 - input mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) ext_attr->uio_irqn_mode = uio_cfg->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) case DRX_UIO_MODE_FIRMWARE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) } /* switch ( uio_cfg->mode ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) /*====================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) } /* switch ( uio_cfg->uio ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) /* Write magic word to disable pdr reg write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) * \fn int ctrl_uio_write()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) * \brief Write to a UIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) * \param demod Pointer to demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) * \param uio_data Pointer to data container for a certain UIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) u16 pin_cfg_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) u16 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) if ((uio_data == NULL) || (demod == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) /* Write magic word to enable pdr reg write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) switch (uio_data->uio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) /*====================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) case DRX_UIO1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) /* DRX_UIO1: SMA_TX UIO-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) if (!ext_attr->has_smatx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) pin_cfg_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) pin_cfg_value |= 0x0113;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) /* io_pad_cfg_mode output mode is drive always */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) /* io_pad_cfg_drive is set to power 2 (23 mA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) /* write to io pad configuration register - output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) /* use corresponding bit in io data output registar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) if (!uio_data->value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) value |= 0x8000; /* write one to 15th bit - 1st UIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) /* write back to io data output register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) /*======================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) case DRX_UIO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) /* DRX_UIO2: SMA_RX UIO-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) if (!ext_attr->has_smarx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) pin_cfg_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) pin_cfg_value |= 0x0113;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) /* io_pad_cfg_mode output mode is drive always */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) /* io_pad_cfg_drive is set to power 2 (23 mA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) /* write to io pad configuration register - output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) /* use corresponding bit in io data output registar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) if (!uio_data->value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) value |= 0x4000; /* write one to 14th bit - 2nd UIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) /* write back to io data output register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) /*====================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) case DRX_UIO3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) /* DRX_UIO3: ASEL UIO-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) if (!ext_attr->has_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) pin_cfg_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) pin_cfg_value |= 0x0113;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) /* io_pad_cfg_mode output mode is drive always */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) /* io_pad_cfg_drive is set to power 2 (23 mA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) /* write to io pad configuration register - output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) /* use corresponding bit in io data output registar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) if (!uio_data->value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) /* write back to io data output register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) /*=====================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) case DRX_UIO4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) /* DRX_UIO4: IRQN UIO-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) if (!ext_attr->has_irqn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) pin_cfg_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) pin_cfg_value |= 0x0113;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) /* io_pad_cfg_mode output mode is drive always */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) /* io_pad_cfg_drive is set to power 2 (23 mA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) /* write to io pad configuration register - output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) /* use corresponding bit in io data output registar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) if (uio_data->value == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) value |= 0x1000; /* write one to 12th bit - 4th UIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) /* write back to io data output register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) /*=====================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) } /* switch ( uio_data->uio ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) /* Write magic word to disable pdr reg write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) /*---------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) /* UIO Configuration Functions - end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) /*---------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) /* I2C Bridge Functions - begin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) * \fn int ctrl_i2c_bridge()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) * \brief Open or close the I2C switch to tuner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) * \param demod Pointer to demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) * \param bridge_closed Pointer to bool indication if bridge is closed not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) struct drxj_hi_cmd hi_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) u16 result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) /* check arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) if (bridge_closed == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) if (*bridge_closed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) /* I2C Bridge Functions - end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) /* Smart antenna Functions - begin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) * \fn int smart_ant_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) * \brief Initialize Smart Antenna.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) * \param pointer to struct drx_demod_instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) static int smart_ant_init(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) u16 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) /* Write magic word to enable pdr reg write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) /* init smart antenna */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) if (ext_attr->smart_ant_inverted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) /* config SMA_TX pin to smart antenna mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) rc = ctrl_set_uio_cfg(demod, &uio_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) /* Write magic word to disable pdr reg write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) u16 cur_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) /* Check param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) if (cmd == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) /* Wait until SCU command interface is ready to receive command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) if (cur_cmd != DRX_SCU_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) switch (cmd->parameter_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) /* do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) /* this number of parameters is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) /* Wait until SCU has processed command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) timeout = jiffies + msecs_to_jiffies(DRXJ_MAX_WAITTIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) while (time_is_after_jiffies(timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) if (cur_cmd == DRX_SCU_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) if (cur_cmd != DRX_SCU_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) /* read results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) if ((cmd->result_len > 0) && (cmd->result != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) s16 err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) switch (cmd->result_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) /* do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) /* this number of parameters is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) /* Check if an error was reported by SCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) err = cmd->result[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) /* check a few fixed error codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) if ((err == (s16) SCU_RAM_PARAM_0_RESULT_UNKSTD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) || (err == (s16) SCU_RAM_PARAM_0_RESULT_UNKCMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) || (err == (s16) SCU_RAM_PARAM_0_RESULT_INVPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) || (err == (s16) SCU_RAM_PARAM_0_RESULT_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) /* here it is assumed that negative means error, and positive no error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) else if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) * \fn int DRXJ_DAP_SCUAtomicReadWriteBlock()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) * \brief Basic access routine for SCU atomic read or write access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) * \param dev_addr pointer to i2c dev address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) * \param addr destination/source address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) * \param datasize size of data buffer in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) * \param data pointer to data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) * \return int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) * \retval 0 Success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) * \retval -EIO Timeout, I2C error, illegal bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) u8 *data, bool read_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) struct drxjscu_cmd scu_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) u16 set_param_parameters[18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) u16 cmd_result[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) /* Parameter check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) if (read_flag) { /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) set_param_parameters[0] = ((~(0x0080)) & datasize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) scu_cmd.parameter_len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) scu_cmd.result_len = datasize / 2 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) set_param_parameters[0] = 0x0080 | datasize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) for (i = 0; i < (datasize / 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) set_param_parameters[i + 2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) (data[2 * i] | (data[(2 * i) + 1] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) scu_cmd.parameter_len = datasize / 2 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) scu_cmd.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) scu_cmd.command =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) SCU_RAM_COMMAND_STANDARD_TOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) scu_cmd.result = cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) scu_cmd.parameter = set_param_parameters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) rc = scu_command(dev_addr, &scu_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) if (read_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) /* read data from buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) for (i = 0; i < (datasize / 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) data[2 * i] = (u8) (scu_cmd.result[i + 2] & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) data[(2 * i) + 1] = (u8) (scu_cmd.result[i + 2] >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) * \fn int DRXJ_DAP_AtomicReadReg16()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) * \brief Atomic read of 16 bits words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) u16 *data, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) u8 buf[2] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) u16 word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) word = (u16) (buf[0] + (buf[1] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) *data = word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) * \fn int drxj_dap_scu_atomic_write_reg16()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) * \brief Atomic read of 16 bits words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) u16 data, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) buf[0] = (u8) (data & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) buf[1] = (u8) ((data >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) * \brief Measure result of ADC synchronisation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) * \param demod demod instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) * \param count (returned) count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) * \retval 0 Success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) * \retval -EIO Failure: I2C error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) u16 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) /* Start measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) *count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) if (data == 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) *count = *count + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) if (data == 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) *count = *count + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) if (data == 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) *count = *count + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) * \brief Synchronize analog and digital clock domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) * \param demod demod instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) * \retval 0 Success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) * \retval -EIO Failure: I2C error or failure to synchronize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) * An IQM reset will also reset the results of this synchronization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) * After an IQM reset this routine needs to be called again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) static int adc_synchronization(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) u16 count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) rc = adc_sync_measurement(demod, &count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) if (count == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) /* Try sampling on a different edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) u16 clk_neg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) rc = adc_sync_measurement(demod, &count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) /* TODO: implement fallback scenarios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) if (count < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) /*== END AUXILIARY FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) /*== 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) * \fn int init_agc ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) * \brief Initialize AGC for all standards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) * \param demod instance of demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) * \param channel pointer to channel data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) static int init_agc(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) struct drx_common_attr *common_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) struct drxj_cfg_agc *p_agc_rf_settings = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) struct drxj_cfg_agc *p_agc_if_settings = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) u16 ingain_tgt_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) u16 clp_dir_to = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) u16 sns_sum_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) u16 clp_sum_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) u16 sns_dir_to = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) u16 ki_innergain_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) u16 agc_ki = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) u16 ki_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) u16 if_iaccu_hi_tgt_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) u16 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) u16 agc_ki_dgain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) u16 ki_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) u16 clp_ctrl_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) u16 agc_rf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) u16 agc_if = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) common_attr = (struct drx_common_attr *) demod->my_common_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) switch (ext_attr->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) clp_sum_max = 1023;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) clp_dir_to = (u16) (-9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) sns_sum_max = 1023;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) sns_dir_to = (u16) (-9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) ki_innergain_min = (u16) (-32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) ki_max = 0x032C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) agc_ki_dgain = 0xC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) if_iaccu_hi_tgt_min = 2047;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) ki_min = 0x0117;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) ingain_tgt_max = 16383;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) clp_ctrl_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) ingain_tgt_max = 5119;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) clp_sum_max = 1023;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) clp_dir_to = (u16) (-5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) sns_sum_max = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) sns_dir_to = (u16) (-3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) ki_innergain_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) ki_max = 0x0657;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) if_iaccu_hi_tgt_min = 2047;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) agc_ki_dgain = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) ki_min = 0x0117;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) clp_ctrl_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) p_agc_if_settings = &(ext_attr->qam_if_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) agc_ki &= 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) /* for new AGC interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) } /* Gain fed from inner to outer AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) } /* set to p_agc_settings->top before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) agc_rf = 0x800 + p_agc_rf_settings->cut_off_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) if (common_attr->tuner_rf_agc_pol == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) agc_rf = 0x87ff - agc_rf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) agc_if = 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) if (common_attr->tuner_if_agc_pol == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) agc_rf = 0x87ff - agc_rf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) /* Set/restore Ki DGAIN factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) data &= ~SCU_RAM_AGC_KI_DGAIN__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) * \fn int set_frequency ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) * \brief Set frequency shift.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) * \param demod instance of demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) * \param channel pointer to channel data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) * \param tuner_freq_offset residual frequency from tuner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) set_frequency(struct drx_demod_instance *demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) struct drx_channel *channel, s32 tuner_freq_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) struct drxj_data *ext_attr = demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) s32 sampling_frequency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) s32 frequency_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) s32 if_freq_actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) s32 rf_freq_residual = -1 * tuner_freq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) s32 adc_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) s32 intermediate_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) u32 iqm_fs_rate_ofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) bool adc_flip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) bool select_pos_image = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) bool rf_mirror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) bool tuner_mirror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) bool image_to_select = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) s32 fm_frequency_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) Program frequency shifter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) No need to account for mirroring on RF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) switch (ext_attr->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) case DRX_STANDARD_PAL_SECAM_LP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) select_pos_image = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) case DRX_STANDARD_FM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) /* After IQM FS sound carrier must appear at 4 Mhz in spect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) Sound carrier is already 3Mhz above centre frequency due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) to tuner setting so now add an extra shift of 1MHz... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) fm_frequency_shift = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) case DRX_STANDARD_NTSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) case DRX_STANDARD_PAL_SECAM_BG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) case DRX_STANDARD_PAL_SECAM_DK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) case DRX_STANDARD_PAL_SECAM_I:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) case DRX_STANDARD_PAL_SECAM_L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) select_pos_image = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) intermediate_freq = demod->my_common_attr->intermediate_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) sampling_frequency = demod->my_common_attr->sys_clock_freq / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) if (tuner_mirror)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) if_freq_actual = intermediate_freq + rf_freq_residual + fm_frequency_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) if (if_freq_actual > sampling_frequency / 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) /* adc mirrors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) adc_freq = sampling_frequency - if_freq_actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) adc_flip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) /* adc doesn't mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) adc_freq = if_freq_actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) adc_flip = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) frequency_shift = adc_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) image_to_select =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) (bool) (rf_mirror ^ tuner_mirror ^ adc_flip ^ select_pos_image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) iqm_fs_rate_ofs = frac28(frequency_shift, sampling_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) if (image_to_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) /* Program frequency shifter with tuner offset compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) /* frequency_shift += tuner_freq_offset; TODO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) * \fn int get_acc_pkt_err()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) * \brief Retrieve signal strength for VSB and QAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) * \param demod Pointer to demod instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) * \param packet_err Pointer to packet error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) * \retval 0 sig_strength contains valid data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) * \retval -EINVAL sig_strength is NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) * \retval -EIO Erroneous data, sig_strength contains invalid data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) #ifdef DRXJ_SIGNAL_ACCUM_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) static u16 pkt_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) static u16 last_pkt_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) u16 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) if (ext_attr->reset_pkt_err_acc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) last_pkt_err = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) pkt_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) ext_attr->reset_pkt_err_acc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) if (data < last_pkt_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) pkt_err += 0xffff - last_pkt_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) pkt_err += data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) pkt_err += (data - last_pkt_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) *packet_err = pkt_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) last_pkt_err = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) * \fn int set_agc_rf ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) * \brief Configure RF AGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) * \param demod instance of demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) * \param agc_settings AGC configuration structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) struct drxj_cfg_agc *p_agc_settings = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) struct drx_common_attr *common_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) drx_write_reg16func_t scu_wr16 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) drx_read_reg16func_t scu_rr16 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) common_attr = (struct drx_common_attr *) demod->my_common_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) if (atomic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) scu_rr16 = drxj_dap_scu_atomic_read_reg16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) scu_wr16 = drxj_dap_scu_atomic_write_reg16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) scu_rr16 = drxj_dap_read_reg16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) scu_wr16 = drxj_dap_write_reg16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) /* Configure AGC only if standard is currently active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) if ((ext_attr->standard == agc_settings->standard) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) (DRXJ_ISQAMSTD(ext_attr->standard) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) DRXJ_ISQAMSTD(agc_settings->standard)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) (DRXJ_ISATVSTD(ext_attr->standard) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) DRXJ_ISATVSTD(agc_settings->standard))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) u16 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) switch (agc_settings->ctrl_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) case DRX_AGC_CTRL_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) /* Enable RF AGC DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) /* Enable SCU RF AGC loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) data &= ~SCU_RAM_AGC_KI_RF__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) if (ext_attr->standard == DRX_STANDARD_8VSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) data |= (2 << SCU_RAM_AGC_KI_RF__B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) else if (DRXJ_ISQAMSTD(ext_attr->standard))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) data |= (5 << SCU_RAM_AGC_KI_RF__B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) data |= (4 << SCU_RAM_AGC_KI_RF__B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) if (common_attr->tuner_rf_agc_pol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) /* Set speed ( using complementary reduction value ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) if (agc_settings->standard == DRX_STANDARD_8VSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) p_agc_settings = &(ext_attr->vsb_if_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) else if (DRXJ_ISQAMSTD(agc_settings->standard))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) p_agc_settings = &(ext_attr->qam_if_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) else if (DRXJ_ISATVSTD(agc_settings->standard))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) p_agc_settings = &(ext_attr->atv_if_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) /* Set TOP, only if IF-AGC is in AUTO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) /* Cut-Off current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) case DRX_AGC_CTRL_USER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) /* Enable RF AGC DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) /* Disable SCU RF AGC loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) data &= ~SCU_RAM_AGC_KI_RF__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) if (common_attr->tuner_rf_agc_pol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) /* Write value to output pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) case DRX_AGC_CTRL_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) /* Disable RF AGC DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) /* Disable SCU RF AGC loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) data &= ~SCU_RAM_AGC_KI_RF__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) } /* switch ( agcsettings->ctrl_mode ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) /* Store rf agc settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) switch (agc_settings->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) ext_attr->vsb_rf_agc_cfg = *agc_settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) ext_attr->qam_rf_agc_cfg = *agc_settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) * \fn int set_agc_if ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) * \brief Configure If AGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) * \param demod instance of demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) * \param agc_settings AGC configuration structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) struct drxj_cfg_agc *p_agc_settings = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) struct drx_common_attr *common_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) drx_write_reg16func_t scu_wr16 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) drx_read_reg16func_t scu_rr16 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) common_attr = (struct drx_common_attr *) demod->my_common_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) if (atomic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) scu_rr16 = drxj_dap_scu_atomic_read_reg16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) scu_wr16 = drxj_dap_scu_atomic_write_reg16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) scu_rr16 = drxj_dap_read_reg16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) scu_wr16 = drxj_dap_write_reg16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) /* Configure AGC only if standard is currently active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) if ((ext_attr->standard == agc_settings->standard) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) (DRXJ_ISQAMSTD(ext_attr->standard) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) DRXJ_ISQAMSTD(agc_settings->standard)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) (DRXJ_ISATVSTD(ext_attr->standard) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) DRXJ_ISATVSTD(agc_settings->standard))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) u16 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) switch (agc_settings->ctrl_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) case DRX_AGC_CTRL_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) /* Enable IF AGC DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) /* Enable SCU IF AGC loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) data &= ~SCU_RAM_AGC_KI_IF__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) if (ext_attr->standard == DRX_STANDARD_8VSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) data |= (3 << SCU_RAM_AGC_KI_IF__B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) else if (DRXJ_ISQAMSTD(ext_attr->standard))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) data |= (6 << SCU_RAM_AGC_KI_IF__B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) data |= (5 << SCU_RAM_AGC_KI_IF__B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) if (common_attr->tuner_if_agc_pol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) /* Set speed (using complementary reduction value) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) if (agc_settings->standard == DRX_STANDARD_8VSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) p_agc_settings = &(ext_attr->vsb_rf_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) else if (DRXJ_ISQAMSTD(agc_settings->standard))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) p_agc_settings = &(ext_attr->qam_rf_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) else if (DRXJ_ISATVSTD(agc_settings->standard))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) p_agc_settings = &(ext_attr->atv_rf_agc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) /* Restore TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) case DRX_AGC_CTRL_USER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) /* Enable IF AGC DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) /* Disable SCU IF AGC loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) if (common_attr->tuner_if_agc_pol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) /* Write value to output pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) case DRX_AGC_CTRL_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) /* Disable If AGC DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) /* Disable SCU IF AGC loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) } /* switch ( agcsettings->ctrl_mode ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) /* always set the top to support configurations without if-loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) /* Store if agc settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) switch (agc_settings->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) ext_attr->vsb_if_agc_cfg = *agc_settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) ext_attr->qam_if_agc_cfg = *agc_settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) * \fn int set_iqm_af ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) * \brief Configure IQM AF registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) * \param demod instance of demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) * \param active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) static int set_iqm_af(struct drx_demod_instance *demod, bool active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) u16 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) /* Configure IQM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) if (!active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) /*== END 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) /*== 8VSB DATAPATH FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) * \fn int power_down_vsb ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) * \brief Powr down QAM related blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) * \param demod instance of demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) * \param channel pointer to channel data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) static int power_down_vsb(struct drx_demod_instance *demod, bool primary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) struct drxjscu_cmd cmd_scu = { /* command */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) /* parameter_len */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) /* result_len */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) /* *parameter */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) /* *result */ NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) struct drx_cfg_mpeg_output cfg_mpeg_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) u16 cmd_result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) STOP demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) reset of FEC and VSB HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) SCU_RAM_COMMAND_CMD_DEMOD_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) cmd_scu.parameter_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) cmd_scu.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) cmd_scu.parameter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) cmd_scu.result = &cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) rc = scu_command(dev_addr, &cmd_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) /* stop all comm_exec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) if (primary) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) rc = set_iqm_af(demod, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) cfg_mpeg_output.enable_mpeg_output = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) * \fn int set_vsb_leak_n_gain ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) * \brief Set ATSC demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) * \param demod instance of demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) static int set_vsb_leak_n_gain(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) static const u8 vsb_ffe_leak_gain_ram0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) DRXJ_16TO8(0x8), /* FFETRAINLKRATIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) DRXJ_16TO8(0x8), /* FFETRAINLKRATIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) DRXJ_16TO8(0x8), /* FFETRAINLKRATIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) DRXJ_16TO8(0xf), /* FFETRAINLKRATIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) DRXJ_16TO8(0xf), /* FFETRAINLKRATIO5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) DRXJ_16TO8(0xf), /* FFETRAINLKRATIO6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) DRXJ_16TO8(0xf), /* FFETRAINLKRATIO7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) DRXJ_16TO8(0xf), /* FFETRAINLKRATIO8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) DRXJ_16TO8(0xf), /* FFETRAINLKRATIO9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) DRXJ_16TO8(0x8), /* FFETRAINLKRATIO10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) DRXJ_16TO8(0x8), /* FFETRAINLKRATIO11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) DRXJ_16TO8(0x8), /* FFETRAINLKRATIO12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579) DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) DRXJ_16TO8(0x2020), /* FIRTRAINGAIN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) DRXJ_16TO8(0x2020), /* FIRTRAINGAIN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) DRXJ_16TO8(0x2020), /* FIRTRAINGAIN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) DRXJ_16TO8(0x4040), /* FIRTRAINGAIN4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) DRXJ_16TO8(0x4040), /* FIRTRAINGAIN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) DRXJ_16TO8(0x4040), /* FIRTRAINGAIN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) DRXJ_16TO8(0x4040), /* FIRTRAINGAIN7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) DRXJ_16TO8(0x4040), /* FIRTRAINGAIN8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) DRXJ_16TO8(0x4040), /* FIRTRAINGAIN9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) DRXJ_16TO8(0x2020), /* FIRTRAINGAIN10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) DRXJ_16TO8(0x2020), /* FIRTRAINGAIN11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) DRXJ_16TO8(0x2020), /* FIRTRAINGAIN12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) DRXJ_16TO8(0x0808), /* FIRRCA1GAIN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) DRXJ_16TO8(0x0808), /* FIRRCA1GAIN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) DRXJ_16TO8(0x0808), /* FIRRCA1GAIN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) DRXJ_16TO8(0x1010), /* FIRRCA1GAIN4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) DRXJ_16TO8(0x1010), /* FIRRCA1GAIN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) DRXJ_16TO8(0x1010), /* FIRRCA1GAIN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) DRXJ_16TO8(0x1010), /* FIRRCA1GAIN7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) DRXJ_16TO8(0x1010) /* FIRRCA1GAIN8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) static const u8 vsb_ffe_leak_gain_ram1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) DRXJ_16TO8(0x1010), /* FIRRCA1GAIN9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) DRXJ_16TO8(0x0808), /* FIRRCA1GAIN10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) DRXJ_16TO8(0x0808), /* FIRRCA1GAIN11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) DRXJ_16TO8(0x0808), /* FIRRCA1GAIN12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) DRXJ_16TO8(0x0808), /* FIRRCA2GAIN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) DRXJ_16TO8(0x0808), /* FIRRCA2GAIN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) DRXJ_16TO8(0x0808), /* FIRRCA2GAIN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) DRXJ_16TO8(0x1010), /* FIRRCA2GAIN4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) DRXJ_16TO8(0x1010), /* FIRRCA2GAIN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) DRXJ_16TO8(0x1010), /* FIRRCA2GAIN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) DRXJ_16TO8(0x1010), /* FIRRCA2GAIN7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) DRXJ_16TO8(0x1010), /* FIRRCA2GAIN8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) DRXJ_16TO8(0x1010), /* FIRRCA2GAIN9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) DRXJ_16TO8(0x0808), /* FIRRCA2GAIN10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) DRXJ_16TO8(0x0808), /* FIRRCA2GAIN11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) DRXJ_16TO8(0x0808), /* FIRRCA2GAIN12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) DRXJ_16TO8(0x0303), /* FIRDDM1GAIN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) DRXJ_16TO8(0x0303), /* FIRDDM1GAIN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) DRXJ_16TO8(0x0303), /* FIRDDM1GAIN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) DRXJ_16TO8(0x0606), /* FIRDDM1GAIN4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) DRXJ_16TO8(0x0606), /* FIRDDM1GAIN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) DRXJ_16TO8(0x0606), /* FIRDDM1GAIN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) DRXJ_16TO8(0x0606), /* FIRDDM1GAIN7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) DRXJ_16TO8(0x0606), /* FIRDDM1GAIN8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) DRXJ_16TO8(0x0606), /* FIRDDM1GAIN9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) DRXJ_16TO8(0x0303), /* FIRDDM1GAIN10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) DRXJ_16TO8(0x0303), /* FIRDDM1GAIN11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) DRXJ_16TO8(0x0303), /* FIRDDM1GAIN12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) DRXJ_16TO8(0x0303), /* FIRDDM2GAIN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) DRXJ_16TO8(0x0303), /* FIRDDM2GAIN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) DRXJ_16TO8(0x0303), /* FIRDDM2GAIN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) DRXJ_16TO8(0x0505), /* FIRDDM2GAIN4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) DRXJ_16TO8(0x0505), /* FIRDDM2GAIN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) DRXJ_16TO8(0x0505), /* FIRDDM2GAIN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) DRXJ_16TO8(0x0505), /* FIRDDM2GAIN7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) DRXJ_16TO8(0x0505), /* FIRDDM2GAIN8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) DRXJ_16TO8(0x0505), /* FIRDDM2GAIN9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) DRXJ_16TO8(0x0303), /* FIRDDM2GAIN10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) DRXJ_16TO8(0x0303), /* FIRDDM2GAIN11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) DRXJ_16TO8(0x0303), /* FIRDDM2GAIN12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) DRXJ_16TO8(0x001f), /* DFETRAINLKRATIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) DRXJ_16TO8(0x01ff), /* DFERCA1TRAINLKRATIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) DRXJ_16TO8(0x01ff), /* DFERCA1DATALKRATIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) DRXJ_16TO8(0x004f), /* DFERCA2TRAINLKRATIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) DRXJ_16TO8(0x004f), /* DFERCA2DATALKRATIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) DRXJ_16TO8(0x01ff), /* DFEDDM1TRAINLKRATIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) DRXJ_16TO8(0x01ff), /* DFEDDM1DATALKRATIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) DRXJ_16TO8(0x0352), /* DFEDDM2TRAINLKRATIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) DRXJ_16TO8(0x0352), /* DFEDDM2DATALKRATIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) DRXJ_16TO8(0x0000), /* DFETRAINGAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) DRXJ_16TO8(0x2020), /* DFERCA1GAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) DRXJ_16TO8(0x1010), /* DFERCA2GAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) DRXJ_16TO8(0x1818), /* DFEDDM1GAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) DRXJ_16TO8(0x1212) /* DFEDDM2GAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) * \fn int set_vsb()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) * \brief Set 8VSB demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) * \param demod instance of demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) static int set_vsb(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) struct drx_common_attr *common_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) struct drxjscu_cmd cmd_scu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) u16 cmd_result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) u16 cmd_param = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) static const u8 vsb_taps_re[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) DRXJ_16TO8(-2), /* re0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) DRXJ_16TO8(4), /* re1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) DRXJ_16TO8(1), /* re2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) DRXJ_16TO8(-4), /* re3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) DRXJ_16TO8(1), /* re4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) DRXJ_16TO8(4), /* re5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) DRXJ_16TO8(-3), /* re6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) DRXJ_16TO8(-3), /* re7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) DRXJ_16TO8(6), /* re8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) DRXJ_16TO8(1), /* re9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) DRXJ_16TO8(-9), /* re10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) DRXJ_16TO8(3), /* re11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) DRXJ_16TO8(12), /* re12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) DRXJ_16TO8(-9), /* re13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) DRXJ_16TO8(-15), /* re14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) DRXJ_16TO8(17), /* re15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) DRXJ_16TO8(19), /* re16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) DRXJ_16TO8(-29), /* re17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) DRXJ_16TO8(-22), /* re18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) DRXJ_16TO8(45), /* re19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) DRXJ_16TO8(25), /* re20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) DRXJ_16TO8(-70), /* re21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) DRXJ_16TO8(-28), /* re22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) DRXJ_16TO8(111), /* re23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) DRXJ_16TO8(30), /* re24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) DRXJ_16TO8(-201), /* re25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752) DRXJ_16TO8(-31), /* re26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) DRXJ_16TO8(629) /* re27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) common_attr = (struct drx_common_attr *) demod->my_common_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) /* stop all comm_exec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761) rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) /* reset demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) cmd_scu.parameter_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) cmd_scu.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) cmd_scu.parameter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) cmd_scu.result = &cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) rc = scu_command(dev_addr, &cmd_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) ext_attr->iqm_rc_rate_ofs = 0x00AD0D79;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) } /* set higher threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908) } /* burst detection on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) } /* drop thresholds by 1 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) } /* drop thresholds by 2 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923) } /* cma on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928) } /* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) /* Initialize the FEC Subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937) u16 fec_oc_snc_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) /* output data even when not locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) /* set clip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972) /* no transparent, no A&C framing; parity is set in mpegoutput */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) u16 fec_oc_reg_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991) } /* timeout counter for restarting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992) rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001) } /* bypass disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002) /* initialize RS packet error measurement parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) /* init measurement period of MER/SER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) /* B-Input to ADC, PGA+filter in standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042) if (!ext_attr->has_lna) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050) /* turn on IQMAF. It has to be in front of setAgc**() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) rc = set_iqm_af(demod, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056) rc = adc_synchronization(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062) rc = init_agc(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072) rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) of only the gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080) struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082) vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083) rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) /* Mpeg output has to be in front of FEC active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) rc = set_mpegtei_handling(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) rc = bit_reverse_mpeg_output(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) rc = set_mpeg_start_width(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112) /* TODO: move to set_standard after hardware reset value problem is solved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) /* Configure initial MPEG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) struct drx_cfg_mpeg_output cfg_mpeg_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117) cfg_mpeg_output.enable_mpeg_output = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) /* TBD: what parameters should be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127) cmd_param = 0x00; /* Default mode AGC on, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128) cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129) | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130) cmd_scu.parameter_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131) cmd_scu.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132) cmd_scu.parameter = &cmd_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) cmd_scu.result = &cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) rc = scu_command(dev_addr, &cmd_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181) /* start demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183) | SCU_RAM_COMMAND_CMD_DEMOD_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) cmd_scu.parameter_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185) cmd_scu.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) cmd_scu.parameter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187) cmd_scu.result = &cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) rc = scu_command(dev_addr, &cmd_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199) rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216) * \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217) * \brief Get the values of packet error in 8VSB mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) * \return Error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220) static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221) u32 *pck_errs, u32 *pck_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224) u16 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) u16 period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) u16 prescale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) u16 packet_errors_mant = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228) u16 packet_errors_exp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235) packet_errors_mant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) packet_errors_exp = (data & FEC_RS_NR_FAILURES_EXP__M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237) >> FEC_RS_NR_FAILURES_EXP__B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) period = FEC_RS_MEASUREMENT_PERIOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) prescale = FEC_RS_MEASUREMENT_PRESCALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240) /* packet error rate = (error packet number) per second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241) /* 77.3 us is time for per packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242) if (period * prescale == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243) pr_err("error: period and/or prescale is zero!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) *pck_errs = packet_errors_mant * (1 << packet_errors_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) *pck_count = period * prescale * 77;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255) * \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) * \brief Get the values of ber in VSB mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257) * \return Error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) u32 *ber, u32 *cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263) u16 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264) u16 period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) u16 prescale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) u16 bit_errors_mant = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267) u16 bit_errors_exp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269) rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274) period = FEC_RS_MEASUREMENT_PERIOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275) prescale = FEC_RS_MEASUREMENT_PRESCALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277) bit_errors_mant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278) bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279) >> FEC_RS_NR_BIT_ERRORS_EXP__B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) *cnt = period * prescale * 207 * ((bit_errors_exp > 2) ? 1 : 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283) if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284) *ber = (*cnt) * 26570;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) if (period * prescale == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287) pr_err("error: period and/or prescale is zero!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) *ber = bit_errors_mant << ((bit_errors_exp > 2) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291) (bit_errors_exp - 3) : bit_errors_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) * \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301) * \brief Get the values of ber in VSB mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302) * \return Error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304) static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305) u32 *ber, u32 *cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307) u16 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310) rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) *ber = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) *cnt = VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) * \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) * \brief Get the values of MER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324) * \return Error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329) u16 data_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331) rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336) *mer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337) (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) /*== END 8VSB DATAPATH FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) /*== QAM DATAPATH FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356) * \fn int power_down_qam ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) * \brief Powr down QAM related blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358) * \param demod instance of demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359) * \param channel pointer to channel data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) static int power_down_qam(struct drx_demod_instance *demod, bool primary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364) struct drxjscu_cmd cmd_scu = { /* command */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365) /* parameter_len */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366) /* result_len */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367) /* *parameter */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) /* *result */ NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) struct drx_cfg_mpeg_output cfg_mpeg_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373) struct drx_common_attr *common_attr = demod->my_common_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) u16 cmd_result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377) STOP demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) resets IQM, QAM and FEC HW blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) /* stop all comm_exec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381) rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392) cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393) SCU_RAM_COMMAND_CMD_DEMOD_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394) cmd_scu.parameter_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) cmd_scu.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396) cmd_scu.parameter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) cmd_scu.result = &cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) rc = scu_command(dev_addr, &cmd_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404) if (primary) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405) rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) rc = set_iqm_af(demod, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416) rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421) rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426) rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431) rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443) memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) cfg_mpeg_output.enable_mpeg_output = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446) rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460) * \fn int set_qam_measurement ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461) * \brief Setup of the QAM Measuremnt intervals for signal quality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462) * \param demod instance of demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) * \param constellation current constellation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) * NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467) * Take into account that for certain settings the errorcounters can overflow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) * The implementation does not check this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) * TODO: overriding the ext_attr->fec_bits_desired by constellation dependent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) * constants to get a measurement period of approx. 1 sec. Remove fec_bits_desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472) * field ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) set_qam_measurement(struct drx_demod_instance *demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) enum drx_modulation constellation, u32 symbol_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481) struct drxj_data *ext_attr = NULL; /* Global data container for DRXJ specific data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) u32 fec_bits_desired = 0; /* BER accounting period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) u16 fec_rs_plen = 0; /* defines RS BER measurement period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) u32 fec_rs_period = 0; /* Value for corresponding I2C register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) u32 fec_rs_bit_cnt = 0; /* Actual precise amount of bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) u32 fec_oc_snc_fail_period = 0; /* Value for corresponding I2C register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) u32 qam_vd_period = 0; /* Value for corresponding I2C register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) u32 qam_vd_bit_cnt = 0; /* Actual precise amount of bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491) u16 fec_vd_plen = 0; /* no of trellis symbols: VD SER measur period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) fec_bits_desired = ext_attr->fec_bits_desired;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) fec_rs_prescale = ext_attr->fec_rs_prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) switch (constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) case DRX_CONSTELLATION_QAM16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) fec_bits_desired = 4 * symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) case DRX_CONSTELLATION_QAM32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505) fec_bits_desired = 5 * symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) fec_bits_desired = 6 * symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) case DRX_CONSTELLATION_QAM128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511) fec_bits_desired = 7 * symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514) fec_bits_desired = 8 * symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) /* Parameters for Reed-Solomon Decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521) /* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) /* rs_bit_cnt = fecrs_period*fecrs_prescale*plen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) /* result is within 32 bit arithmetic -> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) /* no need for mult or frac functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) /* TODO: use constant instead of calculation and remove the fec_rs_plen in ext_attr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) switch (ext_attr->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530) fec_rs_plen = 204 * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) fec_rs_plen = 128 * 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539) ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540) fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen; /* temp storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) if (fec_rs_bit_cnt == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542) pr_err("error: fec_rs_bit_cnt is zero!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545) fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1; /* ceil */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546) if (ext_attr->standard != DRX_STANDARD_ITU_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) fec_oc_snc_fail_period = fec_rs_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549) /* limit to max 16 bit value (I2C register width) if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550) if (fec_rs_period > 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) fec_rs_period = 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) /* write corresponding registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554) switch (ext_attr->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) switch (constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) fec_rs_period = 31581;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562) fec_oc_snc_fail_period = 17932;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) fec_rs_period = 45446;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) fec_oc_snc_fail_period = 25805;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591) ext_attr->fec_rs_period = (u16) fec_rs_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592) ext_attr->fec_rs_prescale = fec_rs_prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609) if (ext_attr->standard == DRX_STANDARD_ITU_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610) /* Parameters for Viterbi Decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612) /* (qamvd_prescale*plen*(qam_constellation+1))) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613) /* vd_bit_cnt = qamvd_period*qamvd_prescale*plen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614) /* result is within 32 bit arithmetic -> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615) /* no need for mult or frac functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617) /* a(8 bit) * b(8 bit) = 16 bit result => mult32 not needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618) fec_vd_plen = ext_attr->fec_vd_plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619) qam_vd_prescale = ext_attr->qam_vd_prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620) qam_vd_bit_cnt = qam_vd_prescale * fec_vd_plen; /* temp storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622) switch (constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624) /* a(16 bit) * b(4 bit) = 20 bit result => mult32 not needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625) qam_vd_period =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626) qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM64 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627) * (QAM_TOP_CONSTELLATION_QAM64 + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630) /* a(16 bit) * b(5 bit) = 21 bit result => mult32 not needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) qam_vd_period =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632) qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM256 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633) * (QAM_TOP_CONSTELLATION_QAM256 + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638) if (qam_vd_period == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639) pr_err("error: qam_vd_period is zero!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642) qam_vd_period = fec_bits_desired / qam_vd_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643) /* limit to max 16 bit value (I2C register width) if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644) if (qam_vd_period > 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) qam_vd_period = 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647) /* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648) qam_vd_bit_cnt *= qam_vd_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650) rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655) rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) ext_attr->qam_vd_period = (u16) qam_vd_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661) ext_attr->qam_vd_prescale = qam_vd_prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672) * \fn int set_qam16 ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673) * \brief QAM16 specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674) * \param demod instance of demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677) static int set_qam16(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681) static const u8 qam_dq_qual_fun[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682) DRXJ_16TO8(2), /* fun0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683) DRXJ_16TO8(2), /* fun1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684) DRXJ_16TO8(2), /* fun2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685) DRXJ_16TO8(2), /* fun3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686) DRXJ_16TO8(3), /* fun4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687) DRXJ_16TO8(3), /* fun5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689) static const u8 qam_eq_cma_rad[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) DRXJ_16TO8(13517), /* RAD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691) DRXJ_16TO8(13517), /* RAD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692) DRXJ_16TO8(13517), /* RAD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693) DRXJ_16TO8(13517), /* RAD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694) DRXJ_16TO8(13517), /* RAD4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695) DRXJ_16TO8(13517), /* RAD5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698) rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703) rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6725) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6726) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6727) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6729) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6730) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6731) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6732) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6734) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6735) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6736) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6737) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6740) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6741) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6742) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6743) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6745) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6746) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6747) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6748) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6750) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6751) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6752) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6753) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6756) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6757) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6758) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6759) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6761) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6762) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6763) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6764) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6766) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6767) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6768) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6769) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6771) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6772) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6773) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6774) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6776) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6777) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6778) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6779) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6781) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6782) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6783) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6784) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6786) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6787) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6788) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6789) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6792) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6793) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6794) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6795) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6797) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6798) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6799) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6800) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6802) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6803) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6804) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6805) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6807) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6808) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6809) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6810) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6812) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6813) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6814) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6815) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6817) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6818) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6819) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6820) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6822) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6823) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6824) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6825) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6827) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6828) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6829) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6830) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6832) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6833) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6834) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6835) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6837) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6838) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6839) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6840) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6842) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6843) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6844) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6845) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6847) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6848) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6849) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6850) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6852) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6853) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6854) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6855) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6857) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6858) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6859) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6860) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6862) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6863) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6864) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6865) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6867) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6868) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6869) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6870) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6872) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6873) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6874) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6875) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6877) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6878) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6879) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6880) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6882) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6883) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6884) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6885) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6887) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6888) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6889) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6890) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6893) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6894) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6895) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6896) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6900) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6901) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6904) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6906) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6907) * \fn int set_qam32 ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6908) * \brief QAM32 specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6909) * \param demod instance of demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6910) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6911) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6912) static int set_qam32(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6914) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6915) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6916) static const u8 qam_dq_qual_fun[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6917) DRXJ_16TO8(3), /* fun0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6918) DRXJ_16TO8(3), /* fun1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6919) DRXJ_16TO8(3), /* fun2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6920) DRXJ_16TO8(3), /* fun3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6921) DRXJ_16TO8(4), /* fun4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6922) DRXJ_16TO8(4), /* fun5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6924) static const u8 qam_eq_cma_rad[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6925) DRXJ_16TO8(6707), /* RAD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6926) DRXJ_16TO8(6707), /* RAD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6927) DRXJ_16TO8(6707), /* RAD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6928) DRXJ_16TO8(6707), /* RAD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6929) DRXJ_16TO8(6707), /* RAD4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6930) DRXJ_16TO8(6707), /* RAD5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6933) rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6934) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6935) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6936) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6938) rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6939) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6940) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6941) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6944) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6945) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6946) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6947) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6949) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6950) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6951) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6952) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6954) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6955) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6956) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6957) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6959) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6960) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6961) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6962) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6964) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6965) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6966) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6967) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6969) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6970) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6971) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6972) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6975) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6976) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6977) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6978) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6980) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6981) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6982) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6983) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6985) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6986) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6987) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6988) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6991) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6992) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6993) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6994) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6996) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6997) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6998) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6999) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7001) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7002) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7003) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7004) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7006) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7007) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7008) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7009) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7011) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7012) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7013) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7014) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7016) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7017) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7018) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7019) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7021) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7022) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7023) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7024) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7027) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7028) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7029) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7030) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7032) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7033) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7034) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7035) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7037) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7038) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7039) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7040) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7042) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7043) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7044) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7045) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7047) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7048) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7049) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7050) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7052) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7053) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7054) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7055) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7057) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7058) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7059) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7060) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7062) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7063) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7064) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7065) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7067) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7068) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7069) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7070) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7072) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7073) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7074) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7075) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7077) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7078) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7079) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7080) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7082) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7083) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7084) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7085) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7087) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7088) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7089) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7090) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7092) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7093) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7094) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7095) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7097) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7098) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7099) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7100) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7102) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7103) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7104) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7105) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7107) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7108) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7109) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7110) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7112) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7113) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7114) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7115) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7117) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7118) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7119) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7120) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7122) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7123) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7124) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7125) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7128) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7129) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7130) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7131) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7135) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7136) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7139) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7142) * \fn int set_qam64 ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7143) * \brief QAM64 specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7144) * \param demod instance of demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7145) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7147) static int set_qam64(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7149) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7150) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7151) static const u8 qam_dq_qual_fun[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7152) /* this is hw reset value. no necessary to re-write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7153) DRXJ_16TO8(4), /* fun0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7154) DRXJ_16TO8(4), /* fun1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7155) DRXJ_16TO8(4), /* fun2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7156) DRXJ_16TO8(4), /* fun3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7157) DRXJ_16TO8(6), /* fun4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7158) DRXJ_16TO8(6), /* fun5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7160) static const u8 qam_eq_cma_rad[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7161) DRXJ_16TO8(13336), /* RAD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7162) DRXJ_16TO8(12618), /* RAD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7163) DRXJ_16TO8(11988), /* RAD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7164) DRXJ_16TO8(13809), /* RAD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7165) DRXJ_16TO8(13809), /* RAD4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7166) DRXJ_16TO8(15609), /* RAD5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7169) rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7170) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7171) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7172) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7174) rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7175) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7176) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7177) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7180) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7181) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7182) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7183) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7185) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7186) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7187) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7188) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7190) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7191) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7192) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7193) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7195) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7196) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7197) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7198) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7200) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7201) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7202) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7203) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7205) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7206) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7207) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7208) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7211) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7212) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7213) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7214) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7216) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7217) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7218) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7219) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7221) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7222) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7223) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7224) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7227) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7228) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7229) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7230) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7232) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7233) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7234) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7235) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7237) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7238) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7239) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7240) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7242) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7243) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7244) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7245) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7247) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7248) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7249) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7250) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7252) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7253) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7254) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7255) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7257) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7258) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7259) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7260) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7263) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7264) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7265) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7266) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7268) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7269) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7270) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7271) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7273) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7274) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7275) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7276) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7278) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7279) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7280) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7281) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7283) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7284) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7285) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7286) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7288) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7289) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7290) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7291) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7293) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7294) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7295) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7296) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7298) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7299) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7300) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7301) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7303) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7304) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7305) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7306) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7308) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7309) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7310) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7311) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7313) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7314) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7315) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7316) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7318) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7319) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7320) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7321) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7323) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7324) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7325) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7326) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7328) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7329) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7330) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7331) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7333) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7334) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7335) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7336) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7338) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7339) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7340) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7341) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7343) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7344) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7345) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7346) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7348) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7349) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7350) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7351) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7353) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7354) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7355) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7356) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7358) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7359) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7360) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7361) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7364) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7365) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7366) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7367) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7371) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7372) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7375) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7378) * \fn int set_qam128 ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7379) * \brief QAM128 specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7380) * \param demod: instance of demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7381) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7383) static int set_qam128(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7385) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7386) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7387) static const u8 qam_dq_qual_fun[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7388) DRXJ_16TO8(6), /* fun0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7389) DRXJ_16TO8(6), /* fun1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7390) DRXJ_16TO8(6), /* fun2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7391) DRXJ_16TO8(6), /* fun3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7392) DRXJ_16TO8(9), /* fun4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7393) DRXJ_16TO8(9), /* fun5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7395) static const u8 qam_eq_cma_rad[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7396) DRXJ_16TO8(6164), /* RAD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7397) DRXJ_16TO8(6598), /* RAD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7398) DRXJ_16TO8(6394), /* RAD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7399) DRXJ_16TO8(6409), /* RAD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7400) DRXJ_16TO8(6656), /* RAD4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7401) DRXJ_16TO8(7238), /* RAD5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7404) rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7405) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7406) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7407) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7409) rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7410) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7411) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7412) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7415) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7416) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7417) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7418) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7420) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7421) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7422) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7423) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7425) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7426) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7427) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7428) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7430) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7431) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7432) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7433) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7435) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7436) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7437) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7438) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7440) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7441) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7442) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7443) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7446) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7447) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7448) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7449) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7451) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7452) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7453) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7454) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7456) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7457) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7458) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7459) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7462) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7463) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7464) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7465) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7467) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7468) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7469) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7470) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7472) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7473) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7474) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7475) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7477) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7478) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7479) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7480) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7482) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7483) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7484) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7485) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7487) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7488) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7489) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7490) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7492) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7493) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7494) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7495) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7498) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7499) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7500) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7501) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7503) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7504) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7505) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7506) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7508) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7509) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7510) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7511) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7513) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7514) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7515) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7516) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7518) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7519) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7520) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7521) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7523) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7524) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7525) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7526) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7528) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7529) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7530) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7531) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7533) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7534) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7535) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7536) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7538) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7539) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7540) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7541) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7543) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7544) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7545) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7546) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7548) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7549) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7550) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7551) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7553) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7554) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7555) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7556) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7558) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7559) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7560) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7561) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7563) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7564) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7565) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7566) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7568) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7569) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7570) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7571) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7573) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7574) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7575) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7576) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7578) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7579) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7580) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7581) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7583) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7584) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7585) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7586) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7588) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7589) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7590) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7591) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7593) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7594) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7595) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7596) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7599) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7600) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7601) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7602) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7606) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7607) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7610) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7613) * \fn int set_qam256 ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7614) * \brief QAM256 specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7615) * \param demod: instance of demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7616) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7618) static int set_qam256(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7620) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7621) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7622) static const u8 qam_dq_qual_fun[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7623) DRXJ_16TO8(8), /* fun0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7624) DRXJ_16TO8(8), /* fun1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7625) DRXJ_16TO8(8), /* fun2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7626) DRXJ_16TO8(8), /* fun3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7627) DRXJ_16TO8(12), /* fun4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7628) DRXJ_16TO8(12), /* fun5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7630) static const u8 qam_eq_cma_rad[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7631) DRXJ_16TO8(12345), /* RAD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7632) DRXJ_16TO8(12345), /* RAD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7633) DRXJ_16TO8(13626), /* RAD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7634) DRXJ_16TO8(12931), /* RAD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7635) DRXJ_16TO8(14719), /* RAD4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7636) DRXJ_16TO8(15356), /* RAD5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7639) rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7640) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7641) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7642) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7644) rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7645) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7646) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7647) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7650) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7651) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7652) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7653) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7655) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7656) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7657) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7658) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7660) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7661) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7662) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7663) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7665) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7666) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7667) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7668) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7670) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7671) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7672) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7673) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7675) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7676) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7677) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7678) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7681) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7682) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7683) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7684) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7686) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7687) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7688) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7689) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7691) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7692) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7693) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7694) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7697) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7698) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7699) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7700) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7702) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7703) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7704) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7705) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7707) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7708) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7709) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7710) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7712) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7713) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7714) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7715) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7717) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7718) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7719) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7720) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7722) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7723) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7724) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7725) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7727) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7728) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7729) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7730) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7733) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7734) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7735) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7736) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7738) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7739) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7740) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7741) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7743) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7744) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7745) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7746) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7748) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7749) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7750) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7751) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7753) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7754) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7755) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7756) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7758) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7759) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7760) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7761) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7763) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7764) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7765) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7766) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7768) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7769) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7770) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7771) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7773) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7774) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7775) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7776) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7778) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7779) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7780) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7781) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7783) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7784) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7785) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7786) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7788) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7789) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7790) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7791) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7793) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7794) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7795) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7796) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7798) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7799) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7800) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7801) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7803) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7804) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7805) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7806) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7808) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7809) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7810) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7811) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7813) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7814) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7815) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7816) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7818) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7819) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7820) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7821) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7823) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7824) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7825) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7826) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7828) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7829) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7830) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7831) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7834) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7835) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7836) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7837) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7840) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7841) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7842) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7845) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7846) #define QAM_SET_OP_ALL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7847) #define QAM_SET_OP_CONSTELLATION 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7848) #define QAM_SET_OP_SPECTRUM 0X4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7850) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7851) * \fn int set_qam ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7852) * \brief Set QAM demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7853) * \param demod: instance of demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7854) * \param channel: pointer to channel data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7855) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7856) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7857) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7858) set_qam(struct drx_demod_instance *demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7859) struct drx_channel *channel, s32 tuner_freq_offset, u32 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7861) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7862) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7863) struct drx_common_attr *common_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7864) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7865) u32 adc_frequency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7866) u32 iqm_rc_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7867) u16 cmd_result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7868) u16 lc_symbol_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7869) u16 iqm_rc_stretch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7870) u16 set_env_parameters = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7871) u16 set_param_parameters[2] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7872) struct drxjscu_cmd cmd_scu = { /* command */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7873) /* parameter_len */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7874) /* result_len */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7875) /* parameter */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7876) /* result */ NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7878) static const u8 qam_a_taps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7879) DRXJ_16TO8(-1), /* re0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7880) DRXJ_16TO8(1), /* re1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7881) DRXJ_16TO8(1), /* re2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7882) DRXJ_16TO8(-1), /* re3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7883) DRXJ_16TO8(-1), /* re4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7884) DRXJ_16TO8(2), /* re5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7885) DRXJ_16TO8(1), /* re6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7886) DRXJ_16TO8(-2), /* re7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7887) DRXJ_16TO8(0), /* re8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7888) DRXJ_16TO8(3), /* re9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7889) DRXJ_16TO8(-1), /* re10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7890) DRXJ_16TO8(-3), /* re11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7891) DRXJ_16TO8(4), /* re12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7892) DRXJ_16TO8(1), /* re13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7893) DRXJ_16TO8(-8), /* re14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7894) DRXJ_16TO8(4), /* re15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7895) DRXJ_16TO8(13), /* re16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7896) DRXJ_16TO8(-13), /* re17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7897) DRXJ_16TO8(-19), /* re18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7898) DRXJ_16TO8(28), /* re19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7899) DRXJ_16TO8(25), /* re20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7900) DRXJ_16TO8(-53), /* re21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7901) DRXJ_16TO8(-31), /* re22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7902) DRXJ_16TO8(96), /* re23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7903) DRXJ_16TO8(37), /* re24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7904) DRXJ_16TO8(-190), /* re25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7905) DRXJ_16TO8(-40), /* re26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7906) DRXJ_16TO8(619) /* re27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7908) static const u8 qam_b64_taps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7909) DRXJ_16TO8(0), /* re0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7910) DRXJ_16TO8(-2), /* re1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7911) DRXJ_16TO8(1), /* re2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7912) DRXJ_16TO8(2), /* re3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7913) DRXJ_16TO8(-2), /* re4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7914) DRXJ_16TO8(0), /* re5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7915) DRXJ_16TO8(4), /* re6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7916) DRXJ_16TO8(-2), /* re7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7917) DRXJ_16TO8(-4), /* re8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7918) DRXJ_16TO8(4), /* re9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7919) DRXJ_16TO8(3), /* re10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7920) DRXJ_16TO8(-6), /* re11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7921) DRXJ_16TO8(0), /* re12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7922) DRXJ_16TO8(6), /* re13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7923) DRXJ_16TO8(-5), /* re14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7924) DRXJ_16TO8(-3), /* re15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7925) DRXJ_16TO8(11), /* re16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7926) DRXJ_16TO8(-4), /* re17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7927) DRXJ_16TO8(-19), /* re18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7928) DRXJ_16TO8(19), /* re19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7929) DRXJ_16TO8(28), /* re20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7930) DRXJ_16TO8(-45), /* re21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7931) DRXJ_16TO8(-36), /* re22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7932) DRXJ_16TO8(90), /* re23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7933) DRXJ_16TO8(42), /* re24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7934) DRXJ_16TO8(-185), /* re25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7935) DRXJ_16TO8(-46), /* re26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7936) DRXJ_16TO8(614) /* re27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7938) static const u8 qam_b256_taps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7939) DRXJ_16TO8(-2), /* re0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7940) DRXJ_16TO8(4), /* re1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7941) DRXJ_16TO8(1), /* re2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7942) DRXJ_16TO8(-4), /* re3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7943) DRXJ_16TO8(0), /* re4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7944) DRXJ_16TO8(4), /* re5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7945) DRXJ_16TO8(-2), /* re6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7946) DRXJ_16TO8(-4), /* re7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7947) DRXJ_16TO8(5), /* re8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7948) DRXJ_16TO8(2), /* re9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7949) DRXJ_16TO8(-8), /* re10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7950) DRXJ_16TO8(2), /* re11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7951) DRXJ_16TO8(11), /* re12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7952) DRXJ_16TO8(-8), /* re13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7953) DRXJ_16TO8(-15), /* re14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7954) DRXJ_16TO8(16), /* re15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7955) DRXJ_16TO8(19), /* re16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7956) DRXJ_16TO8(-27), /* re17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7957) DRXJ_16TO8(-22), /* re18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7958) DRXJ_16TO8(44), /* re19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7959) DRXJ_16TO8(26), /* re20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7960) DRXJ_16TO8(-69), /* re21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7961) DRXJ_16TO8(-28), /* re22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7962) DRXJ_16TO8(110), /* re23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7963) DRXJ_16TO8(31), /* re24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7964) DRXJ_16TO8(-201), /* re25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7965) DRXJ_16TO8(-32), /* re26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7966) DRXJ_16TO8(628) /* re27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7968) static const u8 qam_c_taps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7969) DRXJ_16TO8(-3), /* re0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7970) DRXJ_16TO8(3), /* re1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7971) DRXJ_16TO8(2), /* re2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7972) DRXJ_16TO8(-4), /* re3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7973) DRXJ_16TO8(0), /* re4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7974) DRXJ_16TO8(4), /* re5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7975) DRXJ_16TO8(-1), /* re6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7976) DRXJ_16TO8(-4), /* re7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7977) DRXJ_16TO8(3), /* re8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7978) DRXJ_16TO8(3), /* re9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7979) DRXJ_16TO8(-5), /* re10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7980) DRXJ_16TO8(0), /* re11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7981) DRXJ_16TO8(9), /* re12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7982) DRXJ_16TO8(-4), /* re13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7983) DRXJ_16TO8(-12), /* re14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7984) DRXJ_16TO8(10), /* re15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7985) DRXJ_16TO8(16), /* re16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7986) DRXJ_16TO8(-21), /* re17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7987) DRXJ_16TO8(-20), /* re18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7988) DRXJ_16TO8(37), /* re19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7989) DRXJ_16TO8(25), /* re20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7990) DRXJ_16TO8(-62), /* re21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7991) DRXJ_16TO8(-28), /* re22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7992) DRXJ_16TO8(105), /* re23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7993) DRXJ_16TO8(31), /* re24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7994) DRXJ_16TO8(-197), /* re25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7995) DRXJ_16TO8(-33), /* re26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7996) DRXJ_16TO8(626) /* re27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7999) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8000) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8001) common_attr = (struct drx_common_attr *) demod->my_common_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8003) if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8004) if (ext_attr->standard == DRX_STANDARD_ITU_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8005) switch (channel->constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8006) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8007) iqm_rc_rate = 0x00AE3562;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8008) lc_symbol_freq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8009) QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8010) channel->symbolrate = 5360537;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8011) iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8012) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8013) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8014) iqm_rc_rate = 0x00C05A0E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8015) lc_symbol_freq = 409;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8016) channel->symbolrate = 5056941;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8017) iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8018) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8019) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8020) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8022) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8023) adc_frequency = (common_attr->sys_clock_freq * 1000) / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8024) if (channel->symbolrate == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8025) pr_err("error: channel symbolrate is zero!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8026) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8028) iqm_rc_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8029) (adc_frequency / channel->symbolrate) * (1 << 21) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8030) (frac28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8031) ((adc_frequency % channel->symbolrate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8032) channel->symbolrate) >> 7) - (1 << 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8033) lc_symbol_freq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8034) (u16) (frac28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8035) (channel->symbolrate +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8036) (adc_frequency >> 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8037) adc_frequency) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8038) if (lc_symbol_freq > 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8039) lc_symbol_freq = 511;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8041) iqm_rc_stretch = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8044) if (ext_attr->standard == DRX_STANDARD_ITU_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8045) set_env_parameters = QAM_TOP_ANNEX_A; /* annex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8046) set_param_parameters[0] = channel->constellation; /* constellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8047) set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8048) } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8049) set_env_parameters = QAM_TOP_ANNEX_B; /* annex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8050) set_param_parameters[0] = channel->constellation; /* constellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8051) set_param_parameters[1] = channel->interleavemode; /* interleave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8052) } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8053) set_env_parameters = QAM_TOP_ANNEX_C; /* annex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8054) set_param_parameters[0] = channel->constellation; /* constellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8055) set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8056) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8057) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8061) if (op & QAM_SET_OP_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8062) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8063) STEP 1: reset demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8064) resets IQM, QAM and FEC HW blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8065) resets SCU variables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8067) /* stop all comm_exec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8068) rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8069) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8070) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8071) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8073) rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8074) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8075) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8076) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8078) rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8079) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8080) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8081) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8083) rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8084) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8085) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8086) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8088) rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8089) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8090) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8091) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8093) rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8094) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8095) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8096) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8098) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8099) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8100) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8101) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8104) cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8105) SCU_RAM_COMMAND_CMD_DEMOD_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8106) cmd_scu.parameter_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8107) cmd_scu.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8108) cmd_scu.parameter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8109) cmd_scu.result = &cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8110) rc = scu_command(dev_addr, &cmd_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8111) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8112) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8113) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8117) if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8119) STEP 2: configure demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8120) -set env
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8121) -set params (resets IQM,QAM,FEC HW; initializes some SCU variables )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8123) cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8124) SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8125) cmd_scu.parameter_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8126) cmd_scu.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8127) cmd_scu.parameter = &set_env_parameters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8128) cmd_scu.result = &cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8129) rc = scu_command(dev_addr, &cmd_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8130) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8131) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8132) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8135) cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8136) SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8137) cmd_scu.parameter_len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8138) cmd_scu.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8139) cmd_scu.parameter = set_param_parameters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8140) cmd_scu.result = &cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8141) rc = scu_command(dev_addr, &cmd_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8142) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8143) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8144) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8146) /* set symbol rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8147) rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8148) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8149) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8150) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8152) ext_attr->iqm_rc_rate_ofs = iqm_rc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8153) rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8154) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8155) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8156) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8159) /* STEP 3: enable the system in a mode where the ADC provides valid signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8160) setup constellation independent registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8161) /* from qam_cmd.py script (qam_driver_b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8162) /* TODO: remove re-writes of HW reset values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8163) if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8164) rc = set_frequency(demod, channel, tuner_freq_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8165) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8166) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8167) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8171) if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8173) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8174) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8175) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8176) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8178) rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8179) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8180) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8181) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8185) if (op & QAM_SET_OP_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8186) if (!ext_attr->has_lna) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8187) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8188) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8189) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8190) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8193) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8194) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8195) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8196) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8198) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8199) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8200) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8201) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8203) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8204) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8205) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8206) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8209) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8210) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8211) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8212) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8213) } /* scu temporary shut down agc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8215) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8216) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8217) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8218) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8220) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8221) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8222) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8223) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8225) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8226) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8227) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8228) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8230) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8231) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8232) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8233) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8235) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8236) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8237) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8238) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8240) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8241) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8242) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8243) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8245) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8246) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8247) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8248) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8251) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8252) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8253) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8254) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8256) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8257) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8258) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8259) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8260) } /*! reset default val ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8262) rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8263) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8264) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8265) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8266) } /*! reset default val ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8267) if (ext_attr->standard == DRX_STANDARD_ITU_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8268) rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8269) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8270) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8271) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8272) } /*! reset default val ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8273) rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8274) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8275) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8276) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8277) } /*! reset default val ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8278) rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8279) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8280) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8281) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8282) } /*! reset default val ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8283) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8284) switch (channel->constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8285) case DRX_CONSTELLATION_QAM16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8286) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8287) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8288) rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8289) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8290) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8291) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8293) rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8294) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8295) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8296) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8298) rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8299) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8300) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8301) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8302) } /*! reset default val ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8304) case DRX_CONSTELLATION_QAM32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8305) case DRX_CONSTELLATION_QAM128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8306) rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8307) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8308) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8309) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8311) rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8312) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8313) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8314) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8316) rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8317) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8318) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8319) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8322) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8323) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8324) } /* switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8327) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8328) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8329) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8330) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8331) } /*! reset default val ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8332) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8333) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8334) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8335) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8337) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8338) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8339) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8340) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8342) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8343) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8344) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8345) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8347) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8348) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8349) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8350) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8352) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8353) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8354) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8355) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8357) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8358) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8359) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8360) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8362) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8363) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8364) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8365) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8367) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8368) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8369) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8370) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8372) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8373) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8374) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8375) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8377) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8378) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8379) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8380) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8382) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8383) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8384) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8385) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8387) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8388) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8389) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8390) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8392) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8393) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8394) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8395) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8397) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8398) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8399) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8400) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8402) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8403) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8404) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8405) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8407) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8408) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8409) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8410) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8412) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8413) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8414) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8415) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8417) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8418) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8419) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8420) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8422) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8423) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8424) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8425) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8428) rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8429) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8430) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8431) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8433) rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8434) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8435) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8436) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8438) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8439) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8440) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8441) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8443) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8444) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8445) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8446) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8448) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8449) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8450) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8451) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8454) /* No more resets of the IQM, current standard correctly set =>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8455) now AGCs can be configured. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8456) /* turn on IQMAF. It has to be in front of setAgc**() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8457) rc = set_iqm_af(demod, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8458) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8459) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8460) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8462) rc = adc_synchronization(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8463) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8464) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8465) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8468) rc = init_agc(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8469) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8470) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8471) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8473) rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8474) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8475) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8476) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8478) rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8479) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8480) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8481) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8484) /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8485) of only the gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8486) struct drxj_cfg_afe_gain qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8488) qam_pga_cfg.gain = ext_attr->qam_pga_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8489) rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8490) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8491) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8492) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8495) rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8496) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8497) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8498) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8502) if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8503) if (ext_attr->standard == DRX_STANDARD_ITU_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8504) rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8505) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8506) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8507) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8509) rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8510) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8511) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8512) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8514) } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8515) switch (channel->constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8516) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8517) rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8518) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8519) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8520) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8522) rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8523) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8524) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8525) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8528) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8529) rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8530) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8531) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8532) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8534) rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8535) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8536) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8537) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8540) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8541) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8543) } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8544) rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8545) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8546) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8547) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8549) rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8550) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8551) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8552) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8556) /* SETP 4: constellation specific setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8557) switch (channel->constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8558) case DRX_CONSTELLATION_QAM16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8559) rc = set_qam16(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8560) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8561) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8562) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8565) case DRX_CONSTELLATION_QAM32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8566) rc = set_qam32(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8567) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8568) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8569) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8572) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8573) rc = set_qam64(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8574) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8575) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8576) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8579) case DRX_CONSTELLATION_QAM128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8580) rc = set_qam128(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8581) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8582) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8583) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8586) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8587) rc = set_qam256(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8588) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8589) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8590) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8593) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8594) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8595) } /* switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8598) if ((op & QAM_SET_OP_ALL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8599) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8600) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8601) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8602) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8605) /* Mpeg output has to be in front of FEC active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8606) rc = set_mpegtei_handling(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8607) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8608) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8609) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8611) rc = bit_reverse_mpeg_output(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8612) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8613) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8614) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8616) rc = set_mpeg_start_width(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8617) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8618) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8619) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8622) /* TODO: move to set_standard after hardware reset value problem is solved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8623) /* Configure initial MPEG output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8624) struct drx_cfg_mpeg_output cfg_mpeg_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8626) memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8627) cfg_mpeg_output.enable_mpeg_output = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8629) rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8630) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8631) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8632) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8637) if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8639) /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8640) cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8641) SCU_RAM_COMMAND_CMD_DEMOD_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8642) cmd_scu.parameter_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8643) cmd_scu.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8644) cmd_scu.parameter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8645) cmd_scu.result = &cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8646) rc = scu_command(dev_addr, &cmd_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8647) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8648) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8649) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8653) rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8654) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8655) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8656) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8658) rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8659) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8660) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8661) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8663) rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8664) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8665) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8666) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8670) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8671) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8674) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8675) static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8677) static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8679) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8680) struct drxj_data *ext_attr = demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8681) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8682) u32 iqm_fs_rate_ofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8683) u32 iqm_fs_rate_lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8684) u16 qam_ctl_ena = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8685) u16 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8686) u16 equ_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8687) u16 fsm_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8688) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8689) int ofsofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8691) /* Silence the controlling of lc, equ, and the acquisition state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8692) rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8693) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8694) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8695) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8697) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8698) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8699) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8700) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8703) /* freeze the frequency control loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8704) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8705) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8706) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8707) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8709) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8710) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8711) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8712) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8715) rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8716) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8717) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8718) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8720) rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8721) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8722) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8723) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8725) ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8726) iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8727) iqm_fs_rate_ofs -= 2 * ofsofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8729) /* freeze dq/fq updating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8730) rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8731) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8732) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8733) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8735) data = (data & 0xfff9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8736) rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8737) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8738) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8739) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8741) rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8742) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8743) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8744) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8747) /* lc_cp / _ci / _ca */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8748) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8749) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8750) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8751) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8753) rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8754) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8755) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8756) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8758) rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8759) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8760) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8761) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8764) /* flip the spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8765) rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8766) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8767) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8768) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8770) ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8771) ext_attr->pos_image = (ext_attr->pos_image) ? false : true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8773) /* freeze dq/fq updating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8774) rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8775) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8776) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8777) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8779) equ_mode = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8780) data = (data & 0xfff9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8781) rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8782) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8783) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8784) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8786) rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8787) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8788) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8789) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8792) for (i = 0; i < 28; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8793) rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8794) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8795) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8796) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8798) rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8799) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8800) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8801) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8805) for (i = 0; i < 24; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8806) rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8807) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8808) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8809) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8811) rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8812) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8813) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8814) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8818) data = equ_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8819) rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8820) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8821) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8822) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8824) rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8825) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8826) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8827) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8830) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8831) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8832) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8833) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8836) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8837) while ((fsm_state != 4) && (i++ < 100)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8838) rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8839) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8840) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8841) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8844) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8845) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8846) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8847) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8850) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8851) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8852) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8856) #define NO_LOCK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8857) #define DEMOD_LOCKED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8858) #define SYNC_FLIPPED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8859) #define SPEC_MIRRORED 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8861) * \fn int qam64auto ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8862) * \brief auto do sync pattern switching and mirroring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8863) * \param demod: instance of demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8864) * \param channel: pointer to channel data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8865) * \param tuner_freq_offset: tuner frequency offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8866) * \param lock_status: pointer to lock status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8867) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8869) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8870) qam64auto(struct drx_demod_instance *demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8871) struct drx_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8872) s32 tuner_freq_offset, enum drx_lock_status *lock_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8874) struct drxj_data *ext_attr = demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8875) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8876) struct drx39xxj_state *state = dev_addr->user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8877) struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8878) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8879) u32 lck_state = NO_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8880) u32 start_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8881) u32 d_locked_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8882) u32 timeout_ofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8883) u16 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8885) /* external attributes for storing acquired channel constellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8886) *lock_status = DRX_NOT_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8887) start_time = jiffies_to_msecs(jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8888) lck_state = NO_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8889) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8890) rc = ctrl_lock_status(demod, lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8891) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8892) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8893) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8896) switch (lck_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8897) case NO_LOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8898) if (*lock_status == DRXJ_DEMOD_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8899) rc = ctrl_get_qam_sig_quality(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8900) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8901) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8902) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8904) if (p->cnr.stat[0].svalue > 20800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8905) lck_state = DEMOD_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8906) /* some delay to see if fec_lock possible TODO find the right value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8907) timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8908) d_locked_time = jiffies_to_msecs(jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8912) case DEMOD_LOCKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8913) if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8914) ((jiffies_to_msecs(jiffies) - d_locked_time) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8915) DRXJ_QAM_FEC_LOCK_WAITTIME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8916) rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8917) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8918) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8919) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8921) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8922) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8923) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8924) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8926) lck_state = SYNC_FLIPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8927) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8929) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8930) case SYNC_FLIPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8931) if (*lock_status == DRXJ_DEMOD_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8932) if (channel->mirror == DRX_MIRROR_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8933) /* flip sync pattern back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8934) rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8935) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8936) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8937) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8939) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8940) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8941) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8942) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8944) /* flip spectrum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8945) ext_attr->mirror = DRX_MIRROR_YES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8946) rc = qam_flip_spec(demod, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8947) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8948) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8949) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8951) lck_state = SPEC_MIRRORED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8952) /* reset timer TODO: still need 500ms? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8953) start_time = d_locked_time =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8954) jiffies_to_msecs(jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8955) timeout_ofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8956) } else { /* no need to wait lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8958) start_time =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8959) jiffies_to_msecs(jiffies) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8960) DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8964) case SPEC_MIRRORED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8965) if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8966) ((jiffies_to_msecs(jiffies) - d_locked_time) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8967) DRXJ_QAM_FEC_LOCK_WAITTIME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8968) rc = ctrl_get_qam_sig_quality(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8969) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8970) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8971) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8973) if (p->cnr.stat[0].svalue > 20800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8974) rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8975) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8976) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8977) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8979) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8980) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8981) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8982) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8984) /* no need to wait lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8985) start_time =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8986) jiffies_to_msecs(jiffies) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8987) DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8991) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8992) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8994) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8995) } while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8996) ((*lock_status != DRX_LOCKED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8997) (*lock_status != DRX_NEVER_LOCK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8998) ((jiffies_to_msecs(jiffies) - start_time) <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8999) (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9000) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9001) /* Returning control to application ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9003) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9004) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9005) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9008) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9009) * \fn int qam256auto ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9010) * \brief auto do sync pattern switching and mirroring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9011) * \param demod: instance of demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9012) * \param channel: pointer to channel data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9013) * \param tuner_freq_offset: tuner frequency offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9014) * \param lock_status: pointer to lock status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9015) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9017) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9018) qam256auto(struct drx_demod_instance *demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9019) struct drx_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9020) s32 tuner_freq_offset, enum drx_lock_status *lock_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9022) struct drxj_data *ext_attr = demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9023) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9024) struct drx39xxj_state *state = dev_addr->user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9025) struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9026) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9027) u32 lck_state = NO_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9028) u32 start_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9029) u32 d_locked_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9030) u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9032) /* external attributes for storing acquired channel constellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9033) *lock_status = DRX_NOT_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9034) start_time = jiffies_to_msecs(jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9035) lck_state = NO_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9036) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9037) rc = ctrl_lock_status(demod, lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9038) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9039) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9040) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9042) switch (lck_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9043) case NO_LOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9044) if (*lock_status == DRXJ_DEMOD_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9045) rc = ctrl_get_qam_sig_quality(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9046) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9047) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9048) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9050) if (p->cnr.stat[0].svalue > 26800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9051) lck_state = DEMOD_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9052) timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9053) d_locked_time = jiffies_to_msecs(jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9056) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9057) case DEMOD_LOCKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9058) if (*lock_status == DRXJ_DEMOD_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9059) if ((channel->mirror == DRX_MIRROR_AUTO) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9060) ((jiffies_to_msecs(jiffies) - d_locked_time) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9061) DRXJ_QAM_FEC_LOCK_WAITTIME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9062) ext_attr->mirror = DRX_MIRROR_YES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9063) rc = qam_flip_spec(demod, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9064) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9065) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9066) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9068) lck_state = SPEC_MIRRORED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9069) /* reset timer TODO: still need 300ms? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9070) start_time = jiffies_to_msecs(jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9071) timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9075) case SPEC_MIRRORED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9077) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9078) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9080) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9081) } while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9082) ((*lock_status < DRX_LOCKED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9083) (*lock_status != DRX_NEVER_LOCK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9084) ((jiffies_to_msecs(jiffies) - start_time) <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9085) (DRXJ_QAM_MAX_WAITTIME + timeout_ofs)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9087) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9088) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9089) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9092) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9093) * \fn int set_qam_channel ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9094) * \brief Set QAM channel according to the requested constellation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9095) * \param demod: instance of demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9096) * \param channel: pointer to channel data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9097) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9098) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9099) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9100) set_qam_channel(struct drx_demod_instance *demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9101) struct drx_channel *channel, s32 tuner_freq_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9103) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9104) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9105) enum drx_lock_status lock_status = DRX_NOT_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9106) bool auto_flag = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9108) /* external attributes for storing acquired channel constellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9109) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9111) /* set QAM channel constellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9112) switch (channel->constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9113) case DRX_CONSTELLATION_QAM16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9114) case DRX_CONSTELLATION_QAM32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9115) case DRX_CONSTELLATION_QAM128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9116) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9117) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9118) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9119) if (ext_attr->standard != DRX_STANDARD_ITU_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9120) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9122) ext_attr->constellation = channel->constellation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9123) if (channel->mirror == DRX_MIRROR_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9124) ext_attr->mirror = DRX_MIRROR_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9125) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9126) ext_attr->mirror = channel->mirror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9128) rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9129) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9130) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9131) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9134) if (channel->constellation == DRX_CONSTELLATION_QAM64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9135) rc = qam64auto(demod, channel, tuner_freq_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9136) &lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9138) rc = qam256auto(demod, channel, tuner_freq_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9139) &lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9140) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9141) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9142) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9145) case DRX_CONSTELLATION_AUTO: /* for channel scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9146) if (ext_attr->standard == DRX_STANDARD_ITU_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9147) u16 qam_ctl_ena = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9149) auto_flag = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9151) /* try to lock default QAM constellation: QAM256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9152) channel->constellation = DRX_CONSTELLATION_QAM256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9153) ext_attr->constellation = DRX_CONSTELLATION_QAM256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9154) if (channel->mirror == DRX_MIRROR_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9155) ext_attr->mirror = DRX_MIRROR_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9156) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9157) ext_attr->mirror = channel->mirror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9158) rc = set_qam(demod, channel, tuner_freq_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9159) QAM_SET_OP_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9160) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9161) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9162) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9164) rc = qam256auto(demod, channel, tuner_freq_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9165) &lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9166) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9167) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9168) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9171) if (lock_status >= DRX_LOCKED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9172) channel->constellation = DRX_CONSTELLATION_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9176) /* QAM254 not locked. Try QAM64 constellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9177) channel->constellation = DRX_CONSTELLATION_QAM64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9178) ext_attr->constellation = DRX_CONSTELLATION_QAM64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9179) if (channel->mirror == DRX_MIRROR_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9180) ext_attr->mirror = DRX_MIRROR_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9181) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9182) ext_attr->mirror = channel->mirror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9184) rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9185) SCU_RAM_QAM_CTL_ENA__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9186) &qam_ctl_ena, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9187) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9188) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9189) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9191) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9192) SCU_RAM_QAM_CTL_ENA__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9193) qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9194) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9195) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9196) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9198) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9199) SCU_RAM_QAM_FSM_STATE_TGT__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9200) 0x2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9201) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9202) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9203) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9204) } /* force to rate hunting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9206) rc = set_qam(demod, channel, tuner_freq_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9207) QAM_SET_OP_CONSTELLATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9208) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9209) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9210) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9212) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9213) SCU_RAM_QAM_CTL_ENA__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9214) qam_ctl_ena, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9215) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9216) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9217) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9220) rc = qam64auto(demod, channel, tuner_freq_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9221) &lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9222) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9223) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9224) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9227) channel->constellation = DRX_CONSTELLATION_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9228) } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9229) u16 qam_ctl_ena = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9231) channel->constellation = DRX_CONSTELLATION_QAM64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9232) ext_attr->constellation = DRX_CONSTELLATION_QAM64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9233) auto_flag = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9235) if (channel->mirror == DRX_MIRROR_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9236) ext_attr->mirror = DRX_MIRROR_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9238) ext_attr->mirror = channel->mirror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9239) rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9240) SCU_RAM_QAM_CTL_ENA__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9241) &qam_ctl_ena, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9242) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9243) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9244) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9246) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9247) SCU_RAM_QAM_CTL_ENA__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9248) qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9249) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9250) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9251) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9253) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9254) SCU_RAM_QAM_FSM_STATE_TGT__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9255) 0x2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9256) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9257) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9258) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9259) } /* force to rate hunting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9261) rc = set_qam(demod, channel, tuner_freq_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9262) QAM_SET_OP_CONSTELLATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9263) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9264) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9265) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9267) rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9268) SCU_RAM_QAM_CTL_ENA__A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9269) qam_ctl_ena, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9270) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9271) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9272) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9274) rc = qam64auto(demod, channel, tuner_freq_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9275) &lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9276) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9277) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9278) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9280) channel->constellation = DRX_CONSTELLATION_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9281) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9282) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9285) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9286) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9290) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9291) /* restore starting value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9292) if (auto_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9293) channel->constellation = DRX_CONSTELLATION_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9294) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9297) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9300) * \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9301) * \brief Get RS error count in QAM mode (used for post RS BER calculation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9302) * \return Error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9303) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9304) * precondition: measurement period & measurement prescale must be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9305) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9307) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9308) get_qamrs_err_count(struct i2c_device_addr *dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9309) struct drxjrs_errors *rs_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9311) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9312) u16 nr_bit_errors = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9313) nr_symbol_errors = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9314) nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9316) /* check arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9317) if (dev_addr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9318) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9320) /* all reported errors are received in the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9321) /* most recently finished measurement period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9322) /* no of pre RS bit errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9323) rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9324) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9325) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9326) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9328) /* no of symbol errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9329) rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9330) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9331) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9332) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9334) /* no of packet errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9335) rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9336) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9337) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9338) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9340) /* no of failures to decode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9341) rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9342) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9343) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9344) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9346) /* no of post RS bit erros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9347) rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9348) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9349) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9350) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9352) /* TODO: NOTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9353) /* These register values are fetched in non-atomic fashion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9354) /* It is possible that the read values contain unrelated information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9356) rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9357) rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9358) rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9359) rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9360) rs_errors->nr_snc_par_fail_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9361) nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9364) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9365) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9368) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9371) * \fn int get_sig_strength()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9372) * \brief Retrieve signal strength for VSB and QAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9373) * \param demod Pointer to demod instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9374) * \param u16-t Pointer to signal strength data; range 0, .. , 100.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9375) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9376) * \retval 0 sig_strength contains valid data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9377) * \retval -EINVAL sig_strength is NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9378) * \retval -EIO Erroneous data, sig_strength contains invalid data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9380) #define DRXJ_AGC_TOP 0x2800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9381) #define DRXJ_AGC_SNS 0x1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9382) #define DRXJ_RFAGC_MAX 0x3fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9383) #define DRXJ_RFAGC_MIN 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9385) static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9387) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9388) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9389) u16 rf_gain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9390) u16 if_gain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9391) u16 if_agc_sns = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9392) u16 if_agc_top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9393) u16 rf_agc_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9394) u16 rf_agc_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9396) rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9397) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9398) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9399) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9401) if_gain &= IQM_AF_AGC_IF__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9402) rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9403) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9404) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9405) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9407) rf_gain &= IQM_AF_AGC_RF__M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9409) if_agc_sns = DRXJ_AGC_SNS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9410) if_agc_top = DRXJ_AGC_TOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9411) rf_agc_max = DRXJ_RFAGC_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9412) rf_agc_min = DRXJ_RFAGC_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9414) if (if_gain > if_agc_top) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9415) if (rf_gain > rf_agc_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9416) *sig_strength = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9417) else if (rf_gain > rf_agc_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9418) if (rf_agc_max == rf_agc_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9419) pr_err("error: rf_agc_max == rf_agc_min\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9420) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9422) *sig_strength =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9423) 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9424) rf_agc_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9425) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9426) *sig_strength = 75;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9427) } else if (if_gain > if_agc_sns) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9428) if (if_agc_top == if_agc_sns) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9429) pr_err("error: if_agc_top == if_agc_sns\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9430) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9432) *sig_strength =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9433) 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9434) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9435) if (!if_agc_sns) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9436) pr_err("error: if_agc_sns is zero!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9437) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9439) *sig_strength = (20 * if_gain / if_agc_sns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9442) if (*sig_strength <= 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9443) *sig_strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9446) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9447) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9451) * \fn int ctrl_get_qam_sig_quality()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9452) * \brief Retrieve QAM signal quality from device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9453) * \param devmod Pointer to demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9454) * \param sig_quality Pointer to signal quality data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9455) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9456) * \retval 0 sig_quality contains valid data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9457) * \retval -EINVAL sig_quality is NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9458) * \retval -EIO Erroneous data, sig_quality contains invalid data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9460) * Pre-condition: Device must be started and in lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9462) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9463) ctrl_get_qam_sig_quality(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9465) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9466) struct drxj_data *ext_attr = demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9467) struct drx39xxj_state *state = dev_addr->user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9468) struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9469) struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9470) enum drx_modulation constellation = ext_attr->constellation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9471) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9473) u32 pre_bit_err_rs = 0; /* pre RedSolomon Bit Error Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9474) u32 post_bit_err_rs = 0; /* post RedSolomon Bit Error Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9475) u32 pkt_errs = 0; /* no of packet errors in RS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9476) u16 qam_sl_err_power = 0; /* accumulated error between raw and sliced symbols */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9477) u16 qsym_err_vd = 0; /* quadrature symbol errors in QAM_VD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9478) u16 fec_oc_period = 0; /* SNC sync failure measurement period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9479) u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9480) u16 fec_rs_period = 0; /* Value for corresponding I2C register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9481) /* calculation constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9482) u32 rs_bit_cnt = 0; /* RedSolomon Bit Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9483) u32 qam_sl_sig_power = 0; /* used for MER, depends of QAM constellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9484) /* intermediate results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9485) u32 e = 0; /* exponent value used for QAM BER/SER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9486) u32 m = 0; /* mantisa value used for QAM BER/SER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9487) u32 ber_cnt = 0; /* BER count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9488) /* signal quality info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9489) u32 qam_sl_mer = 0; /* QAM MER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9490) u32 qam_pre_rs_ber = 0; /* Pre RedSolomon BER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9491) u32 qam_post_rs_ber = 0; /* Post RedSolomon BER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9492) u32 qam_vd_ser = 0; /* ViterbiDecoder SER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9493) u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9494) u16 qam_vd_period = 0; /* Viterbi Measurement period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9495) u32 vd_bit_cnt = 0; /* ViterbiDecoder Bit Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9497) p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9499) /* read the physical registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9500) /* Get the RS error data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9501) rc = get_qamrs_err_count(dev_addr, &measuredrs_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9502) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9503) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9504) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9506) /* get the register value needed for MER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9507) rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9508) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9509) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9510) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9512) /* get the register value needed for post RS BER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9513) rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9514) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9515) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9516) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9519) /* get constants needed for signal quality calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9520) fec_rs_period = ext_attr->fec_rs_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9521) fec_rs_prescale = ext_attr->fec_rs_prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9522) rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9523) qam_vd_period = ext_attr->qam_vd_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9524) qam_vd_prescale = ext_attr->qam_vd_prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9525) vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9527) /* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9528) switch (constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9529) case DRX_CONSTELLATION_QAM16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9530) qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9532) case DRX_CONSTELLATION_QAM32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9533) qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9535) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9536) qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9538) case DRX_CONSTELLATION_QAM128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9539) qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9541) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9542) qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9544) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9545) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9548) /* ------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9549) /* MER Calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9550) /* ------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9551) /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9553) /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9554) if (qam_sl_err_power == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9555) qam_sl_mer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9556) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9557) qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9559) /* ----------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9560) /* Pre Viterbi Symbol Error Rate Calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9561) /* ----------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9562) /* pre viterbi SER is good if it is below 0.025 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9564) /* get the register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9565) /* no of quadrature symbol errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9566) rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9567) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9568) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9569) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9571) /* Extract the Exponent and the Mantisa */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9572) /* of number of quadrature symbol errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9573) e = (qsym_err_vd & QAM_VD_NR_QSYM_ERRORS_EXP__M) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9574) QAM_VD_NR_QSYM_ERRORS_EXP__B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9575) m = (qsym_err_vd & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9576) QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9578) if ((m << e) >> 3 > 549752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9579) qam_vd_ser = 500000 * vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9580) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9581) qam_vd_ser = m << ((e > 2) ? (e - 3) : e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9583) /* --------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9584) /* pre and post RedSolomon BER Calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9585) /* --------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9586) /* pre RS BER is good if it is below 3.5e-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9588) /* get the register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9589) pre_bit_err_rs = (u32) measuredrs_errors.nr_bit_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9590) pkt_errs = post_bit_err_rs = (u32) measuredrs_errors.nr_snc_par_fail_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9592) /* Extract the Exponent and the Mantisa of the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9593) /* pre Reed-Solomon bit error count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9594) e = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_EXP__M) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9595) FEC_RS_NR_BIT_ERRORS_EXP__B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9596) m = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9597) FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9599) ber_cnt = m << e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9601) /*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9602) if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9603) qam_pre_rs_ber = 500000 * rs_bit_cnt >> e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9604) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9605) qam_pre_rs_ber = ber_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9607) /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9608) /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9610) => c = (1000000*100*11.17)/1504 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9611) post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9612) (100 * FEC_OC_SNC_FAIL_PERIOD__A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9613) *100 and /100 is for more precision.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9614) => (20 bits * 12 bits) /(16 bits * 7 bits) => safe in 32 bits computation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9616) Precision errors still possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9618) if (!fec_oc_period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9619) qam_post_rs_ber = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9620) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9621) e = post_bit_err_rs * 742686;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9622) m = fec_oc_period * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9623) qam_post_rs_ber = e / m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9626) /* fill signal quality data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9627) p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9628) p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9629) p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9630) p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9631) p->block_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9632) p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9634) p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9635) if (ext_attr->standard == DRX_STANDARD_ITU_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9636) p->pre_bit_error.stat[0].uvalue += qam_vd_ser;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9637) p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9638) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9639) p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9640) p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9643) p->post_bit_error.stat[0].uvalue += qam_post_rs_ber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9644) p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9646) p->block_error.stat[0].uvalue += pkt_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9648) #ifdef DRXJ_SIGNAL_ACCUM_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9649) rc = get_acc_pkt_err(demod, &sig_quality->packet_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9650) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9651) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9652) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9654) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9657) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9658) p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9659) p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9660) p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9661) p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9662) p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9663) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9665) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9668) #endif /* #ifndef DRXJ_VSB_ONLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9670) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9671) /*== END QAM DATAPATH FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9672) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9674) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9675) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9676) /*== ATV DATAPATH FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9677) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9678) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9681) Implementation notes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9683) NTSC/FM AGCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9685) Four AGCs are used for NTSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9686) (1) RF (used to attenuate the input signal in case of to much power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9687) (2) IF (used to attenuate the input signal in case of to much power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9688) (3) Video AGC (used to amplify the output signal in case input to low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9689) (4) SIF AGC (used to amplify the output signal in case input to low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9691) Video AGC is coupled to RF and IF. SIF AGC is not coupled. It is assumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9692) that the coupling between Video AGC and the RF and IF AGCs also works in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9693) favor of the SIF AGC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9695) Three AGCs are used for FM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9696) (1) RF (used to attenuate the input signal in case of to much power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9697) (2) IF (used to attenuate the input signal in case of to much power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9698) (3) SIF AGC (used to amplify the output signal in case input to low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9700) The SIF AGC is now coupled to the RF/IF AGCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9701) The SIF AGC is needed for both SIF output and the internal SIF signal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9702) the AUD block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9704) RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9705) the ATV block. The AGC control algorithms are all implemented in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9706) microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9708) ATV SETTINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9710) (Shadow settings will not be used for now, they will be implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9711) later on because of the schedule)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9713) Several HW/SCU "settings" can be used for ATV. The standard selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9714) will reset most of these settings. To avoid that the end user application
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9715) has to perform these settings each time the ATV or FM standards is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9716) selected the driver will shadow these settings. This enables the end user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9717) to perform the settings only once after a drx_open(). The driver must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9718) write the shadow settings to HW/SCU in case:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9719) ( setstandard FM/ATV) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9720) ( settings have changed && FM/ATV standard is active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9721) The shadow settings will be stored in the device specific data container.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9722) A set of flags will be defined to flag changes in shadow settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9723) A routine will be implemented to write all changed shadow settings to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9724) HW/SCU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9726) The "settings" will consist of: AGC settings, filter settings etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9728) Disadvantage of use of shadow settings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9729) Direct changes in HW/SCU registers will not be reflected in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9730) shadow settings and these changes will be overwritten during a next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9731) update. This can happen during evaluation. This will not be a problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9732) for normal customer usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9734) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9737) * \fn int power_down_atv ()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9738) * \brief Power down ATV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9739) * \param demod instance of demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9740) * \param standard either NTSC or FM (sub strandard for ATV )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9741) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9742) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9743) * Stops and thus resets ATV and IQM block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9744) * SIF and CVBS ADC are powered down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9745) * Calls audio power down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9747) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9748) power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9750) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9751) struct drxjscu_cmd cmd_scu = { /* command */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9752) /* parameter_len */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9753) /* result_len */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9754) /* *parameter */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9755) /* *result */ NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9757) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9758) u16 cmd_result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9760) /* ATV NTSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9762) /* Stop ATV SCU (will reset ATV and IQM hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9763) cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9764) SCU_RAM_COMMAND_CMD_DEMOD_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9765) cmd_scu.parameter_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9766) cmd_scu.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9767) cmd_scu.parameter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9768) cmd_scu.result = &cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9769) rc = scu_command(dev_addr, &cmd_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9770) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9771) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9772) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9774) /* Disable ATV outputs (ATV reset enables CVBS, undo this) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9775) rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9776) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9777) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9778) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9781) rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9782) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9783) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9784) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9786) if (primary) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9787) rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9788) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9789) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9790) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9792) rc = set_iqm_af(demod, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9793) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9794) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9795) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9797) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9798) rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9799) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9800) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9801) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9803) rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9804) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9805) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9806) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9808) rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9809) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9810) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9811) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9813) rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9814) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9815) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9816) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9818) rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9819) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9820) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9821) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9824) rc = power_down_aud(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9825) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9826) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9827) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9830) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9831) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9832) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9835) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9837) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9838) * \brief Power up AUD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9839) * \param demod instance of demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9840) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9841) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9843) static int power_down_aud(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9845) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9846) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9847) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9849) dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9850) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9852) rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9853) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9854) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9855) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9858) ext_attr->aud_data.audio_is_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9860) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9861) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9862) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9865) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9866) * \fn int set_orx_nsu_aox()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9867) * \brief Configure OrxNsuAox for OOB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9868) * \param demod instance of demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9869) * \param active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9870) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9872) static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9874) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9875) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9876) u16 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9878) /* Configure NSU_AOX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9879) rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9880) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9881) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9882) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9884) if (!active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9885) data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9886) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9887) data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9888) rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9889) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9890) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9891) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9895) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9896) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9899) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9900) * \fn int ctrl_set_oob()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9901) * \brief Set OOB channel to be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9902) * \param demod instance of demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9903) * \param oob_param OOB parameters for channel setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9904) * \frequency should be in KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9905) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9906) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9907) * Accepts only. Returns error otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9908) * Demapper value is written after scu_command START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9909) * because START command causes COMM_EXEC transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9910) * from 0 to 1 which causes all registers to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9911) * overwritten with initial value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9912) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9915) /* Nyquist filter impulse response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9916) #define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9917) #define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9918) #define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9920) /* Coefficients for the nyquist filter (total: 27 taps) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9921) #define NYQFILTERLEN 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9923) static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9925) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9926) s32 freq = 0; /* KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9927) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9928) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9929) u16 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9930) bool mirror_freq_spect_oob = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9931) u16 trk_filter_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9932) struct drxjscu_cmd scu_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9933) u16 set_param_parameters[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9934) u16 cmd_result[2] = { 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9935) s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9936) IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9937) IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9938) IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9939) IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9941) u8 mode_val[4] = { 2, 2, 0, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9942) u8 pfi_coeffs[4][6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9943) {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9944) {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9945) {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9946) {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9948) u16 mode_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9950) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9951) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9952) mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9954) /* Check parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9955) if (oob_param == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9956) /* power off oob module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9957) scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9958) | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9959) scu_cmd.parameter_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9960) scu_cmd.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9961) scu_cmd.result = cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9962) rc = scu_command(dev_addr, &scu_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9963) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9964) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9965) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9967) rc = set_orx_nsu_aox(demod, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9968) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9969) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9970) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9972) rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9973) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9974) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9975) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9978) ext_attr->oob_power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9979) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9982) freq = oob_param->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9983) if ((freq < 70000) || (freq > 130000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9984) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9985) freq = (freq - 50000) / 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9988) u16 index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9989) u16 remainder = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9990) u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9992) index = (u16) ((freq - 400) / 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9993) remainder = (u16) ((freq - 400) % 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9994) trk_filter_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9995) trk_filtercfg[index] - (trk_filtercfg[index] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9996) trk_filtercfg[index +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9997) 1]) / 10 * remainder /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9998) 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10001) /********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10002) /* Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10003) /********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10004) rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10005) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10006) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10007) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10009) scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10010) | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10011) scu_cmd.parameter_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10012) scu_cmd.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10013) scu_cmd.result = cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10014) rc = scu_command(dev_addr, &scu_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10015) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10016) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10017) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10019) /********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10020) /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10021) /********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10022) scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10023) | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10024) scu_cmd.parameter_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10025) scu_cmd.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10026) scu_cmd.result = cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10027) rc = scu_command(dev_addr, &scu_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10028) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10029) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10030) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10032) /**********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10033) /* SET_ENV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10034) /**********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10035) /* set frequency, spectrum inversion and data rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10036) scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10037) | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10038) scu_cmd.parameter_len = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10039) /* 1-data rate;2-frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10040) switch (oob_param->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10041) case DRX_OOB_MODE_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10042) if (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10043) /* signal is transmitted inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10044) ((oob_param->spectrum_inverted == true) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10045) /* and tuner is not mirroring the signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10046) (!mirror_freq_spect_oob)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10047) /* or */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10048) /* signal is transmitted noninverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10049) ((oob_param->spectrum_inverted == false) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10050) /* and tuner is mirroring the signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10051) (mirror_freq_spect_oob))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10052) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10053) set_param_parameters[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10054) SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10055) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10056) set_param_parameters[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10057) SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10058) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10059) case DRX_OOB_MODE_B_GRADE_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10060) if (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10061) /* signal is transmitted inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10062) ((oob_param->spectrum_inverted == true) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10063) /* and tuner is not mirroring the signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10064) (!mirror_freq_spect_oob)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10065) /* or */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10066) /* signal is transmitted noninverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10067) ((oob_param->spectrum_inverted == false) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10068) /* and tuner is mirroring the signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10069) (mirror_freq_spect_oob))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10070) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10071) set_param_parameters[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10072) SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10073) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10074) set_param_parameters[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10075) SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10077) case DRX_OOB_MODE_B_GRADE_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10078) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10079) if (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10080) /* signal is transmitted inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10081) ((oob_param->spectrum_inverted == true) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10082) /* and tuner is not mirroring the signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10083) (!mirror_freq_spect_oob)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10084) /* or */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10085) /* signal is transmitted noninverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10086) ((oob_param->spectrum_inverted == false) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10087) /* and tuner is mirroring the signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10088) (mirror_freq_spect_oob))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10089) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10090) set_param_parameters[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10091) SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10092) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10093) set_param_parameters[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10094) SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10095) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10097) set_param_parameters[1] = (u16) (freq & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10098) set_param_parameters[2] = trk_filter_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10099) scu_cmd.parameter = set_param_parameters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10100) scu_cmd.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10101) scu_cmd.result = cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10102) mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10103) rc = scu_command(dev_addr, &scu_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10104) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10105) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10106) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10109) rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10110) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10111) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10112) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10113) } /* Write magic word to enable pdr reg write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10114) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10115) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10116) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10117) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10119) rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10120) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10121) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10122) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10124) rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10125) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10126) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10127) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10128) } /* Write magic word to disable pdr reg write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10130) rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10131) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10132) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10133) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10135) rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10136) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10137) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10138) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10140) rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10141) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10142) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10143) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10146) /* ddc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10147) rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10148) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10149) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10150) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10153) /* nsu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10154) rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10155) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10156) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10157) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10160) /* initialization for target mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10161) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10162) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10163) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10164) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10166) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10167) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10168) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10169) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10172) /* Reset bits for timing and freq. recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10173) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10174) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10175) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10176) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10178) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10179) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10180) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10181) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10183) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10184) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10185) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10186) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10188) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10189) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10190) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10191) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10194) /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10195) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10196) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10197) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10198) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10200) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10201) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10202) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10203) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10205) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10206) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10207) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10208) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10210) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10211) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10212) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10213) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10215) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10216) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10217) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10218) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10221) /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10222) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10223) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10224) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10225) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10227) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10228) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10229) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10230) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10232) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10233) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10234) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10235) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10237) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10238) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10239) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10240) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10242) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10243) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10244) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10245) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10248) /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10249) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10250) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10251) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10252) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10254) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10255) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10256) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10257) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10259) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10260) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10261) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10262) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10264) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10265) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10266) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10267) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10269) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10270) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10271) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10272) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10275) /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10276) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10277) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10278) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10279) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10281) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10282) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10283) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10284) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10286) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10287) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10288) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10289) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10291) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10292) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10293) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10294) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10296) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10297) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10298) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10299) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10302) /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10303) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10304) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10305) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10306) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10308) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10309) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10310) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10311) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10313) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10314) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10315) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10316) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10318) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10319) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10320) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10321) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10323) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10324) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10325) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10326) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10329) /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10330) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10331) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10332) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10333) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10335) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10336) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10337) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10338) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10340) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10341) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10342) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10343) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10345) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10346) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10347) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10348) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10350) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10351) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10352) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10353) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10356) /* PRE-Filter coefficients (PFI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10357) rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10358) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10359) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10360) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10362) rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10363) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10364) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10365) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10368) /* NYQUIST-Filter coefficients (NYQ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10369) for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10370) rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10371) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10372) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10373) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10375) rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10376) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10377) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10378) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10381) rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10382) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10383) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10384) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10386) rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10387) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10388) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10389) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10391) /********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10392) /* Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10393) /********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10394) scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10395) | SCU_RAM_COMMAND_CMD_DEMOD_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10396) scu_cmd.parameter_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10397) scu_cmd.result_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10398) scu_cmd.result = cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10399) rc = scu_command(dev_addr, &scu_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10400) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10401) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10402) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10405) rc = set_orx_nsu_aox(demod, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10406) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10407) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10408) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10410) rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10411) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10412) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10413) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10416) ext_attr->oob_power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10419) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10420) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10423) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10424) /*== END OOB DATAPATH FUNCTIONS ==*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10425) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10427) /*=============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10428) ===== MC command related functions ==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10429) ===========================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10431) /*=============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10432) ===== ctrl_set_channel() ==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10433) ===========================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10435) * \fn int ctrl_set_channel()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10436) * \brief Select a new transmission channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10437) * \param demod instance of demod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10438) * \param channel Pointer to channel data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10439) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10440) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10441) * In case the tuner module is not used and in case of NTSC/FM the pogrammer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10442) * must tune the tuner to the centre frequency of the NTSC/FM channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10443) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10445) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10446) ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10448) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10449) s32 tuner_freq_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10450) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10451) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10452) enum drx_standard standard = DRX_STANDARD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10453) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10454) u32 min_symbol_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10455) u32 max_symbol_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10456) int bandwidth_temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10457) int bandwidth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10458) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10459) /*== check arguments ======================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10460) if ((demod == NULL) || (channel == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10461) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10463) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10464) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10465) standard = ext_attr->standard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10467) /* check valid standards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10468) switch (standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10469) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10470) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10471) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10472) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10473) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10474) #endif /* DRXJ_VSB_ONLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10476) case DRX_STANDARD_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10477) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10478) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10481) /* check bandwidth QAM annex B, NTSC and 8VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10482) if ((standard == DRX_STANDARD_ITU_B) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10483) (standard == DRX_STANDARD_8VSB) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10484) (standard == DRX_STANDARD_NTSC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10485) switch (channel->bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10486) case DRX_BANDWIDTH_6MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10487) case DRX_BANDWIDTH_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10488) channel->bandwidth = DRX_BANDWIDTH_6MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10490) case DRX_BANDWIDTH_8MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10491) case DRX_BANDWIDTH_7MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10492) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10493) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10497) /* For QAM annex A and annex C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10498) -check symbolrate and constellation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10499) -derive bandwidth from symbolrate (input bandwidth is ignored)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10501) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10502) if ((standard == DRX_STANDARD_ITU_A) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10503) (standard == DRX_STANDARD_ITU_C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10504) struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10505) int bw_rolloff_factor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10507) bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10508) min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10509) max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10510) /* config SMA_TX pin to SAW switch mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10511) rc = ctrl_set_uio_cfg(demod, &uio_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10512) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10513) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10514) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10517) if (channel->symbolrate < min_symbol_rate ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10518) channel->symbolrate > max_symbol_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10519) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10522) switch (channel->constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10523) case DRX_CONSTELLATION_QAM16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10524) case DRX_CONSTELLATION_QAM32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10525) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10526) case DRX_CONSTELLATION_QAM128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10527) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10528) bandwidth_temp = channel->symbolrate * bw_rolloff_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10529) bandwidth = bandwidth_temp / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10531) if ((bandwidth_temp % 100) >= 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10532) bandwidth++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10534) if (bandwidth <= 6100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10535) channel->bandwidth = DRX_BANDWIDTH_6MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10536) } else if ((bandwidth > 6100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10537) && (bandwidth <= 7100000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10538) channel->bandwidth = DRX_BANDWIDTH_7MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10539) } else if (bandwidth > 7100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10540) channel->bandwidth = DRX_BANDWIDTH_8MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10542) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10543) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10544) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10548) /* For QAM annex B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10549) -check constellation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10551) if (standard == DRX_STANDARD_ITU_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10552) switch (channel->constellation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10553) case DRX_CONSTELLATION_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10554) case DRX_CONSTELLATION_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10555) case DRX_CONSTELLATION_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10557) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10558) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10561) switch (channel->interleavemode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10562) case DRX_INTERLEAVEMODE_I128_J1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10563) case DRX_INTERLEAVEMODE_I128_J1_V2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10564) case DRX_INTERLEAVEMODE_I128_J2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10565) case DRX_INTERLEAVEMODE_I64_J2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10566) case DRX_INTERLEAVEMODE_I128_J3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10567) case DRX_INTERLEAVEMODE_I32_J4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10568) case DRX_INTERLEAVEMODE_I128_J4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10569) case DRX_INTERLEAVEMODE_I16_J8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10570) case DRX_INTERLEAVEMODE_I128_J5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10571) case DRX_INTERLEAVEMODE_I8_J16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10572) case DRX_INTERLEAVEMODE_I128_J6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10573) case DRX_INTERLEAVEMODE_I128_J7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10574) case DRX_INTERLEAVEMODE_I128_J8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10575) case DRX_INTERLEAVEMODE_I12_J17:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10576) case DRX_INTERLEAVEMODE_I5_J4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10577) case DRX_INTERLEAVEMODE_B52_M240:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10578) case DRX_INTERLEAVEMODE_B52_M720:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10579) case DRX_INTERLEAVEMODE_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10580) case DRX_INTERLEAVEMODE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10582) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10583) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10587) if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10588) /* SAW SW, user UIO is used for switchable SAW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10589) struct drxuio_data uio1 = { DRX_UIO1, false };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10591) switch (channel->bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10592) case DRX_BANDWIDTH_8MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10593) uio1.value = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10595) case DRX_BANDWIDTH_7MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10596) uio1.value = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10598) case DRX_BANDWIDTH_6MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10599) uio1.value = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10601) case DRX_BANDWIDTH_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10602) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10603) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10606) rc = ctrl_uio_write(demod, &uio1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10607) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10608) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10609) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10612) #endif /* DRXJ_VSB_ONLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10613) rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10614) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10615) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10616) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10619) tuner_freq_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10621) /*== Setup demod for specific standard ====================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10622) switch (standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10623) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10624) if (channel->mirror == DRX_MIRROR_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10625) ext_attr->mirror = DRX_MIRROR_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10626) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10627) ext_attr->mirror = channel->mirror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10628) rc = set_vsb(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10629) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10630) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10631) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10633) rc = set_frequency(demod, channel, tuner_freq_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10634) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10635) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10636) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10639) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10640) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10641) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10642) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10643) rc = set_qam_channel(demod, channel, tuner_freq_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10644) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10645) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10646) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10649) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10650) case DRX_STANDARD_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10651) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10652) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10655) /* flag the packet error counter reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10656) ext_attr->reset_pkt_err_acc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10659) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10660) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10663) /*=============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10664) ===== SigQuality() ==========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10665) ===========================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10668) * \fn int ctrl_sig_quality()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10669) * \brief Retrieve signal quality form device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10670) * \param devmod Pointer to demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10671) * \param sig_quality Pointer to signal quality data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10672) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10673) * \retval 0 sig_quality contains valid data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10674) * \retval -EINVAL sig_quality is NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10675) * \retval -EIO Erroneous data, sig_quality contains invalid data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10678) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10679) ctrl_sig_quality(struct drx_demod_instance *demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10680) enum drx_lock_status lock_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10682) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10683) struct drxj_data *ext_attr = demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10684) struct drx39xxj_state *state = dev_addr->user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10685) struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10686) enum drx_standard standard = ext_attr->standard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10687) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10688) u32 ber, cnt, err, pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10689) u16 mer, strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10691) rc = get_sig_strength(demod, &strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10692) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10693) pr_err("error getting signal strength %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10694) p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10695) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10696) p->strength.stat[0].scale = FE_SCALE_RELATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10697) p->strength.stat[0].uvalue = 65535UL * strength/ 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10700) switch (standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10701) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10702) #ifdef DRXJ_SIGNAL_ACCUM_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10703) rc = get_acc_pkt_err(demod, &pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10704) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10705) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10706) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10708) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10709) if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10710) p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10711) p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10712) p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10713) p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10714) p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10715) p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10716) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10717) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10718) rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10719) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10720) pr_err("error %d getting UCB\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10721) p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10722) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10723) p->block_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10724) p->block_error.stat[0].uvalue += err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10725) p->block_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10726) p->block_count.stat[0].uvalue += pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10729) /* PostViterbi is compute in steps of 10^(-6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10730) rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10731) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10732) pr_err("error %d getting pre-ber\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10733) p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10734) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10735) p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10736) p->pre_bit_error.stat[0].uvalue += ber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10737) p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10738) p->pre_bit_count.stat[0].uvalue += cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10741) rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10742) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10743) pr_err("error %d getting post-ber\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10744) p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10745) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10746) p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10747) p->post_bit_error.stat[0].uvalue += ber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10748) p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10749) p->post_bit_count.stat[0].uvalue += cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10751) rc = get_vsbmer(dev_addr, &mer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10752) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10753) pr_err("error %d getting MER\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10754) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10755) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10756) p->cnr.stat[0].svalue = mer * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10757) p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10761) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10762) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10763) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10764) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10765) rc = ctrl_get_qam_sig_quality(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10766) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10767) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10768) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10771) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10772) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10773) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10776) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10777) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10778) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10781) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10784) * \fn int ctrl_lock_status()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10785) * \brief Retrieve lock status .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10786) * \param dev_addr Pointer to demodulator device address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10787) * \param lock_stat Pointer to lock status structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10788) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10789) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10791) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10792) ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10794) enum drx_standard standard = DRX_STANDARD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10795) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10796) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10797) struct drxjscu_cmd cmd_scu = { /* command */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10798) /* parameter_len */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10799) /* result_len */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10800) /* *parameter */ NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10801) /* *result */ NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10803) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10804) u16 cmd_result[2] = { 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10805) u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10807) /* check arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10808) if ((demod == NULL) || (lock_stat == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10809) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10811) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10812) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10813) standard = ext_attr->standard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10815) *lock_stat = DRX_NOT_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10817) /* define the SCU command code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10818) switch (standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10819) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10820) cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10821) SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10822) demod_lock |= 0x6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10824) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10825) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10826) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10827) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10828) cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10829) SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10830) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10831) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10832) case DRX_STANDARD_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10833) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10834) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10837) /* define the SCU command parameters and execute the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10838) cmd_scu.parameter_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10839) cmd_scu.result_len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10840) cmd_scu.parameter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10841) cmd_scu.result = cmd_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10842) rc = scu_command(dev_addr, &cmd_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10843) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10844) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10845) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10848) /* set the lock status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10849) if (cmd_scu.result[1] < demod_lock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10850) /* 0x0000 NOT LOCKED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10851) *lock_stat = DRX_NOT_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10852) } else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10853) *lock_stat = DRXJ_DEMOD_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10854) } else if (cmd_scu.result[1] <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10855) SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10856) /* 0x8000 DEMOD + FEC LOCKED (system lock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10857) *lock_stat = DRX_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10858) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10859) /* 0xC000 NEVER LOCKED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10860) /* (system will never be able to lock to the signal) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10861) *lock_stat = DRX_NEVER_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10864) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10865) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10866) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10869) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10871) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10872) * \fn int ctrl_set_standard()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10873) * \brief Set modulation standard to be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10874) * \param standard Modulation standard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10875) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10876) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10877) * Setup stuff for the desired demodulation standard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10878) * Disable and power down the previous selected demodulation standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10879) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10881) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10882) ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10884) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10885) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10886) enum drx_standard prev_standard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10888) /* check arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10889) if ((standard == NULL) || (demod == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10890) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10892) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10893) prev_standard = ext_attr->standard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10895) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10896) Stop and power down previous standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10897) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10898) switch (prev_standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10899) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10900) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10901) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10902) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10903) rc = power_down_qam(demod, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10904) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10905) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10906) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10908) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10909) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10910) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10911) rc = power_down_vsb(demod, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10912) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10913) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10914) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10917) case DRX_STANDARD_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10918) /* Do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10919) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10920) case DRX_STANDARD_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10921) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10922) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10925) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10926) Initialize channel independent registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10927) Power up new standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10929) ext_attr->standard = *standard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10931) switch (*standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10932) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10933) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10934) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10935) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10936) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10937) u16 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10938) rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10939) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10940) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10941) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10943) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10944) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10945) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10946) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10947) rc = set_vsb_leak_n_gain(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10948) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10949) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10950) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10953) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10954) ext_attr->standard = DRX_STANDARD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10955) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10959) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10960) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10961) /* Don't know what the standard is now ... try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10962) ext_attr->standard = DRX_STANDARD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10963) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10966) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10968) static void drxj_reset_mode(struct drxj_data *ext_attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10970) /* Initialize default AFE configuration for QAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10971) if (ext_attr->has_lna) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10972) /* IF AGC off, PGA active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10973) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10974) ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10975) ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10976) ext_attr->qam_pga_cfg = 140 + (11 * 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10977) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10978) ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10979) ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10980) ext_attr->vsb_pga_cfg = 140 + (11 * 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10981) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10982) /* IF AGC on, PGA not active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10983) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10984) ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10985) ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10986) ext_attr->qam_if_agc_cfg.min_output_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10987) ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10988) ext_attr->qam_if_agc_cfg.speed = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10989) ext_attr->qam_if_agc_cfg.top = 1297;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10990) ext_attr->qam_pga_cfg = 140;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10991) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10992) ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10993) ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10994) ext_attr->vsb_if_agc_cfg.min_output_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10995) ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10996) ext_attr->vsb_if_agc_cfg.speed = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10997) ext_attr->vsb_if_agc_cfg.top = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10998) ext_attr->vsb_pga_cfg = 140;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11000) /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11001) /* mc has not used them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11002) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11003) ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11004) ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11005) ext_attr->qam_rf_agc_cfg.min_output_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11006) ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11007) ext_attr->qam_rf_agc_cfg.speed = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11008) ext_attr->qam_rf_agc_cfg.top = 9500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11009) ext_attr->qam_rf_agc_cfg.cut_off_current = 4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11010) ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11011) ext_attr->qam_pre_saw_cfg.reference = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11012) ext_attr->qam_pre_saw_cfg.use_pre_saw = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11013) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11014) /* Initialize default AFE configuration for VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11015) ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11016) ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11017) ext_attr->vsb_rf_agc_cfg.min_output_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11018) ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11019) ext_attr->vsb_rf_agc_cfg.speed = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11020) ext_attr->vsb_rf_agc_cfg.top = 9500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11021) ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11022) ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11023) ext_attr->vsb_pre_saw_cfg.reference = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11024) ext_attr->vsb_pre_saw_cfg.use_pre_saw = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11028) * \fn int ctrl_power_mode()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11029) * \brief Set the power mode of the device to the specified power mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11030) * \param demod Pointer to demodulator instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11031) * \param mode Pointer to new power mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11032) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11033) * \retval 0 Success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11034) * \retval -EIO I2C error or other failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11035) * \retval -EINVAL Invalid mode argument.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11036) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11037) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11039) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11040) ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11042) struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11043) struct drxj_data *ext_attr = (struct drxj_data *) NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11044) struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11045) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11046) u16 sio_cc_pwd_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11048) common_attr = (struct drx_common_attr *) demod->my_common_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11049) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11050) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11052) /* Check arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11053) if (mode == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11054) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11056) /* If already in requested power mode, do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11057) if (common_attr->current_power_mode == *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11058) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11060) switch (*mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11061) case DRX_POWER_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11062) case DRXJ_POWER_DOWN_MAIN_PATH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11063) sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11064) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11065) case DRXJ_POWER_DOWN_CORE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11066) sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11067) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11068) case DRXJ_POWER_DOWN_PLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11069) sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11070) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11071) case DRX_POWER_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11072) sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11074) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11075) /* Unknow sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11076) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11077) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11080) /* Check if device needs to be powered up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11081) if ((common_attr->current_power_mode != DRX_POWER_UP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11082) rc = power_up_device(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11083) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11084) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11085) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11089) if (*mode == DRX_POWER_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11090) /* Restore analog & pin configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11092) /* Initialize default AFE configuration for VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11093) drxj_reset_mode(ext_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11094) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11095) /* Power down to requested mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11096) /* Backup some register settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11097) /* Set pins with possible pull-ups connected to them in input mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11098) /* Analog power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11099) /* ADC power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11100) /* Power down device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11101) /* stop all comm_exec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11103) Stop and power down previous standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11106) switch (ext_attr->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11107) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11108) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11109) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11110) rc = power_down_qam(demod, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11111) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11112) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11113) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11116) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11117) rc = power_down_vsb(demod, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11118) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11119) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11120) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11123) case DRX_STANDARD_PAL_SECAM_BG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11124) case DRX_STANDARD_PAL_SECAM_DK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11125) case DRX_STANDARD_PAL_SECAM_I:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11126) case DRX_STANDARD_PAL_SECAM_L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11127) case DRX_STANDARD_PAL_SECAM_LP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11128) case DRX_STANDARD_NTSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11129) case DRX_STANDARD_FM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11130) rc = power_down_atv(demod, ext_attr->standard, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11131) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11132) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11133) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11136) case DRX_STANDARD_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11137) /* Do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11139) case DRX_STANDARD_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11140) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11141) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11143) ext_attr->standard = DRX_STANDARD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11146) if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11147) rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11148) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11149) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11150) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11152) rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11153) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11154) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11155) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11158) if ((*mode != DRX_POWER_UP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11159) /* Initialize HI, wakeup key especially before put IC to sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11160) rc = init_hi(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11161) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11162) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11163) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11166) ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11167) rc = hi_cfg_command(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11168) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11169) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11170) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11175) common_attr->current_power_mode = *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11178) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11179) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11182) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11183) /*== CTRL Set/Get Config related functions ===================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11184) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11187) * \fn int ctrl_set_cfg_pre_saw()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11188) * \brief Set Pre-saw reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11189) * \param demod demod instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11190) * \param u16 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11191) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11192) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11193) * Check arguments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11194) * Dispatch handling to standard specific function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11197) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11198) ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11200) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11201) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11202) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11204) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11205) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11207) /* check arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11208) if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11209) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11210) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11213) /* Only if standard is currently active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11214) if ((ext_attr->standard == pre_saw->standard) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11215) (DRXJ_ISQAMSTD(ext_attr->standard) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11216) DRXJ_ISQAMSTD(pre_saw->standard)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11217) (DRXJ_ISATVSTD(ext_attr->standard) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11218) DRXJ_ISATVSTD(pre_saw->standard))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11219) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11220) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11221) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11222) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11226) /* Store pre-saw settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11227) switch (pre_saw->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11228) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11229) ext_attr->vsb_pre_saw_cfg = *pre_saw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11231) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11232) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11233) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11234) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11235) ext_attr->qam_pre_saw_cfg = *pre_saw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11238) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11239) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11243) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11244) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11247) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11250) * \fn int ctrl_set_cfg_afe_gain()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11251) * \brief Set AFE Gain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11252) * \param demod demod instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11253) * \param u16 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11254) * \return int.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11256) * Check arguments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11257) * Dispatch handling to standard specific function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11258) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11260) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11261) ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11263) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11264) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11265) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11266) u8 gain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11268) /* check arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11269) if (afe_gain == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11270) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11272) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11273) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11275) switch (afe_gain->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11276) case DRX_STANDARD_8VSB: fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11277) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11278) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11279) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11280) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11281) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11282) /* Do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11284) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11285) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11288) /* TODO PGA gain is also written by microcode (at least by QAM and VSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11289) So I (PJ) think interface requires choice between auto, user mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11291) if (afe_gain->gain >= 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11292) gain = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11293) else if (afe_gain->gain <= 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11294) gain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11295) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11296) gain = (afe_gain->gain - 140 + 6) / 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11298) /* Only if standard is currently active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11299) if (ext_attr->standard == afe_gain->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11300) rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11301) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11302) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11303) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11307) /* Store AFE Gain settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11308) switch (afe_gain->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11309) case DRX_STANDARD_8VSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11310) ext_attr->vsb_pga_cfg = gain * 13 + 140;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11312) #ifndef DRXJ_VSB_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11313) case DRX_STANDARD_ITU_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11314) case DRX_STANDARD_ITU_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11315) case DRX_STANDARD_ITU_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11316) ext_attr->qam_pga_cfg = gain * 13 + 140;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11318) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11319) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11320) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11324) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11325) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11328) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11331) /*=============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11332) ===== EXPORTED FUNCTIONS ====================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11334) static int drx_ctrl_u_code(struct drx_demod_instance *demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11335) struct drxu_code_info *mc_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11336) enum drxu_code_action action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11337) static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11340) * \fn drxj_open()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11341) * \brief Open the demod instance, configure device, configure drxdriver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11342) * \return Status_t Return status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11343) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11344) * drxj_open() can be called with a NULL ucode image => no ucode upload.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11345) * This means that drxj_open() must NOT contain SCU commands or, in general,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11346) * rely on SCU or AUD ucode to be present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11347) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11350) static int drxj_open(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11352) struct i2c_device_addr *dev_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11353) struct drxj_data *ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11354) struct drx_common_attr *common_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11355) u32 driver_version = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11356) struct drxu_code_info ucode_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11357) struct drx_cfg_mpeg_output cfg_mpeg_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11358) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11359) enum drx_power_mode power_mode = DRX_POWER_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11361) if ((demod == NULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11362) (demod->my_common_attr == NULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11363) (demod->my_ext_attr == NULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11364) (demod->my_i2c_dev_addr == NULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11365) (demod->my_common_attr->is_opened)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11366) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11369) /* Check arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11370) if (demod->my_ext_attr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11373) dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11374) ext_attr = (struct drxj_data *) demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11375) common_attr = (struct drx_common_attr *) demod->my_common_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11377) rc = ctrl_power_mode(demod, &power_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11378) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11379) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11380) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11382) if (power_mode != DRX_POWER_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11383) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11384) pr_err("failed to powerup device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11385) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11388) /* has to be in front of setIqmAf and setOrxNsuAox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11389) rc = get_device_capabilities(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11390) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11391) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11392) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11396) * Soft reset of sys- and osc-clockdomain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11398) * HACK: On windows, it writes a 0x07 here, instead of just 0x03.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11399) * As we didn't load the firmware here yet, we should do the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11400) * Btw, this is coherent with DRX-K, where we send reset codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11401) * for modulation (OFTM, in DRX-k), SYS and OSC clock domains.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11403) rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11404) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11405) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11406) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11408) rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11409) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11410) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11411) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11413) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11415) /* TODO first make sure that everything keeps working before enabling this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11416) /* PowerDownAnalogBlocks() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11417) rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11418) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11419) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11420) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11423) rc = set_iqm_af(demod, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11424) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11425) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11426) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11428) rc = set_orx_nsu_aox(demod, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11429) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11430) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11431) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11434) rc = init_hi(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11435) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11436) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11437) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11440) /* disable mpegoutput pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11441) memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11442) cfg_mpeg_output.enable_mpeg_output = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11444) rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11445) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11446) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11447) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11449) /* Stop AUD Inform SetAudio it will need to do all setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11450) rc = power_down_aud(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11451) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11452) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11453) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11455) /* Stop SCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11456) rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11457) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11458) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11459) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11462) /* Upload microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11463) if (common_attr->microcode_file != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11464) /* Dirty trick to use common ucode upload & verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11465) pretend device is already open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11466) common_attr->is_opened = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11467) ucode_info.mc_file = common_attr->microcode_file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11469) if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11470) pr_err("Should powerup before loading the firmware.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11471) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11474) rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11475) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11476) pr_err("error %d while uploading the firmware\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11477) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11479) if (common_attr->verify_microcode == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11480) rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11481) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11482) pr_err("error %d while verifying the firmware\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11483) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11484) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11487) common_attr->is_opened = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11490) /* Run SCU for a little while to initialize microcode version numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11491) rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11492) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11493) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11494) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11497) /* Initialize scan timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11498) common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11499) common_attr->scan_desired_lock = DRX_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11501) drxj_reset_mode(ext_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11502) ext_attr->standard = DRX_STANDARD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11504) rc = smart_ant_init(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11505) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11506) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11507) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11510) /* Stamp driver version number in SCU data RAM in BCD code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11511) Done to enable field application engineers to retrieve drxdriver version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11512) via I2C from SCU RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11514) driver_version = (VERSION_MAJOR / 100) % 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11515) driver_version <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11516) driver_version += (VERSION_MAJOR / 10) % 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11517) driver_version <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11518) driver_version += (VERSION_MAJOR % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11519) driver_version <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11520) driver_version += (VERSION_MINOR % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11521) driver_version <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11522) driver_version += (VERSION_PATCH / 1000) % 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11523) driver_version <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11524) driver_version += (VERSION_PATCH / 100) % 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11525) driver_version <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11526) driver_version += (VERSION_PATCH / 10) % 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11527) driver_version <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11528) driver_version += (VERSION_PATCH % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11529) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11530) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11531) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11532) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11534) rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11535) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11536) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11537) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11540) rc = ctrl_set_oob(demod, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11541) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11542) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11543) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11546) /* refresh the audio data structure with default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11547) ext_attr->aud_data = drxj_default_aud_data_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11549) demod->my_common_attr->is_opened = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11550) drxj_set_lna_state(demod, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11552) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11553) common_attr->is_opened = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11554) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11557) /*============================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11559) * \fn drxj_close()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11560) * \brief Close the demod instance, power down the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11561) * \return Status_t Return status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11562) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11564) static int drxj_close(struct drx_demod_instance *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11566) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11567) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11568) enum drx_power_mode power_mode = DRX_POWER_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11570) if ((demod->my_common_attr == NULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11571) (demod->my_ext_attr == NULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11572) (demod->my_i2c_dev_addr == NULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11573) (!demod->my_common_attr->is_opened)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11574) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11577) /* power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11578) rc = ctrl_power_mode(demod, &power_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11579) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11580) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11581) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11584) rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11585) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11586) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11587) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11589) power_mode = DRX_POWER_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11590) rc = ctrl_power_mode(demod, &power_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11591) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11592) pr_err("error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11593) goto rw_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11596) DRX_ATTR_ISOPENED(demod) = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11599) rw_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11600) DRX_ATTR_ISOPENED(demod) = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11602) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11606) * Microcode related functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11610) * drx_u_code_compute_crc - Compute CRC of block of microcode data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11611) * @block_data: Pointer to microcode data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11612) * @nr_words: Size of microcode block (number of 16 bits words).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11613) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11614) * returns The computed CRC residue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11616) static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11618) u16 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11619) u16 j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11620) u32 crc_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11621) u32 carry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11623) while (i < nr_words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11624) crc_word |= (u32)be16_to_cpu(*(__be16 *)(block_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11625) for (j = 0; j < 16; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11626) crc_word <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11627) if (carry != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11628) crc_word ^= 0x80050000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11629) carry = crc_word & 0x80000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11631) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11632) block_data += (sizeof(u16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11634) return (u16)(crc_word >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11638) * drx_check_firmware - checks if the loaded firmware is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11640) * @demod: demod structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11641) * @mc_data: pointer to the start of the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11642) * @size: firmware size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11644) static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11645) unsigned size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11647) struct drxu_code_block_hdr block_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11648) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11649) unsigned count = 2 * sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11650) u32 mc_dev_type, mc_version, mc_base_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11651) u16 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data + sizeof(u16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11654) * Scan microcode blocks first for version info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11655) * and firmware check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11658) /* Clear version block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11659) DRX_ATTR_MCRECORD(demod).aux_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11660) DRX_ATTR_MCRECORD(demod).mc_dev_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11661) DRX_ATTR_MCRECORD(demod).mc_version = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11662) DRX_ATTR_MCRECORD(demod).mc_base_version = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11664) for (i = 0; i < mc_nr_of_blks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11665) if (count + 3 * sizeof(u16) + sizeof(u32) > size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11666) goto eof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11668) /* Process block header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11669) block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data + count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11670) count += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11671) block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data + count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11672) count += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11673) block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data + count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11674) count += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11675) block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data + count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11676) count += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11678) pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11679) count, block_hdr.addr, block_hdr.size, block_hdr.flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11680) block_hdr.CRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11682) if (block_hdr.flags & 0x8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11683) u8 *auxblk = ((void *)mc_data) + block_hdr.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11684) u16 auxtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11686) if (block_hdr.addr + sizeof(u16) > size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11687) goto eof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11689) auxtype = be16_to_cpu(*(__be16 *)(auxblk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11691) /* Aux block. Check type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11692) if (DRX_ISMCVERTYPE(auxtype)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11693) if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11694) goto eof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11696) auxblk += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11697) mc_dev_type = be32_to_cpu(*(__be32 *)(auxblk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11698) auxblk += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11699) mc_version = be32_to_cpu(*(__be32 *)(auxblk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11700) auxblk += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11701) mc_base_version = be32_to_cpu(*(__be32 *)(auxblk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11703) DRX_ATTR_MCRECORD(demod).aux_type = auxtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11704) DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11705) DRX_ATTR_MCRECORD(demod).mc_version = mc_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11706) DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11708) pr_info("Firmware dev %x, ver %x, base ver %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11709) mc_dev_type, mc_version, mc_base_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11712) } else if (count + block_hdr.size * sizeof(u16) > size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11713) goto eof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11715) count += block_hdr.size * sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11718) eof:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11719) pr_err("Firmware is truncated at pos %u/%u\n", count, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11720) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11723) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11724) * drx_ctrl_u_code - Handle microcode upload or verify.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11725) * @dev_addr: Address of device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11726) * @mc_info: Pointer to information about microcode data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11727) * @action: Either UCODE_UPLOAD or UCODE_VERIFY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11728) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11729) * This function returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11730) * 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11731) * - In case of UCODE_UPLOAD: code is successfully uploaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11732) * - In case of UCODE_VERIFY: image on device is equal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11733) * image provided to this control function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11734) * -EIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11735) * - In case of UCODE_UPLOAD: I2C error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11736) * - In case of UCODE_VERIFY: I2C error or image on device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11737) * is not equal to image provided to this control function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11738) * -EINVAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11739) * - Invalid arguments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11740) * - Provided image is corrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11742) static int drx_ctrl_u_code(struct drx_demod_instance *demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11743) struct drxu_code_info *mc_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11744) enum drxu_code_action action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11746) struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11747) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11748) u16 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11749) u16 mc_nr_of_blks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11750) u16 mc_magic_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11751) const u8 *mc_data_init = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11752) u8 *mc_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11753) unsigned size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11754) char *mc_file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11756) /* Check arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11757) if (!mc_info || !mc_info->mc_file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11758) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11760) mc_file = mc_info->mc_file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11762) if (!demod->firmware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11763) const struct firmware *fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11765) rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11766) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11767) pr_err("Couldn't read firmware %s\n", mc_file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11768) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11770) demod->firmware = fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11772) if (demod->firmware->size < 2 * sizeof(u16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11773) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11774) pr_err("Firmware is too short!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11775) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11778) pr_info("Firmware %s, size %zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11779) mc_file, demod->firmware->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11782) mc_data_init = demod->firmware->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11783) size = demod->firmware->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11785) mc_data = (void *)mc_data_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11786) /* Check data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11787) mc_magic_word = be16_to_cpu(*(__be16 *)(mc_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11788) mc_data += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11789) mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11790) mc_data += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11792) if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11793) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11794) pr_err("Firmware magic word doesn't match\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11795) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11798) if (action == UCODE_UPLOAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11799) rc = drx_check_firmware(demod, (u8 *)mc_data_init, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11800) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11801) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11802) pr_info("Uploading firmware %s\n", mc_file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11803) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11804) pr_info("Verifying if firmware upload was ok.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11807) /* Process microcode blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11808) for (i = 0; i < mc_nr_of_blks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11809) struct drxu_code_block_hdr block_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11810) u16 mc_block_nr_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11812) /* Process block header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11813) block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11814) mc_data += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11815) block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11816) mc_data += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11817) block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11818) mc_data += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11819) block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11820) mc_data += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11822) pr_debug("%zd: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11823) (mc_data - mc_data_init), block_hdr.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11824) block_hdr.size, block_hdr.flags, block_hdr.CRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11826) /* Check block header on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11827) - data larger than 64Kb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11828) - if CRC enabled check CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11830) if ((block_hdr.size > 0x7FFF) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11831) (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11832) (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11833) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11834) /* Wrong data ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11835) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11836) pr_err("firmware CRC is wrong\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11837) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11840) if (!block_hdr.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11841) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11843) mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11845) /* Perform the desired action */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11846) switch (action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11847) case UCODE_UPLOAD: /* Upload microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11848) if (drxdap_fasi_write_block(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11849) block_hdr.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11850) mc_block_nr_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11851) mc_data, 0x0000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11852) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11853) pr_err("error writing firmware at pos %zd\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11854) mc_data - mc_data_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11855) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11858) case UCODE_VERIFY: { /* Verify uploaded microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11859) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11860) u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11861) u32 bytes_to_comp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11862) u32 bytes_left = mc_block_nr_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11863) u32 curr_addr = block_hdr.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11864) u8 *curr_ptr = mc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11866) while (bytes_left != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11867) if (bytes_left > DRX_UCODE_MAX_BUF_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11868) bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11869) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11870) bytes_to_comp = bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11872) if (drxdap_fasi_read_block(dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11873) curr_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11874) (u16)bytes_to_comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11875) (u8 *)mc_data_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11876) 0x0000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11877) pr_err("error reading firmware at pos %zd\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11878) mc_data - mc_data_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11879) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11882) result = memcmp(curr_ptr, mc_data_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11883) bytes_to_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11885) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11886) pr_err("error verifying firmware at pos %zd\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11887) mc_data - mc_data_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11888) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11891) curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11892) curr_ptr =&(curr_ptr[bytes_to_comp]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11893) bytes_left -=((u32) bytes_to_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11895) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11897) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11898) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11899) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11902) mc_data += mc_block_nr_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11907) release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11908) release_firmware(demod->firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11909) demod->firmware = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11911) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11914) /* caller is expected to check if lna is supported before enabling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11915) static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11917) struct drxuio_cfg uio_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11918) struct drxuio_data uio_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11919) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11921) uio_cfg.uio = DRX_UIO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11922) uio_cfg.mode = DRX_UIO_MODE_READWRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11923) /* Configure user-I/O #3: enable read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11924) result = ctrl_set_uio_cfg(demod, &uio_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11925) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11926) pr_err("Failed to setup LNA GPIO!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11927) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11930) uio_data.uio = DRX_UIO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11931) uio_data.value = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11932) result = ctrl_uio_write(demod, &uio_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11933) if (result != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11934) pr_err("Failed to %sable LNA!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11935) state ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11936) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11938) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11942) * The Linux DVB Driver for Micronas DRX39xx family (drx3933j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11943) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11944) * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11947) static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11949) struct drx39xxj_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11950) struct drx_demod_instance *demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11951) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11952) enum drx_power_mode power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11954) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11955) power_mode = DRX_POWER_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11956) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11957) power_mode = DRX_POWER_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11959) result = ctrl_power_mode(demod, &power_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11960) if (result != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11961) pr_err("Power state change failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11962) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11965) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11968) static int drx39xxj_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11970) struct drx39xxj_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11971) struct drx_demod_instance *demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11972) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11973) enum drx_lock_status lock_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11975) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11977) result = ctrl_lock_status(demod, &lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11978) if (result != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11979) pr_err("drx39xxj: could not get lock status!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11980) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11983) switch (lock_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11984) case DRX_NEVER_LOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11985) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11986) pr_err("drx says NEVER_LOCK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11988) case DRX_NOT_LOCKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11989) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11991) case DRX_LOCK_STATE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11992) case DRX_LOCK_STATE_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11993) case DRX_LOCK_STATE_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11994) case DRX_LOCK_STATE_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11995) case DRX_LOCK_STATE_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11996) case DRX_LOCK_STATE_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11997) case DRX_LOCK_STATE_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11998) case DRX_LOCK_STATE_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11999) case DRX_LOCK_STATE_9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12000) *status = FE_HAS_SIGNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12001) | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12002) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12003) case DRX_LOCKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12004) *status = FE_HAS_SIGNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12005) | FE_HAS_CARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12006) | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12008) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12009) pr_err("Lock state unknown %d\n", lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12011) ctrl_sig_quality(demod, lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12013) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12016) static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12018) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12020) if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12021) *ber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12022) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12025) if (!p->pre_bit_count.stat[0].uvalue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12026) if (!p->pre_bit_error.stat[0].uvalue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12027) *ber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12028) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12029) *ber = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12030) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12031) *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12032) p->pre_bit_count.stat[0].uvalue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12034) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12037) static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12038) u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12040) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12042) if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12043) *strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12044) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12047) *strength = p->strength.stat[0].uvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12051) static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12053) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12054) u64 tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12056) if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12057) *snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12058) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12061) tmp64 = p->cnr.stat[0].svalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12062) do_div(tmp64, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12063) *snr = tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12064) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12067) static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12069) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12071) if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12072) *ucb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12073) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12076) *ucb = p->block_error.stat[0].uvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12077) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12080) static int drx39xxj_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12082) #ifdef DJH_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12083) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12084) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12085) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12086) struct drx39xxj_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12087) struct drx_demod_instance *demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12088) enum drx_standard standard = DRX_STANDARD_8VSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12089) struct drx_channel channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12090) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12091) static const struct drx_channel def_channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12092) /* frequency */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12093) /* bandwidth */ DRX_BANDWIDTH_6MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12094) /* mirror */ DRX_MIRROR_NO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12095) /* constellation */ DRX_CONSTELLATION_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12096) /* hierarchy */ DRX_HIERARCHY_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12097) /* priority */ DRX_PRIORITY_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12098) /* coderate */ DRX_CODERATE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12099) /* guard */ DRX_GUARD_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12100) /* fftmode */ DRX_FFTMODE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12101) /* classification */ DRX_CLASSIFICATION_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12102) /* symbolrate */ 5057000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12103) /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12104) /* ldpc */ DRX_LDPC_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12105) /* carrier */ DRX_CARRIER_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12106) /* frame mode */ DRX_FRAMEMODE_UNKNOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12108) u32 constellation = DRX_CONSTELLATION_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12110) /* Bring the demod out of sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12111) drx39xxj_set_powerstate(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12113) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12114) u32 int_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12116) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12117) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12119) /* Set tuner to desired frequency and standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12120) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12122) /* Use the tuner's IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12123) if (fe->ops.tuner_ops.get_if_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12124) fe->ops.tuner_ops.get_if_frequency(fe, &int_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12125) demod->my_common_attr->intermediate_freq = int_freq / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12128) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12129) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12132) switch (p->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12133) case SYS_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12134) standard = DRX_STANDARD_8VSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12136) case SYS_DVBC_ANNEX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12137) standard = DRX_STANDARD_ITU_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12139) switch (p->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12140) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12141) constellation = DRX_CONSTELLATION_QAM64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12143) case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12144) constellation = DRX_CONSTELLATION_QAM256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12146) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12147) constellation = DRX_CONSTELLATION_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12151) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12152) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12154) /* Set the standard (will be powered up if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12155) result = ctrl_set_standard(demod, &standard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12156) if (result != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12157) pr_err("Failed to set standard! result=%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12158) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12159) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12162) /* set channel parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12163) channel = def_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12164) channel.frequency = p->frequency / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12165) channel.bandwidth = DRX_BANDWIDTH_6MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12166) channel.constellation = constellation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12168) /* program channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12169) result = ctrl_set_channel(demod, &channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12170) if (result != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12171) pr_err("Failed to set channel!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12172) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12174) /* Just for giggles, let's shut off the LNA again.... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12175) drxj_set_lna_state(demod, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12177) /* After set_frontend, except for strength, stats aren't available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12178) p->strength.stat[0].scale = FE_SCALE_RELATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12183) static int drx39xxj_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12185) /* power-down the demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12186) return drx39xxj_set_powerstate(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12189) static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12191) struct drx39xxj_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12192) struct drx_demod_instance *demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12193) bool i2c_gate_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12194) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12196) #ifdef DJH_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12197) pr_debug("i2c gate call: enable=%d state=%d\n", enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12198) state->i2c_gate_open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12201) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12202) i2c_gate_state = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12203) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12204) i2c_gate_state = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12206) if (state->i2c_gate_open == enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12207) /* We're already in the desired state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12211) result = ctrl_i2c_bridge(demod, &i2c_gate_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12212) if (result != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12213) pr_err("drx39xxj: could not open i2c gate [%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12214) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12215) dump_stack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12217) state->i2c_gate_open = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12222) static int drx39xxj_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12224) struct drx39xxj_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12225) struct drx_demod_instance *demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12226) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12228) if (fe->exit == DVB_FE_DEVICE_RESUME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12229) /* so drxj_open() does what it needs to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12230) demod->my_common_attr->is_opened = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12231) rc = drxj_open(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12232) if (rc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12233) pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12234) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12235) drx39xxj_set_powerstate(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12237) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12240) static int drx39xxj_set_lna(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12242) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12243) struct drx39xxj_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12244) struct drx_demod_instance *demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12245) struct drxj_data *ext_attr = demod->my_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12247) if (c->lna) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12248) if (!ext_attr->has_lna) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12249) pr_err("LNA is not supported on this device!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12255) return drxj_set_lna_state(demod, c->lna);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12258) static int drx39xxj_get_tune_settings(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12259) struct dvb_frontend_tune_settings *tune)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12261) tune->min_delay_ms = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12265) static void drx39xxj_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12267) struct drx39xxj_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12268) struct drx_demod_instance *demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12270) /* if device is removed don't access it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12271) if (fe->exit != DVB_FE_DEVICE_REMOVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12272) drxj_close(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12274) kfree(demod->my_ext_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12275) kfree(demod->my_common_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12276) kfree(demod->my_i2c_dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12277) release_firmware(demod->firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12278) kfree(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12279) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12282) static const struct dvb_frontend_ops drx39xxj_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12284) struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12286) struct drx39xxj_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12287) struct i2c_device_addr *demod_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12288) struct drx_common_attr *demod_comm_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12289) struct drxj_data *demod_ext_attr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12290) struct drx_demod_instance *demod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12291) struct dtv_frontend_properties *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12292) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12294) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12295) state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12296) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12297) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12299) demod = kmemdup(&drxj_default_demod_g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12300) sizeof(struct drx_demod_instance), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12301) if (demod == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12302) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12304) demod_addr = kmemdup(&drxj_default_addr_g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12305) sizeof(struct i2c_device_addr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12306) if (demod_addr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12307) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12309) demod_comm_attr = kmemdup(&drxj_default_comm_attr_g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12310) sizeof(struct drx_common_attr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12311) if (demod_comm_attr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12312) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12314) demod_ext_attr = kmemdup(&drxj_data_g, sizeof(struct drxj_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12315) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12316) if (demod_ext_attr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12317) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12319) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12320) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12321) state->demod = demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12323) /* setup the demod data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12324) demod->my_i2c_dev_addr = demod_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12325) demod->my_common_attr = demod_comm_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12326) demod->my_i2c_dev_addr->user_data = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12327) demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12328) demod->my_common_attr->verify_microcode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12329) demod->my_common_attr->intermediate_freq = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12330) demod->my_common_attr->current_power_mode = DRX_POWER_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12331) demod->my_ext_attr = demod_ext_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12332) ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12333) demod->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12335) result = drxj_open(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12336) if (result != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12337) pr_err("DRX open failed! Aborting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12338) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12341) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12342) memcpy(&state->frontend.ops, &drx39xxj_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12343) sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12345) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12347) /* Initialize stats - needed for DVBv5 stats to work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12348) p = &state->frontend.dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12349) p->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12350) p->pre_bit_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12351) p->pre_bit_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12352) p->post_bit_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12353) p->post_bit_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12354) p->block_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12355) p->block_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12356) p->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12358) p->strength.stat[0].scale = FE_SCALE_RELATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12359) p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12360) p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12361) p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12362) p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12363) p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12364) p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12365) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12367) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12369) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12370) kfree(demod_ext_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12371) kfree(demod_comm_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12372) kfree(demod_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12373) kfree(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12374) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12376) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12378) EXPORT_SYMBOL(drx39xxj_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12380) static const struct dvb_frontend_ops drx39xxj_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12381) .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12382) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12383) .name = "Micronas DRX39xxj family Frontend",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12384) .frequency_min_hz = 51 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12385) .frequency_max_hz = 858 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12386) .frequency_stepsize_hz = 62500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12387) .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12390) .init = drx39xxj_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12391) .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12392) .sleep = drx39xxj_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12393) .set_frontend = drx39xxj_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12394) .get_tune_settings = drx39xxj_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12395) .read_status = drx39xxj_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12396) .read_ber = drx39xxj_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12397) .read_signal_strength = drx39xxj_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12398) .read_snr = drx39xxj_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12399) .read_ucblocks = drx39xxj_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12400) .release = drx39xxj_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12401) .set_lna = drx39xxj_set_lna,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12404) MODULE_DESCRIPTION("Micronas DRX39xxj Frontend");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12405) MODULE_AUTHOR("Devin Heitmueller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12406) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12407) MODULE_FIRMWARE(DRX39XX_MAIN_FIRMWARE);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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