Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef DIBX000_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define DIBX000_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) enum dibx000_i2c_interface {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 	DIBX000_I2C_INTERFACE_TUNER = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 	DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 	DIBX000_I2C_INTERFACE_GPIO_3_4 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 	DIBX000_I2C_INTERFACE_GPIO_6_7 = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) struct dibx000_i2c_master {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define DIB3000MC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define DIB7000   2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DIB7000P  11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DIB7000MC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DIB8000   13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	u16 device_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	enum dibx000_i2c_interface selected_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /*	struct i2c_adapter  tuner_i2c_adap; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct i2c_adapter gated_tuner_i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct i2c_adapter master_i2c_adap_gpio12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct i2c_adapter master_i2c_adap_gpio34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct i2c_adapter master_i2c_adap_gpio67;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct i2c_adapter *i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u8 i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u16 base_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	/* for the I2C transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct i2c_msg msg[34];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u8 i2c_write_buffer[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u8 i2c_read_buffer[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct mutex i2c_buffer_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 					u16 device_rev, struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 					u8 i2c_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 							*mst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 							enum dibx000_i2c_interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 							intf, int gating);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) extern int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define BAND_LBAND 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define BAND_UHF   0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define BAND_VHF   0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define BAND_SBAND 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define BAND_FM	   0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define BAND_CBAND 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 									(freq_kHz) <= 115000 ? BAND_FM : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 									(freq_kHz) <= 250000 ? BAND_VHF : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 									(freq_kHz) <= 863000 ? BAND_UHF : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 									(freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) struct dibx000_agc_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/* defines the capabilities of this AGC-setting - using the BAND_-defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u8 band_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u16 setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u16 inv_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u16 time_stabiliz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u8 alpha_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u16 thlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u8 wbd_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u16 wbd_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u8 wbd_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u8 wbd_alpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u16 agc1_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u16 agc1_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u16 agc2_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u16 agc2_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u8 agc1_pt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u8 agc1_pt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u8 agc1_pt3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u8 agc1_slope1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u8 agc1_slope2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u8 agc2_pt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u8 agc2_pt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u8 agc2_slope1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u8 agc2_slope2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u8 alpha_mant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u8 alpha_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u8 beta_mant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u8 beta_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u8 perform_agc_softsplit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		u16 min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		u16 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		u16 min_thres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		u16 max_thres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	} split;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct dibx000_bandwidth_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u32 internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32 sampling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u8 pll_prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u8 pll_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u8 pll_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u8 pll_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u8 pll_bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u8 enable_refdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u8 bypclk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u8 IO_CLK_en_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u8 ADClkSrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u8 modulo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u16 sad_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	u32 ifreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u32 timf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	u32 xtal_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) enum dibx000_adc_states {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	DIBX000_SLOW_ADC_ON = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	DIBX000_SLOW_ADC_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	DIBX000_ADC_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	DIBX000_ADC_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	DIBX000_VBG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	DIBX000_VBG_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BANDWIDTH_TO_KHZ(v)	((v) / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BANDWIDTH_TO_HZ(v)	((v) * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Chip output mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OUTMODE_HIGH_Z              0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OUTMODE_MPEG2_PAR_GATED_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OUTMODE_MPEG2_PAR_CONT_CLK  2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OUTMODE_MPEG2_SERIAL        7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OUTMODE_DIVERSITY           4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OUTMODE_MPEG2_FIFO          5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OUTMODE_ANALOG_ADC          6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define INPUT_MODE_OFF                0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define INPUT_MODE_DIVERSITY          0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define INPUT_MODE_MPEG               0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) enum frontend_tune_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	CT_TUNER_START = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	CT_TUNER_STEP_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	CT_TUNER_STEP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	CT_TUNER_STEP_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	CT_TUNER_STEP_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	CT_TUNER_STEP_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	CT_TUNER_STEP_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	CT_TUNER_STEP_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	CT_TUNER_STEP_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	CT_TUNER_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	CT_AGC_START = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	CT_AGC_STEP_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	CT_AGC_STEP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	CT_AGC_STEP_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	CT_AGC_STEP_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	CT_AGC_STEP_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	CT_AGC_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	CT_DEMOD_START = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	CT_DEMOD_STEP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	CT_DEMOD_STEP_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	CT_DEMOD_STEP_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	CT_DEMOD_STEP_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	CT_DEMOD_STEP_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	CT_DEMOD_STEP_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	CT_DEMOD_STEP_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	CT_DEMOD_STEP_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	CT_DEMOD_STEP_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	CT_DEMOD_STEP_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	CT_DEMOD_STEP_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	CT_DEMOD_SEARCH_NEXT = 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	CT_DEMOD_STEP_LOCKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	CT_DEMOD_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	CT_DONE = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	CT_SHUTDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct dvb_frontend_parametersContext {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CHANNEL_STATUS_PARAMETERS_UNKNOWN   0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CHANNEL_STATUS_PARAMETERS_SET       0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u32 tune_time_estimation[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	s32 tps_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	u16 tps[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define FE_STATUS_TUNE_FAILED          0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define FE_STATUS_TUNE_TIMED_OUT      -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define FE_STATUS_TUNE_TIME_TOO_SHORT -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define FE_STATUS_TUNE_PENDING        -3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define FE_STATUS_STD_SUCCESS         -4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define FE_STATUS_FFT_SUCCESS         -5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define FE_STATUS_DEMOD_SUCCESS       -6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define FE_STATUS_LOCKED              -7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define FE_STATUS_DATA_LOCKED         -8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define FE_CALLBACK_TIME_NEVER 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DATA_BUS_ACCESS_MODE_8BIT                 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DATA_BUS_ACCESS_MODE_16BIT                0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct dibGPIOFunction {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define BOARD_GPIO_COMPONENT_BUS_ADAPTER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define BOARD_GPIO_COMPONENT_DEMOD       2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	u8 component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define BOARD_GPIO_FUNCTION_BOARD_ON      1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define BOARD_GPIO_FUNCTION_BOARD_OFF     2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define BOARD_GPIO_FUNCTION_COMPONENT_ON  3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define BOARD_GPIO_FUNCTION_COMPONENT_OFF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define BOARD_GPIO_FUNCTION_SUBBAND_PWM   5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define BOARD_GPIO_FUNCTION_SUBBAND_GPIO   6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	u8 function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* mask, direction and value are used specify which GPIO to change GPIO0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  * is LSB and possible GPIO31 is MSB.  The same bit-position as in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  * mask is used for the direction and the value. Direction == 1 is OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  * 0 == IN. For direction "OUT" value is either 1 or 0, for direction IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  * value has no meaning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  * In case of BOARD_GPIO_FUNCTION_PWM mask is giving the GPIO to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  * used to do the PWM. Direction gives the PWModulator to be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  * Value gives the PWM value in device-dependent scale.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	u32 direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MAX_NB_SUBBANDS   8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct dibSubbandSelection {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	u8  size; /* Actual number of subbands. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		u16 f_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		struct dibGPIOFunction gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	} subband[MAX_NB_SUBBANDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DEMOD_TIMF_SET    0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DEMOD_TIMF_GET    0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DEMOD_TIMF_UPDATE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MPEG_ON_DIBTX		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DIV_ON_DIBTX		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define ADC_ON_DIBTX		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DEMOUT_ON_HOSTBUS	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DIBTX_ON_HOSTBUS	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MPEG_ON_HOSTBUS		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #endif