Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef DIB7000P_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define DIB7000P_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include "dibx000_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) struct dib7000p_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	u8 output_mpeg2_in_188_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	u8 hostbus_diversity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	u8 tuner_is_baseband;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	int (*update_lna) (struct dvb_frontend *, u16 agc_global);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	u8 agc_config_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	struct dibx000_agc_config *agc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	struct dibx000_bandwidth_config *bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DIB7000P_GPIO_DEFAULT_DIRECTIONS 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	u16 gpio_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DIB7000P_GPIO_DEFAULT_VALUES     0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	u16 gpio_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DIB7000P_GPIO_PWM_POS0(v)        ((v & 0xf) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DIB7000P_GPIO_PWM_POS1(v)        ((v & 0xf) << 8 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DIB7000P_GPIO_PWM_POS2(v)        ((v & 0xf) << 4 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DIB7000P_GPIO_PWM_POS3(v)         (v & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DIB7000P_GPIO_DEFAULT_PWM_POS    0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	u16 gpio_pwm_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	u16 pwm_freq_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	u8 quartz_direct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	u8 spur_protect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	int (*agc_control) (struct dvb_frontend *, u8 before);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	u8 output_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	u8 disable_sample_and_hold:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	u8 enable_current_mirror:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	u16 diversity_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	u8 default_i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	u8 enMpegOutput:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DEFAULT_DIB7000P_I2C_ADDRESS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct dib7000p_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	int (*set_wbd_ref)(struct dvb_frontend *demod, u16 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	int (*get_agc_values)(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		u16 *agc_global, u16 *agc1, u16 *agc2, u16 *wbd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	int (*set_agc1_min)(struct dvb_frontend *fe, u16 v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	int (*update_pll)(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	int (*set_gpio)(struct dvb_frontend *demod, u8 num, u8 dir, u8 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	u32 (*ctrl_timf)(struct dvb_frontend *fe, u8 op, u32 timf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	int (*dib7000pc_detection)(struct i2c_adapter *i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	struct i2c_adapter *(*get_i2c_master)(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	int (*pid_filter_ctrl)(struct dvb_frontend *fe, u8 onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	int (*pid_filter)(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	int (*i2c_enumeration)(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	struct i2c_adapter *(*get_i2c_tuner)(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	int (*tuner_sleep)(struct dvb_frontend *fe, int onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	int (*get_adc_power)(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	int (*slave_reset)(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	struct dvb_frontend *(*init)(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #if IS_REACHABLE(CONFIG_DVB_DIB7000P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void *dib7000p_attach(struct dib7000p_ops *ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline void *dib7000p_attach(struct dib7000p_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif