^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Linux-DVB Driver for DiBcom's second generation DiB7000P (PC).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <media/dvb_math.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "dib7000p.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int buggy_sfn_workaround;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) module_param(buggy_sfn_workaround, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define dprintk(fmt, arg...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) printk(KERN_DEBUG pr_fmt("%s: " fmt), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __func__, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct i2c_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct i2c_adapter *i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct dib7000p_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct dvb_frontend demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct dib7000p_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct i2c_adapter *i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct dibx000_i2c_master i2c_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u16 wbd_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 current_band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 current_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct dibx000_agc_config *current_agc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 timf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 div_force_off:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 div_state:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u16 div_sync_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 agc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u16 gpio_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u16 gpio_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 sfn_workaround_active:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SOC7090 0x7090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u16 tuner_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct i2c_adapter dib7090_tuner_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* for the I2C transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 i2c_write_buffer[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 i2c_read_buffer[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct mutex i2c_buffer_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 input_mode_mpeg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* for DVBv5 stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) s64 old_ucb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long per_jiffies_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long ber_jiffies_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long get_stats_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum dib7000p_power_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) DIB7000P_POWER_ALL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DIB7000P_POWER_ANALOG_ADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DIB7000P_POWER_INTERFACE_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* dib7090 specific functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dprintk("could not acquire lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) state->i2c_write_buffer[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) state->i2c_write_buffer[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) state->msg[0].addr = state->i2c_addr >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) state->msg[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) state->msg[0].buf = state->i2c_write_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) state->msg[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) state->msg[1].addr = state->i2c_addr >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) state->msg[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) state->msg[1].buf = state->i2c_read_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) state->msg[1].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dprintk("i2c read error on %d\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mutex_unlock(&state->i2c_buffer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dprintk("could not acquire lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) state->i2c_write_buffer[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) state->i2c_write_buffer[2] = (val >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) state->i2c_write_buffer[3] = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) memset(&state->msg[0], 0, sizeof(struct i2c_msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) state->msg[0].addr = state->i2c_addr >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) state->msg[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) state->msg[0].buf = state->i2c_write_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) state->msg[0].len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) -EREMOTEIO : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mutex_unlock(&state->i2c_buffer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u16 l = 0, r, *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) n = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) l = *n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) while (l) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) r = *n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dib7000p_write_word(state, r, *n++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) r++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) } while (--l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) l = *n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u16 outreg, fifo_threshold, smo_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) outreg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) fifo_threshold = 1792;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dprintk("setting output mode for demod %p to %d\n", &state->demod, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case OUTMODE_MPEG2_PAR_GATED_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) outreg = (1 << 10); /* 0x0400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case OUTMODE_MPEG2_PAR_CONT_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) outreg = (1 << 10) | (1 << 6); /* 0x0440 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case OUTMODE_MPEG2_SERIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case OUTMODE_DIVERSITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (state->cfg.hostbus_diversity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) outreg = (1 << 10) | (4 << 6); /* 0x0500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) outreg = (1 << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case OUTMODE_MPEG2_FIFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) smo_mode |= (3 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) fifo_threshold = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) outreg = (1 << 10) | (5 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case OUTMODE_ANALOG_ADC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) outreg = (1 << 10) | (3 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case OUTMODE_HIGH_Z:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) outreg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dprintk("Unhandled output_mode passed to be set for demod %p\n", &state->demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (state->cfg.output_mpeg2_in_188_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) smo_mode |= (1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret |= dib7000p_write_word(state, 235, smo_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (state->version != SOC7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct dib7000p_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (state->div_force_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dprintk("diversity combination deactivated - forced by COFDM parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) onoff = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dib7000p_write_word(state, 207, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) state->div_state = (u8) onoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (onoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dib7000p_write_word(state, 204, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dib7000p_write_word(state, 205, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dib7000p_write_word(state, 204, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dib7000p_write_word(state, 205, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* by default everything is powered off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* now, depending on the requested mode, we power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* power up everything in the demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case DIB7000P_POWER_ALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) reg_774 = 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) reg_775 = 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) reg_776 = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) reg_899 = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (state->version == SOC7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) reg_1280 &= 0x001f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) reg_1280 &= 0x01ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case DIB7000P_POWER_ANALOG_ADC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* dem, cfg, iqc, sad, agc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* nud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) reg_776 &= ~((1 << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Dout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (state->version != SOC7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) reg_1280 &= ~((1 << 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) reg_1280 &= ~(1 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case DIB7000P_POWER_INTERFACE_ONLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* TODO power up either SDIO or I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (state->version == SOC7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) reg_1280 &= ~((1 << 7) | (1 << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* TODO following stuff is just converted from the dib7000-driver - check when is used what */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dib7000p_write_word(state, 774, reg_774);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dib7000p_write_word(state, 775, reg_775);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dib7000p_write_word(state, 776, reg_776);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dib7000p_write_word(state, 1280, reg_1280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (state->version != SOC7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dib7000p_write_word(state, 899, reg_899);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u16 reg_908 = 0, reg_909 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (state->version != SOC7090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) reg_908 = dib7000p_read_word(state, 908);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) reg_909 = dib7000p_read_word(state, 909);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) switch (no) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case DIBX000_SLOW_ADC_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (state->version == SOC7090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) reg = dib7000p_read_word(state, 1925);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dib7000p_write_word(state, 1925, reg | (1 << 4) | (1 << 2)); /* en_slowAdc = 1 & reset_sladc = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) reg = dib7000p_read_word(state, 1925); /* read access to make it works... strange ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dib7000p_write_word(state, 1925, reg & ~(1 << 4)); /* en_slowAdc = 1 & reset_sladc = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dib7000p_write_word(state, 72, reg | (1 << 14) | (3 << 12) | 524); /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; (Vin2 = Vcm) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) reg_909 |= (1 << 1) | (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dib7000p_write_word(state, 909, reg_909);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) reg_909 &= ~(1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case DIBX000_SLOW_ADC_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (state->version == SOC7090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) reg = dib7000p_read_word(state, 1925);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) reg_909 |= (1 << 1) | (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case DIBX000_ADC_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) reg_908 &= 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) reg_909 &= 0x0003;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case DIBX000_ADC_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) reg_908 |= (1 << 14) | (1 << 13) | (1 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case DIBX000_VBG_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) reg_908 &= ~(1 << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case DIBX000_VBG_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) reg_908 |= (1 << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) // dprintk( "908: %x, 909: %x\n", reg_908, reg_909);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) reg_908 |= (state->cfg.enable_current_mirror & 1) << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (state->version != SOC7090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dib7000p_write_word(state, 908, reg_908);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dib7000p_write_word(state, 909, reg_909);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u32 timf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) // store the current bandwidth for later use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) state->current_bandwidth = bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (state->timf == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dprintk("using default timf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) timf = state->cfg.bw->timf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dprintk("using updated timf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) timf = state->timf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) timf = timf * (bw / 50) / 160;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dib7000p_write_word(state, 24, (u16) ((timf) & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int dib7000p_sad_calib(struct dib7000p_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dib7000p_write_word(state, 73, (0 << 1) | (0 << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (state->version == SOC7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dib7000p_write_word(state, 74, 2048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dib7000p_write_word(state, 74, 776);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* do the calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dib7000p_write_word(state, 73, (1 << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dib7000p_write_word(state, 73, (0 << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int dib7000p_set_wbd_ref(struct dvb_frontend *demod, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct dib7000p_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (value > 4095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) value = 4095;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) state->wbd_ref = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int dib7000p_get_agc_values(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u16 *agc_global, u16 *agc1, u16 *agc2, u16 *wbd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (agc_global != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *agc_global = dib7000p_read_word(state, 394);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (agc1 != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) *agc1 = dib7000p_read_word(state, 392);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (agc2 != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) *agc2 = dib7000p_read_word(state, 393);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (wbd != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) *wbd = dib7000p_read_word(state, 397);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int dib7000p_set_agc1_min(struct dvb_frontend *fe, u16 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return dib7000p_write_word(state, 108, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static void dib7000p_reset_pll(struct dib7000p_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u16 clk_cfg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (state->version == SOC7090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* force PLL bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dib7000p_write_word(state, 900, clk_cfg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* P_pll_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dib7000p_write_word(state, 900, clk_cfg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dib7000p_write_word(state, 72, bw->sad_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static u32 dib7000p_get_internal_freq(struct dib7000p_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 internal = (u32) dib7000p_read_word(state, 18) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) internal |= (u32) dib7000p_read_word(state, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) internal /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u16 reg_1857, reg_1856 = dib7000p_read_word(state, 1856);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u8 loopdiv, prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 internal, xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* get back old values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) prediv = reg_1856 & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) loopdiv = (reg_1856 >> 6) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) reg_1856 &= 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) reg_1857 = dib7000p_read_word(state, 1857);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* write new system clk into P_sec_len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) internal = dib7000p_get_internal_freq(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) xtal = (internal / loopdiv) * prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dib7000p_write_word(state, 19, (u16) (internal & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dib7000p_write_word(state, 1857, reg_1857 | (1 << 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dprintk("Waiting for PLL to lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int dib7000p_reset_gpio(struct dib7000p_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* reset the GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dprintk("gpio dir: %x: val: %x, pwm_pos: %x\n", st->gpio_dir, st->gpio_val, st->cfg.gpio_pwm_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dib7000p_write_word(st, 1029, st->gpio_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dib7000p_write_word(st, 1030, st->gpio_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* TODO 1031 is P_gpio_od */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dib7000p_write_word(st, 1032, st->cfg.gpio_pwm_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dib7000p_write_word(st, 1037, st->cfg.pwm_freq_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) st->gpio_dir = dib7000p_read_word(st, 1029);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) st->gpio_dir &= ~(1 << num); /* reset the direction bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dib7000p_write_word(st, 1029, st->gpio_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) st->gpio_val = dib7000p_read_word(st, 1030);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) st->gpio_val &= ~(1 << num); /* reset the direction bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) st->gpio_val |= (val & 0x01) << num; /* set the new value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dib7000p_write_word(st, 1030, st->gpio_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int dib7000p_set_gpio(struct dvb_frontend *demod, u8 num, u8 dir, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct dib7000p_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return dib7000p_cfg_gpio(state, num, dir, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static u16 dib7000p_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) // auto search configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 3, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) (1<<3)|(1<<11)|(1<<12)|(1<<13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 0x0814, /* Equal Lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 12, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 0x001b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 0x7740,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 0x005b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 0x8d80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 0x01c9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 0xc380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 0x0090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 0xd4c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 1, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 0x6680,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* set ADC level to -16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 11, 79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) (1 << 13) - 825 - 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) (1 << 13) - 837 - 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) (1 << 13) - 811 - 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) (1 << 13) - 766 - 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) (1 << 13) - 737 - 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) (1 << 13) - 693 - 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) (1 << 13) - 648 - 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) (1 << 13) - 619 - 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) (1 << 13) - 575 - 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) (1 << 13) - 531 - 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) (1 << 13) - 501 - 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 1, 142,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 0x0410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* disable power smoothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 8, 145,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 1, 154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 1 << 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 1, 168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 0x0ccd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 1, 183,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 0x200f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 1, 212,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 0x169,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 5, 187,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 0x023d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 0x00a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 0x00a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 0x7ff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 0x3ccc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 1, 198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 1, 222,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 1, 235,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 0x0062,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static void dib7000p_reset_stats(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int dib7000p_demod_reset(struct dib7000p_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (state->version == SOC7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dibx000_reset_i2c_master(&state->i2c_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* restart all parts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dib7000p_write_word(state, 770, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dib7000p_write_word(state, 771, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dib7000p_write_word(state, 772, 0x001f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dib7000p_write_word(state, 770, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dib7000p_write_word(state, 771, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dib7000p_write_word(state, 772, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dib7000p_write_word(state, 1280, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (state->version != SOC7090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dib7000p_write_word(state, 898, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dib7000p_write_word(state, 898, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dib7000p_reset_pll(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (dib7000p_reset_gpio(state) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dprintk("GPIO reset was not successful.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (state->version == SOC7090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dib7000p_write_word(state, 899, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* impulse noise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dib7000p_write_word(state, 273, (0<<6) | 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dprintk("OUTPUT_MODE could not be reset.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dib7000p_sad_calib(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* unforce divstr regardless whether i2c enumeration was done or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dib7000p_set_bandwidth(state, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (state->version == SOC7090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dib7000p_write_word(state, 36, 0x0755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (state->cfg.tuner_is_baseband)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) dib7000p_write_word(state, 36, 0x0755);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dib7000p_write_word(state, 36, 0x1f55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dib7000p_write_tab(state, dib7000p_defaults);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (state->version != SOC7090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dib7000p_write_word(state, 901, 0x0006);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dib7000p_write_word(state, 902, (3 << 10) | (1 << 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dib7000p_write_word(state, 905, 0x2c8e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static void dib7000p_pll_clk_cfg(struct dib7000p_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u16 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) tmp = dib7000p_read_word(state, 903);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dib7000p_write_word(state, 903, (tmp | 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) tmp = dib7000p_read_word(state, 900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static void dib7000p_restart_agc(struct dib7000p_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) // P_restart_iqc & P_restart_agc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dib7000p_write_word(state, 770, (1 << 11) | (1 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dib7000p_write_word(state, 770, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static int dib7000p_update_lna(struct dib7000p_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) u16 dyn_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (state->cfg.update_lna) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dyn_gain = dib7000p_read_word(state, 394);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (state->cfg.update_lna(&state->demod, dyn_gain)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dib7000p_restart_agc(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct dibx000_agc_config *agc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (state->current_band == band && state->current_agc != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) state->current_band = band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) for (i = 0; i < state->cfg.agc_config_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (state->cfg.agc[i].band_caps & band) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) agc = &state->cfg.agc[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (agc == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dprintk("no valid AGC configuration found for band 0x%02x\n", band);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) state->current_agc = agc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dib7000p_write_word(state, 75, agc->setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dib7000p_write_word(state, 76, agc->inv_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dib7000p_write_word(state, 77, agc->time_stabiliz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) // Demod AGC loop configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* AGC continued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (state->wbd_ref != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | state->wbd_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | agc->wbd_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dib7000p_write_word(state, 107, agc->agc1_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dib7000p_write_word(state, 108, agc->agc1_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dib7000p_write_word(state, 109, agc->agc2_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dib7000p_write_word(state, 110, agc->agc2_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dib7000p_write_word(state, 112, agc->agc1_pt3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u32 internal = dib7000p_get_internal_freq(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) s32 unit_khz_dds_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 abs_offset_khz = abs(offset_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 dds = state->cfg.bw->ifreq & 0x1ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u8 invert = !!(state->cfg.bw->ifreq & (1 << 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (internal == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) pr_warn("DIB7000P: dib7000p_get_internal_freq returned 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* 2**26 / Fsampling is the unit 1KHz offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) unit_khz_dds_val = 67108864 / (internal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dprintk("setting a frequency offset of %dkHz internal freq = %d invert = %d\n", offset_khz, internal, invert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (offset_khz < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) unit_khz_dds_val *= -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* IF tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dds -= (abs_offset_khz * unit_khz_dds_val); /* /100 because of /100 on the unit_khz_dds_val line calc for better accuracy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dds += (abs_offset_khz * unit_khz_dds_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (abs_offset_khz <= (internal / 2)) { /* Max dds offset is the half of the demod freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dib7000p_write_word(state, 21, (u16) (((dds >> 16) & 0x1ff) | (0 << 10) | (invert << 9)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dib7000p_write_word(state, 22, (u16) (dds & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int dib7000p_agc_startup(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct dib7000p_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u8 *agc_state = &state->agc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u8 agc_split;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u32 upd_demod_gain_period = 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) s32 frequency_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) switch (state->agc_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (state->version == SOC7090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) reg = dib7000p_read_word(state, 0x79b) & 0xff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF); /* lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* enable adc i & q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) reg = dib7000p_read_word(state, 0x780);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dib7000p_set_adc_state(state, DIBX000_ADC_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dib7000p_pll_clk_cfg(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (demod->ops.tuner_ops.get_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u32 frequency_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) demod->ops.tuner_ops.get_frequency(demod, &frequency_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) frequency_offset = (s32)frequency_tuner / 1000 - ch->frequency / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (dib7000p_set_dds(state, frequency_offset) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ret = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) (*agc_state)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (state->cfg.agc_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) state->cfg.agc_control(&state->demod, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dib7000p_write_word(state, 78, 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (!state->current_agc->perform_agc_softsplit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* we are using the wbd - so slow AGC startup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* force 0 split on WBD and restart AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) (*agc_state)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ret = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* default AGC startup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) (*agc_state) = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* wait AGC rough lock time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dib7000p_restart_agc(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case 2: /* fast split search path after 5sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) (*agc_state)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case 3: /* split search ended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) agc_split = (u8) dib7000p_read_word(state, 396); /* store the split value for the next time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dib7000p_restart_agc(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dprintk("SPLIT %p: %u\n", demod, agc_split);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) (*agc_state)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ret = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) case 4: /* LNA startup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (dib7000p_update_lna(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ret = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) (*agc_state)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (state->cfg.agc_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) state->cfg.agc_control(&state->demod, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) (*agc_state)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static void dib7000p_update_timf(struct dib7000p_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) u32 timf = (dib7000p_read_word(state, 427) << 16) | dib7000p_read_word(state, 428);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) state->timf = timf * 160 / (state->current_bandwidth / 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) dib7000p_write_word(state, 23, (u16) (timf >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dib7000p_write_word(state, 24, (u16) (timf & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) dprintk("updated timf_frequency: %d (default: %d)\n", state->timf, state->cfg.bw->timf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) switch (op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) case DEMOD_TIMF_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) state->timf = timf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) case DEMOD_TIMF_UPDATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dib7000p_update_timf(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) case DEMOD_TIMF_GET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) dib7000p_set_bandwidth(state, state->current_bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return state->timf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static void dib7000p_set_channel(struct dib7000p_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct dtv_frontend_properties *ch, u8 seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) u16 value, est[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* nfft, guard, qam, alpha */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) switch (ch->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) case TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) value |= (0 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) case TRANSMISSION_MODE_4K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) value |= (2 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) case TRANSMISSION_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) value |= (1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) switch (ch->guard_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) case GUARD_INTERVAL_1_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) value |= (0 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) case GUARD_INTERVAL_1_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) value |= (1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) case GUARD_INTERVAL_1_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) value |= (3 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) case GUARD_INTERVAL_1_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) value |= (2 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) switch (ch->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) case QPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) value |= (0 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) value |= (1 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) value |= (2 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) switch (HIERARCHY_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) case HIERARCHY_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) value |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) case HIERARCHY_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) value |= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) case HIERARCHY_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) value |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) dib7000p_write_word(state, 0, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (1 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) value |= (1 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (ch->hierarchy == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) value |= (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (1 == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) value |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) value |= (2 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) value |= (3 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) value |= (5 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) value |= (7 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) value |= (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dib7000p_write_word(state, 208, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* offset loop parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dib7000p_write_word(state, 26, 0x6680);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dib7000p_write_word(state, 32, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) dib7000p_write_word(state, 29, 0x1273);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) dib7000p_write_word(state, 33, 0x0005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* P_dvsy_sync_wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) switch (ch->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) case TRANSMISSION_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) value = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) case TRANSMISSION_MODE_4K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) value = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) case TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) value = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) switch (ch->guard_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) case GUARD_INTERVAL_1_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) value *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) case GUARD_INTERVAL_1_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) value *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) case GUARD_INTERVAL_1_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) value *= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) case GUARD_INTERVAL_1_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) value *= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (state->cfg.diversity_delay == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) state->div_sync_wait = (value * 3) / 2 + 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* deactivate the possibility of diversity reception if extended interleaver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) state->div_force_off = !1 && ch->transmission_mode != TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) dib7000p_set_diversity_in(&state->demod, state->div_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* channel estimation fine configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) switch (ch->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) est[2] = 0x0333; /* P_adp_regul_ext 0.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) for (value = 0; value < 4; value++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) dib7000p_write_word(state, 187 + value, est[value]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static int dib7000p_autosearch_start(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct dib7000p_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct dtv_frontend_properties schan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) u32 value, factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) u32 internal = dib7000p_get_internal_freq(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) schan = *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) schan.modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) schan.guard_interval = GUARD_INTERVAL_1_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) schan.transmission_mode = TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) schan.code_rate_HP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) schan.code_rate_LP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) schan.hierarchy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) dib7000p_set_channel(state, &schan, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) factor = BANDWIDTH_TO_KHZ(ch->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (factor >= 5000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (state->version == SOC7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) factor = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) factor = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) factor = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) value = 30 * internal * factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) dib7000p_write_word(state, 7, (u16) (value & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) value = 100 * internal * factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) dib7000p_write_word(state, 9, (u16) (value & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) value = 500 * internal * factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) dib7000p_write_word(state, 11, (u16) (value & 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) value = dib7000p_read_word(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) dib7000p_write_word(state, 0, (u16) ((1 << 9) | value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) dib7000p_read_word(state, 1284);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) dib7000p_write_word(state, 0, (u16) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct dib7000p_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) u16 irq_pending = dib7000p_read_word(state, 1284);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (irq_pending & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (irq_pending & 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) 107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) 128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) 147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) 166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) 199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) 213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) 225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) 235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) 244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) 250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) 255, 255, 255, 255, 255, 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) u32 xtal = state->cfg.bw->xtal_hz / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) int coef_re[8], coef_im[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) int bw_khz = bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) u32 pha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dprintk("relative position of the Spur: %dk (RF: %dk, XTAL: %dk)\n", f_rel, rf_khz, xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (f_rel < -bw_khz / 2 || f_rel > bw_khz / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) bw_khz /= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) dib7000p_write_word(state, 142, 0x0610);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) for (k = 0; k < 8; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (pha == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) coef_re[k] = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) coef_im[k] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) } else if (pha < 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) coef_re[k] = sine[256 - (pha & 0xff)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) coef_im[k] = sine[pha & 0xff];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) } else if (pha == 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) coef_re[k] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) coef_im[k] = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) } else if (pha < 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) coef_re[k] = -sine[pha & 0xff];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) coef_im[k] = sine[256 - (pha & 0xff)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) } else if (pha == 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) coef_re[k] = -256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) coef_im[k] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) } else if (pha < 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) coef_re[k] = -sine[256 - (pha & 0xff)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) coef_im[k] = -sine[pha & 0xff];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) } else if (pha == 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) coef_re[k] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) coef_im[k] = -256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) coef_re[k] = sine[pha & 0xff];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) coef_im[k] = -sine[256 - (pha & 0xff)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) coef_re[k] *= notch[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) coef_re[k] += (1 << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (coef_re[k] >= (1 << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) coef_re[k] = (1 << 24) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) coef_re[k] /= (1 << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) coef_im[k] *= notch[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) coef_im[k] += (1 << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (coef_im[k] >= (1 << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) coef_im[k] = (1 << 24) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) coef_im[k] /= (1 << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) dprintk("PALF COEF: %d re: %d im: %d\n", k, coef_re[k], coef_im[k]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) dib7000p_write_word(state, 144, coef_im[k] & 0x3ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) dib7000p_write_word(state, 143, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static int dib7000p_tune(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct dib7000p_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) u16 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (ch != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) dib7000p_set_channel(state, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) // restart demod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) dib7000p_write_word(state, 770, 0x4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dib7000p_write_word(state, 770, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) msleep(45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (state->sfn_workaround_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dprintk("SFN workaround is active\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) tmp |= (1 << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) dib7000p_write_word(state, 166, 0x4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) dib7000p_write_word(state, 166, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dib7000p_write_word(state, 29, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) // never achieved a lock with that bandwidth so far - wait for osc-freq to update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (state->timf == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* offset loop parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) tmp = (6 << 8) | 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) switch (ch->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) case TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) tmp |= (2 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) case TRANSMISSION_MODE_4K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) tmp |= (3 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) case TRANSMISSION_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) tmp |= (4 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) tmp = (0 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) switch (ch->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) case TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) tmp |= 0x6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) case TRANSMISSION_MODE_4K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) tmp |= 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) case TRANSMISSION_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) tmp |= 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dib7000p_write_word(state, 32, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) tmp = (0 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) switch (ch->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) case TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) tmp |= 0x6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) case TRANSMISSION_MODE_4K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) tmp |= 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) case TRANSMISSION_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) tmp |= 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) dib7000p_write_word(state, 33, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) tmp = dib7000p_read_word(state, 509);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (!((tmp >> 6) & 0x1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /* restart the fec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) tmp = dib7000p_read_word(state, 771);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) dib7000p_write_word(state, 771, tmp | (1 << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) dib7000p_write_word(state, 771, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) msleep(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) tmp = dib7000p_read_word(state, 509);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) // we achieved a lock - it's time to update the osc freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if ((tmp >> 6) & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) dib7000p_update_timf(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /* P_timf_alpha += 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) tmp = dib7000p_read_word(state, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dib7000p_write_word(state, 26, (tmp & ~(0xf << 12)) | ((((tmp >> 12) & 0xf) + 5) << 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (state->cfg.spur_protect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) dib7000p_reset_stats(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static int dib7000p_wakeup(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct dib7000p_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (state->version == SOC7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dib7000p_sad_calib(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static int dib7000p_sleep(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct dib7000p_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (state->version == SOC7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static int dib7000p_identify(struct dib7000p_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dprintk("checking demod on I2C address: %d (%x)\n", st->i2c_addr, st->i2c_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if ((value = dib7000p_read_word(st, 768)) != 0x01b3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dprintk("wrong Vendor ID (read=0x%x)\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if ((value = dib7000p_read_word(st, 769)) != 0x4000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) dprintk("wrong Device ID (%x)\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static int dib7000p_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) struct dtv_frontend_properties *fep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) u16 tps = dib7000p_read_word(state, 463);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) fep->inversion = INVERSION_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) switch ((tps >> 8) & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) fep->transmission_mode = TRANSMISSION_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) fep->transmission_mode = TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) switch (tps & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) fep->guard_interval = GUARD_INTERVAL_1_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) fep->guard_interval = GUARD_INTERVAL_1_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) fep->guard_interval = GUARD_INTERVAL_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) fep->guard_interval = GUARD_INTERVAL_1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) switch ((tps >> 14) & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) fep->modulation = QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) fep->modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) fep->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) fep->hierarchy = HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) switch ((tps >> 5) & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) fep->code_rate_HP = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) fep->code_rate_HP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) fep->code_rate_HP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) fep->code_rate_HP = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) fep->code_rate_HP = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) switch ((tps >> 2) & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) fep->code_rate_LP = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) fep->code_rate_LP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) fep->code_rate_LP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) fep->code_rate_LP = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) fep->code_rate_LP = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* native interleaver: (dib7000p_read_word(state, 464) >> 5) & 0x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static int dib7000p_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) int time, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (state->version == SOC7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) dib7090_set_diversity_in(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* maybe the parameter has been changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) state->sfn_workaround_active = buggy_sfn_workaround;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (fe->ops.tuner_ops.set_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* start up the AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) state->agc_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) time = dib7000p_agc_startup(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (time != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) msleep(time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) } while (time != -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) fep->guard_interval == GUARD_INTERVAL_AUTO || fep->modulation == QAM_AUTO || fep->code_rate_HP == FEC_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) int i = 800, found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) dib7000p_autosearch_start(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) found = dib7000p_autosearch_is_irq(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) } while (found == 0 && i--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) dprintk("autosearch returns: %d\n", found);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (found == 0 || found == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) dib7000p_get_frontend(fe, fep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ret = dib7000p_tune(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /* make this a config parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) if (state->version == SOC7090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dib7090_set_output_mode(fe, state->cfg.output_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (state->cfg.enMpegOutput == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) dib7090_setDibTxMux(state, MPEG_ON_DIBTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) dib7000p_set_output_mode(state, state->cfg.output_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static int dib7000p_get_stats(struct dvb_frontend *fe, enum fe_status stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) static int dib7000p_read_status(struct dvb_frontend *fe, enum fe_status *stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) u16 lock = dib7000p_read_word(state, 509);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) *stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (lock & 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) *stat |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (lock & 0x3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) *stat |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (lock & 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) *stat |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (lock & 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) *stat |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if ((lock & 0x0038) == 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) *stat |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) dib7000p_get_stats(fe, *stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) static int dib7000p_read_ber(struct dvb_frontend *fe, u32 * ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) *ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) *unc = dib7000p_read_word(state, 506);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) u16 val = dib7000p_read_word(state, 394);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) *strength = 65535 - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static u32 dib7000p_get_snr(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) s32 signal_mant, signal_exp, noise_mant, noise_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) u32 result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) val = dib7000p_read_word(state, 479);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) noise_mant = (val >> 4) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) noise_exp = ((val & 0xf) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) val = dib7000p_read_word(state, 480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) noise_exp += ((val >> 14) & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if ((noise_exp & 0x20) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) noise_exp -= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) signal_mant = (val >> 6) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) signal_exp = (val & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if ((signal_exp & 0x20) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) signal_exp -= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (signal_mant != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) result = intlog10(2) * 10 * signal_exp - 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (noise_mant != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) result -= intlog10(2) * 10 * noise_exp - 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) static int dib7000p_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) u32 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) result = dib7000p_get_snr(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) *snr = result / ((1 << 24) / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) static void dib7000p_reset_stats(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) struct dib7000p_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) struct dtv_frontend_properties *c = &demod->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) u32 ucb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) memset(&c->strength, 0, sizeof(c->strength));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) memset(&c->cnr, 0, sizeof(c->cnr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) memset(&c->block_error, 0, sizeof(c->block_error));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) c->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) c->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) c->block_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) c->block_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) c->post_bit_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) c->post_bit_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) c->strength.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) c->strength.stat[0].uvalue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) dib7000p_read_unc_blocks(demod, &ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) state->old_ucb = ucb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) state->ber_jiffies_stats = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) state->per_jiffies_stats = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct linear_segments {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) unsigned x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) signed y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) * Table to estimate signal strength in dBm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) * This table should be empirically determinated by measuring the signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) * strength generated by a RF generator directly connected into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) * a device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) * This table was determinated by measuring the signal strength generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) * by a DTA-2111 RF generator directly connected into a dib7000p device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) * (a Hauppauge Nova-TD stick), using a good quality 3 meters length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) * RC6 cable and good RC6 connectors, connected directly to antenna 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) * As the minimum output power of DTA-2111 is -31dBm, a 16 dBm attenuator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) * were used, for the lower power values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) * The real value can actually be on other devices, or even at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) * second antena input, depending on several factors, like if LNA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) * is enabled or not, if diversity is enabled, type of connectors, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) * Yet, it is better to use this measure in dB than a random non-linear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * percentage value, especially for antenna adjustments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) * On my tests, the precision of the measure using this table is about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) * 0.5 dB, with sounds reasonable enough to adjust antennas.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) #define DB_OFFSET 131000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static struct linear_segments strength_to_db_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) { 63630, DB_OFFSET - 20500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) { 62273, DB_OFFSET - 21000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) { 60162, DB_OFFSET - 22000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) { 58730, DB_OFFSET - 23000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) { 58294, DB_OFFSET - 24000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) { 57778, DB_OFFSET - 25000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) { 57320, DB_OFFSET - 26000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) { 56779, DB_OFFSET - 27000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) { 56293, DB_OFFSET - 28000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) { 55724, DB_OFFSET - 29000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) { 55145, DB_OFFSET - 30000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) { 54680, DB_OFFSET - 31000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) { 54293, DB_OFFSET - 32000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) { 53813, DB_OFFSET - 33000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) { 53427, DB_OFFSET - 34000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) { 52981, DB_OFFSET - 35000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) { 52636, DB_OFFSET - 36000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) { 52014, DB_OFFSET - 37000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) { 51674, DB_OFFSET - 38000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) { 50692, DB_OFFSET - 39000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) { 49824, DB_OFFSET - 40000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) { 49052, DB_OFFSET - 41000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) { 48436, DB_OFFSET - 42000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) { 47836, DB_OFFSET - 43000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) { 47368, DB_OFFSET - 44000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) { 46468, DB_OFFSET - 45000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) { 45597, DB_OFFSET - 46000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) { 44586, DB_OFFSET - 47000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) { 43667, DB_OFFSET - 48000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) { 42673, DB_OFFSET - 49000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) { 41816, DB_OFFSET - 50000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) { 40876, DB_OFFSET - 51000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) { 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static u32 interpolate_value(u32 value, struct linear_segments *segments,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) unsigned len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) u64 tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) u32 dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) s32 dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) if (value >= segments[0].x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) return segments[0].y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (value < segments[len-1].x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) return segments[len-1].y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) for (i = 1; i < len - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) /* If value is identical, no need to interpolate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (value == segments[i].x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return segments[i].y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (value > segments[i].x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /* Linear interpolation between the two (x,y) points */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) dy = segments[i - 1].y - segments[i].y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) dx = segments[i - 1].x - segments[i].x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) tmp64 = value - segments[i].x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) tmp64 *= dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) do_div(tmp64, dx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) ret = segments[i].y + tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /* FIXME: may require changes - this one was borrowed from dib8000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static u32 dib7000p_get_time_us(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) struct dtv_frontend_properties *c = &demod->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) u64 time_us, tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) u32 tmp, denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) int guard, rate_num, rate_denum = 1, bits_per_symbol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) int interleaving = 0, fft_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) switch (c->guard_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) case GUARD_INTERVAL_1_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) guard = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) case GUARD_INTERVAL_1_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) guard = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) case GUARD_INTERVAL_1_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) guard = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) case GUARD_INTERVAL_1_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) guard = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) switch (c->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) case TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) fft_div = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) case TRANSMISSION_MODE_4K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) fft_div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) case TRANSMISSION_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) fft_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) switch (c->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) case DQPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) case QPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) bits_per_symbol = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) bits_per_symbol = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) bits_per_symbol = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) switch ((c->hierarchy == 0 || 1 == 1) ? c->code_rate_HP : c->code_rate_LP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) rate_num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) rate_denum = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) rate_num = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) rate_denum = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) rate_num = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) rate_denum = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) rate_num = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) rate_denum = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) rate_num = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) rate_denum = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) denom = bits_per_symbol * rate_num * fft_div * 384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) * FIXME: check if the math makes sense. If so, fill the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) * interleaving var.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /* If calculus gets wrong, wait for 1s for the next stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (!denom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) /* Estimate the period for the total bit rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) time_us = rate_denum * (1008 * 1562500L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) tmp64 = time_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) do_div(tmp64, guard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) time_us = time_us + tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) time_us += denom / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) do_div(time_us, denom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) tmp = 1008 * 96 * interleaving;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) time_us += tmp + tmp / guard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) return time_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static int dib7000p_get_stats(struct dvb_frontend *demod, enum fe_status stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) struct dib7000p_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) struct dtv_frontend_properties *c = &demod->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) int show_per_stats = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) u32 time_us = 0, val, snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) u64 blocks, ucb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) s32 db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) u16 strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /* Get Signal strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) dib7000p_read_signal_strength(demod, &strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) val = strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) db = interpolate_value(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) strength_to_db_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) ARRAY_SIZE(strength_to_db_table)) - DB_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) c->strength.stat[0].svalue = db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) /* UCB/BER/CNR measures require lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (!(stat & FE_HAS_LOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) c->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) c->block_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) c->block_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) c->post_bit_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) c->post_bit_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /* Check if time for stats was elapsed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) if (time_after(jiffies, state->per_jiffies_stats)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) /* Get SNR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) snr = dib7000p_get_snr(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) snr = (1000L * snr) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) c->cnr.stat[0].svalue = snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) /* Get UCB measures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) dib7000p_read_unc_blocks(demod, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) ucb = val - state->old_ucb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) if (val < state->old_ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) ucb += 0x100000000LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) c->block_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) c->block_error.stat[0].uvalue = ucb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) /* Estimate the number of packets based on bitrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) if (!time_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) time_us = dib7000p_get_time_us(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (time_us) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) blocks = 1250000ULL * 1000000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) do_div(blocks, time_us * 8 * 204);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) c->block_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) c->block_count.stat[0].uvalue += blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) show_per_stats = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) /* Get post-BER measures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if (time_after(jiffies, state->ber_jiffies_stats)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) time_us = dib7000p_get_time_us(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) dprintk("Next all layers stats available in %u us.\n", time_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) dib7000p_read_ber(demod, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) c->post_bit_error.stat[0].uvalue += val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) c->post_bit_count.stat[0].uvalue += 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) /* Get PER measures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) if (show_per_stats) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) dib7000p_read_unc_blocks(demod, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) c->block_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) c->block_error.stat[0].uvalue += val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) time_us = dib7000p_get_time_us(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (time_us) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) blocks = 1250000ULL * 1000000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) do_div(blocks, time_us * 8 * 204);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) c->block_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) c->block_count.stat[0].uvalue += blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) static int dib7000p_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) tune->min_delay_ms = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) static void dib7000p_release(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) struct dib7000p_state *st = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) dibx000_exit_i2c_master(&st->i2c_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) i2c_del_adapter(&st->dib7090_tuner_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) kfree(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) static int dib7000pc_detection(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) u8 *tx, *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) {.addr = 18 >> 1, .flags = 0, .len = 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) {.addr = 18 >> 1, .flags = I2C_M_RD, .len = 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) tx = kzalloc(2, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (!tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) rx = kzalloc(2, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) if (!rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) goto rx_memory_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) msg[0].buf = tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) msg[1].buf = rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) tx[0] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) tx[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (i2c_transfer(i2c_adap, msg, 2) == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) if (rx[0] == 0x01 && rx[1] == 0xb3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) dprintk("-D- DiB7000PC detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) msg[0].addr = msg[1].addr = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) if (i2c_transfer(i2c_adap, msg, 2) == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (rx[0] == 0x01 && rx[1] == 0xb3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) dprintk("-D- DiB7000PC detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) dprintk("-D- DiB7000PC not detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) kfree(rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) rx_memory_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) kfree(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) static struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) struct dib7000p_state *st = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) static int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) u16 val = dib7000p_read_word(state, 235) & 0xffef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) val |= (onoff & 0x1) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) dprintk("PID filter enabled %d\n", onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) return dib7000p_write_word(state, 235, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) static int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) dprintk("PID filter: index %x, PID %d, OnOff %d\n", id, pid, onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) static int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) struct dib7000p_state *dpst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) int k = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) u8 new_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) dpst = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) if (!dpst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) dpst->i2c_adap = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) mutex_init(&dpst->i2c_buffer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) for (k = no_of_demods - 1; k >= 0; k--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) dpst->cfg = cfg[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) /* designated i2c address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) if (cfg[k].default_i2c_addr != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) new_addr = cfg[k].default_i2c_addr + (k << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) new_addr = (0x40 + k) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) dpst->i2c_addr = new_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if (dib7000p_identify(dpst) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) dpst->i2c_addr = default_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) if (dib7000p_identify(dpst) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) dprintk("DiB7000P #%d: not identified\n", k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) kfree(dpst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) /* start diversity to pull_down div_str - just for i2c-enumeration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) dib7000p_set_output_mode(dpst, OUTMODE_DIVERSITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) /* set new i2c address and force divstart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) dib7000p_write_word(dpst, 1285, (new_addr << 2) | 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) for (k = 0; k < no_of_demods; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) dpst->cfg = cfg[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) if (cfg[k].default_i2c_addr != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) dpst->i2c_addr = (0x40 + k) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) // unforce divstr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) /* deactivate div - it was just for i2c-enumeration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) dib7000p_set_output_mode(dpst, OUTMODE_HIGH_Z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) kfree(dpst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) static const s32 lut_1000ln_mant[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) 6908, 6956, 7003, 7047, 7090, 7131, 7170, 7208, 7244, 7279, 7313, 7346, 7377, 7408, 7438, 7467, 7495, 7523, 7549, 7575, 7600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) static s32 dib7000p_get_adc_power(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) u32 tmp_val = 0, exp = 0, mant = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) s32 pow_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) u16 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) u8 ix = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) buf[0] = dib7000p_read_word(state, 0x184);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) buf[1] = dib7000p_read_word(state, 0x185);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) pow_i = (buf[0] << 16) | buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) dprintk("raw pow_i = %d\n", pow_i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) tmp_val = pow_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) while (tmp_val >>= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) exp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) mant = (pow_i * 1000 / (1 << exp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) dprintk(" mant = %d exp = %d\n", mant / 1000, exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) ix = (u8) ((mant - 1000) / 100); /* index of the LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) dprintk(" ix = %d\n", ix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) pow_i = (lut_1000ln_mant[ix] + 693 * (exp - 20) - 6908);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) pow_i = (pow_i << 8) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) dprintk(" pow_i = %d\n", pow_i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) return pow_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) static int map_addr_to_serpar_number(struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) if ((msg->buf[0] <= 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) msg->buf[0] -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) else if (msg->buf[0] == 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) msg->buf[0] = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) else if (msg->buf[0] == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) msg->buf[0] = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) else if (msg->buf[0] == 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) msg->buf[0] = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) msg->buf[0] -= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) else if (msg->buf[0] == 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) msg->buf[0] = 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) static int w7090p_tuner_write_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) u8 n_overflow = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) u16 i = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) u16 serpar_num = msg[0].buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) while (n_overflow == 1 && i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) i--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) dprintk("Tuner ITF: write busy (overflow)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) dib7000p_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) dib7000p_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) static int w7090p_tuner_read_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) u8 n_overflow = 1, n_empty = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) u16 i = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) u16 serpar_num = msg[0].buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) u16 read_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) while (n_overflow == 1 && i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) i--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) dprintk("TunerITF: read busy (overflow)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) dib7000p_write_word(state, 1985, (0 << 6) | (serpar_num & 0x3f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) i = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) while (n_empty == 1 && i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) n_empty = dib7000p_read_word(state, 1984) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) i--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) dprintk("TunerITF: read busy (empty)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) read_word = dib7000p_read_word(state, 1987);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) msg[1].buf[0] = (read_word >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) msg[1].buf[1] = (read_word) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) static int w7090p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) if (map_addr_to_serpar_number(&msg[0]) == 0) { /* else = Tuner regs to ignore : DIG_CFG, CTRL_RF_LT, PLL_CFG, PWM1_REG, ADCCLK, DIG_CFG_3; SLEEP_EN... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) if (num == 1) { /* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) return w7090p_tuner_write_serpar(i2c_adap, msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) } else { /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) return w7090p_tuner_read_serpar(i2c_adap, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) struct i2c_msg msg[], int num, u16 apb_address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) u16 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) if (num == 1) { /* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) dib7000p_write_word(state, apb_address, ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) word = dib7000p_read_word(state, apb_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) msg[1].buf[0] = (word >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) msg[1].buf[1] = (word) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) static int dib7090_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) u16 apb_address = 0, word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) switch (msg[0].buf[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) case 0x12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) apb_address = 1920;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) case 0x14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) apb_address = 1921;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) case 0x24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) apb_address = 1922;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) case 0x1a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) apb_address = 1923;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) case 0x22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) apb_address = 1924;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) case 0x33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) apb_address = 1926;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) case 0x34:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) apb_address = 1927;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) case 0x35:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) apb_address = 1928;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) case 0x36:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) apb_address = 1929;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) case 0x37:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) apb_address = 1930;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) case 0x38:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) apb_address = 1931;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) case 0x39:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) apb_address = 1932;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) case 0x2a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) apb_address = 1935;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) case 0x2b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) apb_address = 1936;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) case 0x2c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) apb_address = 1937;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) case 0x2d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) apb_address = 1938;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) case 0x2e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) apb_address = 1939;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) case 0x2f:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) apb_address = 1940;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) case 0x30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) apb_address = 1941;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) case 0x31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) apb_address = 1942;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) case 0x32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) apb_address = 1943;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) case 0x3e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) apb_address = 1944;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) case 0x3f:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) apb_address = 1945;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) case 0x40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) apb_address = 1948;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) case 0x25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) apb_address = 914;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) case 0x26:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) apb_address = 915;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) case 0x27:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) apb_address = 917;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) case 0x28:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) apb_address = 916;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) case 0x1d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) i = ((dib7000p_read_word(state, 72) >> 12) & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) word = dib7000p_read_word(state, 384 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) msg[1].buf[0] = (word >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) msg[1].buf[1] = (word) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) case 0x1f:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) if (num == 1) { /* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) word = (u16) ((msg[0].buf[1] << 8) | msg[0].buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) word &= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) dib7000p_write_word(state, 72, word); /* Set the proper input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) if (apb_address != 0) /* R/W access via APB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) return dib7090p_rw_on_apb(i2c_adap, msg, num, apb_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) else /* R/W access via SERPAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) return w7090p_tuner_rw_serpar(i2c_adap, msg, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) static u32 dib7000p_i2c_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) return I2C_FUNC_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) static const struct i2c_algorithm dib7090_tuner_xfer_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .master_xfer = dib7090_tuner_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .functionality = dib7000p_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) static struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) struct dib7000p_state *st = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) return &st->dib7090_tuner_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) static int dib7090_host_bus_drive(struct dib7000p_state *state, u8 drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) /* drive host bus 2, 3, 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) reg |= (drive << 12) | (drive << 6) | drive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) dib7000p_write_word(state, 1798, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) /* drive host bus 5,6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) reg |= (drive << 8) | (drive << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) dib7000p_write_word(state, 1799, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) /* drive host bus 7, 8, 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) reg |= (drive << 12) | (drive << 6) | drive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) dib7000p_write_word(state, 1800, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) /* drive host bus 10, 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) reg |= (drive << 8) | (drive << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) dib7000p_write_word(state, 1801, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) /* drive host bus 12, 13, 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) reg |= (drive << 12) | (drive << 6) | drive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) dib7000p_write_word(state, 1802, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) static u32 dib7090_calcSyncFreq(u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 syncSize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) u32 quantif = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) u32 nom = (insertExtSynchro * P_Kin + syncSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) u32 denom = P_Kout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) u32 syncFreq = ((nom << quantif) / denom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) if ((syncFreq & ((1 << quantif) - 1)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) syncFreq = (syncFreq >> quantif) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) syncFreq = (syncFreq >> quantif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) if (syncFreq != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) syncFreq = syncFreq - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) return syncFreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) dprintk("Configure DibStream Tx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) dib7000p_write_word(state, 1615, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) dib7000p_write_word(state, 1603, P_Kin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) dib7000p_write_word(state, 1605, P_Kout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) dib7000p_write_word(state, 1606, insertExtSynchro);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) dib7000p_write_word(state, 1608, synchroMode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) dib7000p_write_word(state, 1609, (syncWord >> 16) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) dib7000p_write_word(state, 1610, syncWord & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) dib7000p_write_word(state, 1612, syncSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) dib7000p_write_word(state, 1615, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 synchroMode, u32 insertExtSynchro, u32 syncWord, u32 syncSize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) u32 dataOutRate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) u32 syncFreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) dprintk("Configure DibStream Rx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) if ((P_Kin != 0) && (P_Kout != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) syncFreq = dib7090_calcSyncFreq(P_Kin, P_Kout, insertExtSynchro, syncSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) dib7000p_write_word(state, 1542, syncFreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) dib7000p_write_word(state, 1554, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) dib7000p_write_word(state, 1536, P_Kin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) dib7000p_write_word(state, 1537, P_Kout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) dib7000p_write_word(state, 1539, synchroMode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) dib7000p_write_word(state, 1540, (syncWord >> 16) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) dib7000p_write_word(state, 1541, syncWord & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) dib7000p_write_word(state, 1543, syncSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) dib7000p_write_word(state, 1544, dataOutRate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) dib7000p_write_word(state, 1554, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) static void dib7090_enMpegMux(struct dib7000p_state *state, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) u16 reg_1287 = dib7000p_read_word(state, 1287);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) switch (onoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) reg_1287 &= ~(1<<7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) reg_1287 |= (1<<7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) dib7000p_write_word(state, 1287, reg_1287);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) static void dib7090_configMpegMux(struct dib7000p_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) dprintk("Enable Mpeg mux\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) dib7090_enMpegMux(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) /* If the input mode is MPEG do not divide the serial clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) enSerialClkDiv2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) dib7000p_write_word(state, 1287, ((pulseWidth & 0x1f) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) | ((enSerialMode & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) | (enSerialClkDiv2 & 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) dib7090_enMpegMux(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) case MPEG_ON_DIBTX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) dprintk("SET MPEG ON DIBSTREAM TX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) reg_1288 |= (1<<9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) case DIV_ON_DIBTX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) dprintk("SET DIV_OUT ON DIBSTREAM TX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) reg_1288 |= (1<<8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) case ADC_ON_DIBTX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) dprintk("SET ADC_OUT ON DIBSTREAM TX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) reg_1288 |= (1<<7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) dib7000p_write_word(state, 1288, reg_1288);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) case DEMOUT_ON_HOSTBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) dprintk("SET DEM OUT OLD INTERF ON HOST BUS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) dib7090_enMpegMux(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) reg_1288 |= (1<<6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) case DIBTX_ON_HOSTBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) dprintk("SET DIBSTREAM TX ON HOST BUS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) dib7090_enMpegMux(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) reg_1288 |= (1<<5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) case MPEG_ON_HOSTBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) dprintk("SET MPEG MUX ON HOST BUS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) reg_1288 |= (1<<4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) dib7000p_write_word(state, 1288, reg_1288);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) u16 reg_1287;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) switch (onoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) case 0: /* only use the internal way - not the diversity input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) dprintk("%s mode OFF : by default Enable Mpeg INPUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) /* Do not divide the serial clock of MPEG MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) /* in SERIAL MODE in case input mode MPEG is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) reg_1287 = dib7000p_read_word(state, 1287);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) /* enSerialClkDiv2 == 1 ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) if ((reg_1287 & 0x1) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) /* force enSerialClkDiv2 = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) reg_1287 &= ~0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) dib7000p_write_word(state, 1287, reg_1287);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) state->input_mode_mpeg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) case 1: /* both ways */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) case 2: /* only the diversity input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) dprintk("%s ON : Enable diversity INPUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) state->input_mode_mpeg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) dib7000p_set_diversity_in(&state->demod, onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) u16 outreg, smo_mode, fifo_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) u8 prefer_mpeg_mux_use = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) dib7090_host_bus_drive(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) fifo_threshold = 1792;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) case OUTMODE_HIGH_Z:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) outreg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) case OUTMODE_MPEG2_SERIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) if (prefer_mpeg_mux_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) dprintk("setting output mode TS_SERIAL using Mpeg Mux\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) dib7090_configMpegMux(state, 3, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) } else {/* Use Smooth block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) dprintk("setting output mode TS_SERIAL using Smooth bloc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) outreg |= (2<<6) | (0 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) case OUTMODE_MPEG2_PAR_GATED_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) if (prefer_mpeg_mux_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) dprintk("setting output mode TS_PARALLEL_GATED using Mpeg Mux\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) dib7090_configMpegMux(state, 2, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) } else { /* Use Smooth block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) dprintk("setting output mode TS_PARALLEL_GATED using Smooth block\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) outreg |= (0<<6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) dprintk("setting output mode TS_PARALLEL_CONT using Smooth block\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) outreg |= (1<<6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) case OUTMODE_MPEG2_FIFO: /* Using Smooth block because not supported by new Mpeg Mux bloc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) dprintk("setting output mode TS_FIFO using Smooth block\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) outreg |= (5<<6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) smo_mode |= (3 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) fifo_threshold = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) case OUTMODE_DIVERSITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) dprintk("setting output mode MODE_DIVERSITY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) dib7090_setDibTxMux(state, DIV_ON_DIBTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) case OUTMODE_ANALOG_ADC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) dprintk("setting output mode MODE_ANALOG_ADC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) dib7090_setDibTxMux(state, ADC_ON_DIBTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) if (mode != OUTMODE_HIGH_Z)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) outreg |= (1 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) if (state->cfg.output_mpeg2_in_188_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) smo_mode |= (1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) ret |= dib7000p_write_word(state, 235, smo_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) ret |= dib7000p_write_word(state, 1286, outreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) static int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) u16 en_cur_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) dprintk("sleep dib7090: %d\n", onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) en_cur_state = dib7000p_read_word(state, 1922);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) if (en_cur_state > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) state->tuner_enable = en_cur_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) if (onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) en_cur_state &= 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) if (state->tuner_enable != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) en_cur_state = state->tuner_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) dib7000p_write_word(state, 1922, en_cur_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) static int dib7090_get_adc_power(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) return dib7000p_get_adc_power(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) static int dib7090_slave_reset(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) struct dib7000p_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) reg = dib7000p_read_word(state, 1794);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) dib7000p_write_word(state, 1794, reg | (4 << 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) dib7000p_write_word(state, 1032, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) static const struct dvb_frontend_ops dib7000p_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) static struct dvb_frontend *dib7000p_init(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) struct dvb_frontend *demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) struct dib7000p_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) st = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) if (st == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) memcpy(&st->cfg, cfg, sizeof(struct dib7000p_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) st->i2c_adap = i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) st->i2c_addr = i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) st->gpio_val = cfg->gpio_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) st->gpio_dir = cfg->gpio_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) /* Ensure the output mode remains at the previous default if it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) * not specifically set by the caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) st->cfg.output_mode = OUTMODE_MPEG2_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) demod = &st->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) demod->demodulator_priv = st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) mutex_init(&st->i2c_buffer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) if (dib7000p_identify(st) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) st->version = dib7000p_read_word(st, 897);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) /* FIXME: make sure the dev.parent field is initialized, or else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) request_firmware() will hit an OOPS (this should be moved somewhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) more common) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) st->i2c_master.gated_tuner_i2c_adap.dev.parent = i2c_adap->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) /* init 7090 tuner adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) strscpy(st->dib7090_tuner_adap.name, "DiB7090 tuner interface",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) sizeof(st->dib7090_tuner_adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) st->dib7090_tuner_adap.algo = &dib7090_tuner_xfer_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) st->dib7090_tuner_adap.algo_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) st->dib7090_tuner_adap.dev.parent = st->i2c_adap->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) i2c_set_adapdata(&st->dib7090_tuner_adap, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) i2c_add_adapter(&st->dib7090_tuner_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) dib7000p_demod_reset(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) dib7000p_reset_stats(demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) if (st->version == SOC7090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) dib7090_set_output_mode(demod, st->cfg.output_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) dib7090_set_diversity_in(demod, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) return demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) kfree(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) void *dib7000p_attach(struct dib7000p_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) if (!ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) ops->slave_reset = dib7090_slave_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) ops->get_adc_power = dib7090_get_adc_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) ops->dib7000pc_detection = dib7000pc_detection;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) ops->get_i2c_tuner = dib7090_get_i2c_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) ops->tuner_sleep = dib7090_tuner_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) ops->init = dib7000p_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) ops->set_agc1_min = dib7000p_set_agc1_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) ops->set_gpio = dib7000p_set_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) ops->i2c_enumeration = dib7000p_i2c_enumeration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) ops->pid_filter = dib7000p_pid_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) ops->pid_filter_ctrl = dib7000p_pid_filter_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) ops->get_i2c_master = dib7000p_get_i2c_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) ops->update_pll = dib7000p_update_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) ops->ctrl_timf = dib7000p_ctrl_timf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) ops->get_agc_values = dib7000p_get_agc_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) ops->set_wbd_ref = dib7000p_set_wbd_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) return ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) EXPORT_SYMBOL(dib7000p_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) static const struct dvb_frontend_ops dib7000p_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) .delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) .name = "DiBcom 7000PC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) .frequency_min_hz = 44250 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .frequency_max_hz = 867250 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) .frequency_stepsize_hz = 62500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) .caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .release = dib7000p_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) .init = dib7000p_wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) .sleep = dib7000p_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) .set_frontend = dib7000p_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .get_tune_settings = dib7000p_fe_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .get_frontend = dib7000p_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) .read_status = dib7000p_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) .read_ber = dib7000p_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) .read_signal_strength = dib7000p_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .read_snr = dib7000p_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) .read_ucblocks = dib7000p_read_unc_blocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) MODULE_AUTHOR("Olivier Grenie <olivie.grenie@parrot.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) MODULE_AUTHOR("Patrick Boettcher <patrick.boettcher@posteo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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