^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for DiBcom DiB3000MC/P-demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004-7 DiBcom (http://www.dibcom.fr/)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@posteo.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This code is partially based on the previous dib3000mc.c .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "dib3000mc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int buggy_sfn_workaround;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) module_param(buggy_sfn_workaround, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define dprintk(fmt, arg...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) printk(KERN_DEBUG pr_fmt("%s: " fmt), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __func__, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct dib3000mc_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct dvb_frontend demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct dib3000mc_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct i2c_adapter *i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct dibx000_i2c_master i2c_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 timf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 current_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u16 dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 sfn_workaround_active :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static u16 dib3000mc_read_word(struct dib3000mc_state *state, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { .addr = state->i2c_addr >> 1, .flags = 0, .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u16 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) b = kmalloc(4, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (!b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) b[0] = (reg >> 8) | 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) b[1] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) b[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) b[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) msg[0].buf = b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) msg[1].buf = b + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dprintk("i2c read error on %d\n",reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) word = (b[2] << 8) | b[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) kfree(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .addr = state->i2c_addr >> 1, .flags = 0, .len = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) b = kmalloc(4, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (!b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) b[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) b[1] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) b[2] = val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) b[3] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) msg.buf = b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) rc = i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) kfree(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int dib3000mc_identify(struct dib3000mc_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if ((value = dib3000mc_read_word(state, 1025)) != 0x01b3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dprintk("-E- DiB3000MC/P: wrong Vendor ID (read=0x%x)\n",value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) value = dib3000mc_read_word(state, 1026);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (value != 0x3001 && value != 0x3002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dprintk("-E- DiB3000MC/P: wrong Device ID (%x)\n",value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) state->dev_id = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dprintk("-I- found DiB3000MC/P: %x\n",state->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u32 bw, u8 update_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 timf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (state->timf == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) timf = 1384402; // default value for 8MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (update_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) msleep(200); // first time we do an update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) timf = state->timf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) timf *= (bw / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (update_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) s16 tim_offs = dib3000mc_read_word(state, 416);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (tim_offs & 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) tim_offs -= 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (nfft == TRANSMISSION_MODE_2K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) tim_offs *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) timf += tim_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) state->timf = timf / (bw / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dprintk("timf: %d\n", timf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dib3000mc_write_word(state, 23, (u16) (timf >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dib3000mc_write_word(state, 24, (u16) (timf ) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int dib3000mc_setup_pwm_state(struct dib3000mc_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u16 reg_51, reg_52 = state->cfg->agc->setup & 0xfefb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (state->cfg->pwm3_inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) reg_51 = (2 << 14) | (0 << 10) | (7 << 6) | (2 << 2) | (2 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) reg_52 |= (1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) reg_51 = (2 << 14) | (4 << 10) | (7 << 6) | (2 << 2) | (2 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) reg_52 |= (1 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dib3000mc_write_word(state, 51, reg_51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dib3000mc_write_word(state, 52, reg_52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (state->cfg->use_pwm3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dib3000mc_write_word(state, 245, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dib3000mc_write_word(state, 1040, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int dib3000mc_set_output_mode(struct dib3000mc_state *state, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u16 fifo_threshold = 1792;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u16 outreg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u16 outmode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u16 elecout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u16 smo_reg = dib3000mc_read_word(state, 206) & 0x0010; /* keep the pid_parse bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dprintk("-I- Setting output mode for demod %p to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) &state->demod, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case OUTMODE_HIGH_Z: // disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) elecout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) outmode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) outmode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case OUTMODE_MPEG2_SERIAL: // STBs with serial input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) outmode = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) elecout = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*ADDR @ 206 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) P_smo_error_discard [1;6:6] = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) P_smo_rs_discard [1;5:5] = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) P_smo_pid_parse [1;4:4] = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) P_smo_fifo_flush [1;3:3] = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) P_smo_mode [2;2:1] = 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) P_smo_ovf_prot [1;0:0] = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) smo_reg |= 3 << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) fifo_threshold = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) outmode = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) case OUTMODE_DIVERSITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) outmode = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) elecout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dprintk("Unhandled output_mode passed to be set for demod %p\n",&state->demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) outmode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if ((state->cfg->output_mpeg2_in_188_bytes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) smo_reg |= (1 << 5); // P_smo_rs_discard [1;5:5] = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) outreg = dib3000mc_read_word(state, 244) & 0x07FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) outreg |= (outmode << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret |= dib3000mc_write_word(state, 244, outreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ret |= dib3000mc_write_word(state, 206, smo_reg); /*smo_ mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret |= dib3000mc_write_word(state, 207, fifo_threshold); /* synchronous fread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret |= dib3000mc_write_word(state, 1040, elecout); /* P_out_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int dib3000mc_set_bandwidth(struct dib3000mc_state *state, u32 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u16 bw_cfg[6] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u16 imp_bw_cfg[3] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* settings here are for 27.7MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) switch (bw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) bw_cfg[0] = 0x0019; bw_cfg[1] = 0x5c30; bw_cfg[2] = 0x0054; bw_cfg[3] = 0x88a0; bw_cfg[4] = 0x01a6; bw_cfg[5] = 0xab20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) imp_bw_cfg[0] = 0x04db; imp_bw_cfg[1] = 0x00db; imp_bw_cfg[2] = 0x00b7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case 7000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bw_cfg[0] = 0x001c; bw_cfg[1] = 0xfba5; bw_cfg[2] = 0x0060; bw_cfg[3] = 0x9c25; bw_cfg[4] = 0x01e3; bw_cfg[5] = 0x0cb7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) imp_bw_cfg[0] = 0x04c0; imp_bw_cfg[1] = 0x00c0; imp_bw_cfg[2] = 0x00a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case 6000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) bw_cfg[0] = 0x0021; bw_cfg[1] = 0xd040; bw_cfg[2] = 0x0070; bw_cfg[3] = 0xb62b; bw_cfg[4] = 0x0233; bw_cfg[5] = 0x8ed5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) imp_bw_cfg[0] = 0x04a5; imp_bw_cfg[1] = 0x00a5; imp_bw_cfg[2] = 0x0089;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case 5000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) bw_cfg[0] = 0x0028; bw_cfg[1] = 0x9380; bw_cfg[2] = 0x0087; bw_cfg[3] = 0x4100; bw_cfg[4] = 0x02a4; bw_cfg[5] = 0x4500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) imp_bw_cfg[0] = 0x0489; imp_bw_cfg[1] = 0x0089; imp_bw_cfg[2] = 0x0072;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) default: return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) for (reg = 6; reg < 12; reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dib3000mc_write_word(state, reg, bw_cfg[reg - 6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dib3000mc_write_word(state, 12, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dib3000mc_write_word(state, 13, 0x03e8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dib3000mc_write_word(state, 14, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dib3000mc_write_word(state, 15, 0x03f2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dib3000mc_write_word(state, 16, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dib3000mc_write_word(state, 17, 0xb0d0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) // P_sec_len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dib3000mc_write_word(state, 18, 0x0393);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dib3000mc_write_word(state, 19, 0x8700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) for (reg = 55; reg < 58; reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) // Timing configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static u16 impulse_noise_val[29] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x38, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c, 0x3ffe, 0x7f3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 0x2d94, 0x76, 0x53d, 0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3, 0x3feb, 0x7d2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0x365e, 0x76, 0x48c, 0x3ffe, 0x5b3, 0x3feb, 0x76, 0x0000, 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void dib3000mc_set_impulse_noise(struct dib3000mc_state *state, u8 mode, s16 nfft)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u16 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) for (i = 58; i < 87; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dib3000mc_write_word(state, i, impulse_noise_val[i-58]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (nfft == TRANSMISSION_MODE_8K) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dib3000mc_write_word(state, 58, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dib3000mc_write_word(state, 84, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dib3000mc_write_word(state, 85, 0x8200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dib3000mc_write_word(state, 34, 0x1294);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dib3000mc_write_word(state, 35, 0x1ff8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (mode == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dib3000mc_write_word(state, 55, dib3000mc_read_word(state, 55) | (1 << 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int dib3000mc_init(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct dib3000mc_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct dibx000_agc_config *agc = state->cfg->agc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) // Restart Configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dib3000mc_write_word(state, 1027, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dib3000mc_write_word(state, 1027, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) // power up the demod + mobility configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dib3000mc_write_word(state, 140, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dib3000mc_write_word(state, 1031, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (state->cfg->mobile_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dib3000mc_write_word(state, 139, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dib3000mc_write_word(state, 141, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dib3000mc_write_word(state, 175, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dib3000mc_write_word(state, 1032, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dib3000mc_write_word(state, 139, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dib3000mc_write_word(state, 141, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dib3000mc_write_word(state, 175, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dib3000mc_write_word(state, 1032, 0x012C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dib3000mc_write_word(state, 1033, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) // P_clk_cfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dib3000mc_write_word(state, 1037, 0x3130);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) // other configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) // P_ctrl_sfreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dib3000mc_write_word(state, 33, (5 << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dib3000mc_write_word(state, 88, (1 << 10) | (0x10 << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) // Phase noise control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) // P_fft_phacor_inh, P_fft_phacor_cpe, P_fft_powrange
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dib3000mc_write_word(state, 99, (1 << 9) | (0x20 << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (state->cfg->phase_noise_mode == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dib3000mc_write_word(state, 111, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dib3000mc_write_word(state, 111, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) // P_agc_global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dib3000mc_write_word(state, 50, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) // agc setup misc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dib3000mc_setup_pwm_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) // P_agc_counter_lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dib3000mc_write_word(state, 53, 0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) // P_agc_counter_unlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dib3000mc_write_word(state, 54, 0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* agc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dib3000mc_write_word(state, 36, state->cfg->max_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dib3000mc_write_word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12) | (0x1d << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dib3000mc_write_word(state, 38, state->cfg->pwm3_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dib3000mc_write_word(state, 39, state->cfg->ln_adc_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) // set_agc_loop_Bw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dib3000mc_write_word(state, 40, 0x0179);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dib3000mc_write_word(state, 41, 0x03f0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dib3000mc_write_word(state, 42, agc->agc1_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dib3000mc_write_word(state, 43, agc->agc1_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dib3000mc_write_word(state, 44, agc->agc2_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dib3000mc_write_word(state, 45, agc->agc2_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dib3000mc_write_word(state, 46, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dib3000mc_write_word(state, 47, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dib3000mc_write_word(state, 48, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dib3000mc_write_word(state, 49, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) // Begin: TimeOut registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) // P_pha3_thres
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dib3000mc_write_word(state, 110, 3277);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) // P_timf_alpha = 6, P_corm_alpha = 6, P_corm_thres = 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dib3000mc_write_word(state, 26, 0x6680);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) // lock_mask0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dib3000mc_write_word(state, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) // lock_mask1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dib3000mc_write_word(state, 2, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) // lock_mask2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dib3000mc_write_word(state, 3, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) // P_search_maxtrial=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dib3000mc_write_word(state, 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dib3000mc_set_bandwidth(state, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) // div_lock_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dib3000mc_write_word(state, 4, 0x814);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dib3000mc_write_word(state, 21, (1 << 9) | 0x164);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dib3000mc_write_word(state, 22, 0x463d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) // Spurious rm cfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) // P_cspu_regul, P_cspu_win_cut
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dib3000mc_write_word(state, 120, 0x200f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) // P_adp_selec_monit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dib3000mc_write_word(state, 134, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) // Fec cfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dib3000mc_write_word(state, 195, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) // diversity register: P_dvsy_sync_wait..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dib3000mc_write_word(state, 180, 0x2FF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) // Impulse noise configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dib3000mc_set_impulse_noise(state, 0, TRANSMISSION_MODE_8K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) // output mode set-up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* close the i2c-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dib3000mc_write_word(state, 769, (1 << 7) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int dib3000mc_sleep(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct dib3000mc_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dib3000mc_write_word(state, 1031, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dib3000mc_write_word(state, 1032, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dib3000mc_write_word(state, 1033, 0xFFF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u16 cfg[4] = { 0 },reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) switch (qam) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case QPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) cfg[0] = 0x099a; cfg[1] = 0x7fae; cfg[2] = 0x0333; cfg[3] = 0x7ff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cfg[0] = 0x023d; cfg[1] = 0x7fdf; cfg[2] = 0x00a4; cfg[3] = 0x7ff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) cfg[0] = 0x0148; cfg[1] = 0x7ff0; cfg[2] = 0x00a4; cfg[3] = 0x7ff8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) for (reg = 129; reg < 133; reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dib3000mc_write_word(state, reg, cfg[reg - 129]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct dtv_frontend_properties *ch, u16 seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u32 bw = BANDWIDTH_TO_KHZ(ch->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dib3000mc_set_bandwidth(state, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dib3000mc_set_timing(state, ch->transmission_mode, bw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dib3000mc_write_word(state, 100, (16 << 6) + 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (boost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dib3000mc_write_word(state, 100, (11 << 6) + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dib3000mc_write_word(state, 100, (16 << 6) + 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dib3000mc_write_word(state, 1027, 0x0800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dib3000mc_write_word(state, 1027, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) //Default cfg isi offset adp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dib3000mc_write_word(state, 26, 0x6680);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dib3000mc_write_word(state, 29, 0x1273);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dib3000mc_write_word(state, 33, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dib3000mc_set_adp_cfg(state, QAM_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dib3000mc_write_word(state, 133, 15564);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dib3000mc_write_word(state, 12 , 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dib3000mc_write_word(state, 13 , 0x3e8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dib3000mc_write_word(state, 14 , 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dib3000mc_write_word(state, 15 , 0x3f2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dib3000mc_write_word(state, 93,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dib3000mc_write_word(state, 94,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dib3000mc_write_word(state, 95,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dib3000mc_write_word(state, 96,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dib3000mc_write_word(state, 97,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dib3000mc_write_word(state, 98,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dib3000mc_set_impulse_noise(state, 0, ch->transmission_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) switch (ch->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) switch (ch->guard_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case GUARD_INTERVAL_1_4: value |= (3 << 5); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case GUARD_INTERVAL_1_8: value |= (2 << 5); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) switch (ch->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case QPSK: value |= (0 << 3); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case QAM_16: value |= (1 << 3); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case QAM_64: value |= (2 << 3); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) switch (HIERARCHY_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case HIERARCHY_2: value |= 2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case HIERARCHY_4: value |= 4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case HIERARCHY_1: value |= 1; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dib3000mc_write_word(state, 0, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ch->hierarchy == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) value |= (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (1 == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) value |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) case FEC_2_3: value |= (2 << 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case FEC_3_4: value |= (3 << 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case FEC_5_6: value |= (5 << 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case FEC_7_8: value |= (7 << 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case FEC_1_2: value |= (1 << 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dib3000mc_write_word(state, 181, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) // diversity synchro delay add 50% SFN margin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) switch (ch->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case TRANSMISSION_MODE_8K: value = 256; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) case TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) default: value = 64; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) switch (ch->guard_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case GUARD_INTERVAL_1_16: value *= 2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case GUARD_INTERVAL_1_8: value *= 4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case GUARD_INTERVAL_1_4: value *= 8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case GUARD_INTERVAL_1_32: value *= 1; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) value <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) value |= dib3000mc_read_word(state, 180) & 0x000f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dib3000mc_write_word(state, 180, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) // restart demod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) value = dib3000mc_read_word(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dib3000mc_write_word(state, 0, value | (1 << 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dib3000mc_write_word(state, 0, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->transmission_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int dib3000mc_autosearch_start(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct dtv_frontend_properties *chan = &demod->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct dib3000mc_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) // u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct dtv_frontend_properties schan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) schan = *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* TODO what is that ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* a channel for autosearch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) schan.transmission_mode = TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) schan.guard_interval = GUARD_INTERVAL_1_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) schan.modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) schan.code_rate_HP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) schan.code_rate_LP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) schan.hierarchy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dib3000mc_set_channel_cfg(state, &schan, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) reg = dib3000mc_read_word(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dib3000mc_write_word(state, 0, reg | (1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dib3000mc_read_word(state, 511);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dib3000mc_write_word(state, 0, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int dib3000mc_autosearch_is_irq(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct dib3000mc_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u16 irq_pending = dib3000mc_read_word(state, 511);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (irq_pending & 0x1) // failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (irq_pending & 0x2) // succeeded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return 0; // still pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static int dib3000mc_tune(struct dvb_frontend *demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct dib3000mc_state *state = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) // ** configure demod **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dib3000mc_set_channel_cfg(state, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) // activates isi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (state->sfn_workaround_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dprintk("SFN workaround is active\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dib3000mc_write_word(state, 29, 0x1273);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dib3000mc_write_word(state, 108, 0x4000); // P_pha3_force_pha_shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dib3000mc_write_word(state, 29, 0x1073);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dib3000mc_write_word(state, 108, 0x0000); // P_pha3_force_pha_shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dib3000mc_set_adp_cfg(state, (u8)ch->modulation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (ch->transmission_mode == TRANSMISSION_MODE_8K) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dib3000mc_write_word(state, 26, 38528);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dib3000mc_write_word(state, 33, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dib3000mc_write_word(state, 26, 30336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dib3000mc_write_word(state, 33, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (dib3000mc_read_word(state, 509) & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dib3000mc_set_timing(state, ch->transmission_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) BANDWIDTH_TO_KHZ(ch->bandwidth_hz), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct i2c_adapter * dib3000mc_get_tuner_i2c_master(struct dvb_frontend *demod, int gating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct dib3000mc_state *st = demod->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return dibx000_get_i2c_adapter(&st->i2c_master, DIBX000_I2C_INTERFACE_TUNER, gating);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) EXPORT_SYMBOL(dib3000mc_get_tuner_i2c_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int dib3000mc_get_frontend(struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct dtv_frontend_properties *fep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct dib3000mc_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u16 tps = dib3000mc_read_word(state,458);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) fep->inversion = INVERSION_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) fep->bandwidth_hz = state->current_bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) switch ((tps >> 8) & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) case 0: fep->transmission_mode = TRANSMISSION_MODE_2K; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case 1: fep->transmission_mode = TRANSMISSION_MODE_8K; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) switch (tps & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case 0: fep->guard_interval = GUARD_INTERVAL_1_32; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case 1: fep->guard_interval = GUARD_INTERVAL_1_16; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case 2: fep->guard_interval = GUARD_INTERVAL_1_8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case 3: fep->guard_interval = GUARD_INTERVAL_1_4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) switch ((tps >> 13) & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case 0: fep->modulation = QPSK; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) case 1: fep->modulation = QAM_16; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) default: fep->modulation = QAM_64; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* (tps >> 12) & 0x1 == hrch is used, (tps >> 9) & 0x7 == alpha */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) fep->hierarchy = HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) switch ((tps >> 5) & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case 1: fep->code_rate_HP = FEC_1_2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) case 2: fep->code_rate_HP = FEC_2_3; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) case 3: fep->code_rate_HP = FEC_3_4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case 5: fep->code_rate_HP = FEC_5_6; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) default: fep->code_rate_HP = FEC_7_8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) switch ((tps >> 2) & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) case 1: fep->code_rate_LP = FEC_1_2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case 2: fep->code_rate_LP = FEC_2_3; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) case 3: fep->code_rate_LP = FEC_3_4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) case 5: fep->code_rate_LP = FEC_5_6; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) default: fep->code_rate_LP = FEC_7_8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static int dib3000mc_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct dib3000mc_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) state->current_bandwidth = fep->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* maybe the parameter has been changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) state->sfn_workaround_active = buggy_sfn_workaround;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) fep->guard_interval == GUARD_INTERVAL_AUTO ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) fep->modulation == QAM_AUTO ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) fep->code_rate_HP == FEC_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) int i = 1000, found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dib3000mc_autosearch_start(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) found = dib3000mc_autosearch_is_irq(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) } while (found == 0 && i--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dprintk("autosearch returns: %d\n",found);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (found == 0 || found == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return 0; // no channel found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dib3000mc_get_frontend(fe, fep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = dib3000mc_tune(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* make this a config parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int dib3000mc_read_status(struct dvb_frontend *fe, enum fe_status *stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct dib3000mc_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u16 lock = dib3000mc_read_word(state, 509);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) *stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (lock & 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) *stat |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (lock & 0x3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) *stat |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (lock & 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) *stat |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (lock & 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) *stat |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (lock & 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) *stat |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int dib3000mc_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct dib3000mc_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) *ber = (dib3000mc_read_word(state, 500) << 16) | dib3000mc_read_word(state, 501);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int dib3000mc_read_unc_blocks(struct dvb_frontend *fe, u32 *unc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct dib3000mc_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) *unc = dib3000mc_read_word(state, 508);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int dib3000mc_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct dib3000mc_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u16 val = dib3000mc_read_word(state, 392);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) *strength = 65535 - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int dib3000mc_read_snr(struct dvb_frontend* fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) *snr = 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static int dib3000mc_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) tune->min_delay_ms = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static void dib3000mc_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct dib3000mc_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dibx000_exit_i2c_master(&state->i2c_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) int dib3000mc_pid_control(struct dvb_frontend *fe, int index, int pid,int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct dib3000mc_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dib3000mc_write_word(state, 212 + index, onoff ? (1 << 13) | pid : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) EXPORT_SYMBOL(dib3000mc_pid_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) int dib3000mc_pid_parse(struct dvb_frontend *fe, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct dib3000mc_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u16 tmp = dib3000mc_read_word(state, 206) & ~(1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) tmp |= (onoff << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return dib3000mc_write_word(state, 206, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) EXPORT_SYMBOL(dib3000mc_pid_parse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) void dib3000mc_set_config(struct dvb_frontend *fe, struct dib3000mc_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct dib3000mc_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) state->cfg = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) EXPORT_SYMBOL(dib3000mc_set_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) int dib3000mc_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib3000mc_config cfg[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct dib3000mc_state *dmcst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u8 new_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static u8 DIB3000MC_I2C_ADDRESS[] = {20,22,24,26};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) dmcst = kzalloc(sizeof(struct dib3000mc_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (dmcst == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dmcst->i2c_adap = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) for (k = no_of_demods-1; k >= 0; k--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dmcst->cfg = &cfg[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* designated i2c address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) new_addr = DIB3000MC_I2C_ADDRESS[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dmcst->i2c_addr = new_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (dib3000mc_identify(dmcst) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dmcst->i2c_addr = default_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (dib3000mc_identify(dmcst) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dprintk("-E- DiB3000P/MC #%d: not identified\n", k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) kfree(dmcst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dib3000mc_set_output_mode(dmcst, OUTMODE_MPEG2_PAR_CONT_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) // set new i2c address and force divstr (Bit 1) to value 0 (Bit 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) dib3000mc_write_word(dmcst, 1024, (new_addr << 3) | 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dmcst->i2c_addr = new_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) for (k = 0; k < no_of_demods; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) dmcst->cfg = &cfg[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) dmcst->i2c_addr = DIB3000MC_I2C_ADDRESS[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dib3000mc_write_word(dmcst, 1024, dmcst->i2c_addr << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* turn off data output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dib3000mc_set_output_mode(dmcst, OUTMODE_HIGH_Z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) kfree(dmcst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) EXPORT_SYMBOL(dib3000mc_i2c_enumeration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static const struct dvb_frontend_ops dib3000mc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct dvb_frontend * dib3000mc_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib3000mc_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct dvb_frontend *demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct dib3000mc_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) st = kzalloc(sizeof(struct dib3000mc_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (st == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) st->cfg = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) st->i2c_adap = i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) st->i2c_addr = i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) demod = &st->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) demod->demodulator_priv = st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) memcpy(&st->demod.ops, &dib3000mc_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (dib3000mc_identify(st) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dibx000_init_i2c_master(&st->i2c_master, DIB3000MC, st->i2c_adap, st->i2c_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) dib3000mc_write_word(st, 1037, 0x3130);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) kfree(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) EXPORT_SYMBOL(dib3000mc_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static const struct dvb_frontend_ops dib3000mc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .name = "DiBcom 3000MC/P",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .frequency_min_hz = 44250 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .frequency_max_hz = 867250 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .frequency_stepsize_hz = 62500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) FE_CAN_TRANSMISSION_MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) FE_CAN_GUARD_INTERVAL_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) FE_CAN_RECOVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) FE_CAN_HIERARCHY_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .release = dib3000mc_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .init = dib3000mc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .sleep = dib3000mc_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .set_frontend = dib3000mc_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .get_tune_settings = dib3000mc_fe_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .get_frontend = dib3000mc_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .read_status = dib3000mc_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .read_ber = dib3000mc_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .read_signal_strength = dib3000mc_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .read_snr = dib3000mc_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .read_ucblocks = dib3000mc_read_unc_blocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) MODULE_AUTHOR("Patrick Boettcher <patrick.boettcher@posteo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) MODULE_DESCRIPTION("Driver for the DiBcom 3000MC/P COFDM demodulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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