^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * dib3000mb_priv.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@posteo.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * for more information see dib3000mb.c .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __DIB3000MB_PRIV_H_INCLUDED__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __DIB3000MB_PRIV_H_INCLUDED__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* handy shortcuts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define rd(reg) dib3000_read_reg(state,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define wr(reg,val) if (dib3000_write_reg(state,reg,val)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) { pr_err("while sending 0x%04x to 0x%04x.", val, reg); return -EREMOTEIO; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define wr_foreach(a,v) { int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) if (sizeof(a) != sizeof(v)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) pr_err("sizeof: %zu %zu is different", sizeof(a), sizeof(v));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) for (i=0; i < sizeof(a)/sizeof(u16); i++) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) wr(a[i],v[i]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define set_or(reg,val) wr(reg,rd(reg) | val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define set_and(reg,val) wr(reg,rd(reg) & val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define dprintk(level, fmt, arg...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if (debug & level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) printk(KERN_DEBUG pr_fmt("%s: " fmt), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) __func__, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* mask for enabling a specific pid for the pid_filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DIB3000_ACTIVATE_PID_FILTERING (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* common values for tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DIB3000_ALPHA_0 ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DIB3000_ALPHA_1 ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DIB3000_ALPHA_2 ( 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DIB3000_ALPHA_4 ( 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DIB3000_CONSTELLATION_QPSK ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DIB3000_CONSTELLATION_16QAM ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DIB3000_CONSTELLATION_64QAM ( 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DIB3000_GUARD_TIME_1_32 ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DIB3000_GUARD_TIME_1_16 ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DIB3000_GUARD_TIME_1_8 ( 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DIB3000_GUARD_TIME_1_4 ( 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DIB3000_TRANSMISSION_MODE_2K ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DIB3000_TRANSMISSION_MODE_8K ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DIB3000_SELECT_LP ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DIB3000_SELECT_HP ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DIB3000_FEC_1_2 ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DIB3000_FEC_2_3 ( 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DIB3000_FEC_3_4 ( 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DIB3000_FEC_5_6 ( 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DIB3000_FEC_7_8 ( 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DIB3000_HRCH_OFF ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DIB3000_HRCH_ON ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DIB3000_DDS_INVERSION_OFF ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DIB3000_DDS_INVERSION_ON ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DIB3000_TUNER_WRITE_ENABLE(a) (0xffff & (a << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DIB3000_TUNER_WRITE_DISABLE(a) (0xffff & ((a << 8) | (1 << 7)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DIB3000_REG_MANUFACTOR_ID ( 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DIB3000_I2C_ID_DIBCOM (0x01b3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DIB3000_REG_DEVICE_ID ( 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DIB3000MB_DEVICE_ID (0x3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DIB3000MC_DEVICE_ID (0x3001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DIB3000P_DEVICE_ID (0x3002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* frontend state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct dib3000_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct dib3000_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int timing_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int timing_offset_comp_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 last_tuned_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 last_tuned_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* register addresses and some of their default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* restart subsystems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DIB3000MB_REG_RESTART ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DIB3000MB_RESTART_OFF ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DIB3000MB_RESTART_AUTO_SEARCH (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DIB3000MB_RESTART_CTRL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DIB3000MB_RESTART_AGC (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* FFT size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DIB3000MB_REG_FFT ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Guard time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DIB3000MB_REG_GUARD_TIME ( 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* QAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DIB3000MB_REG_QAM ( 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Alpha coefficient high priority Viterbi algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DIB3000MB_REG_VIT_ALPHA ( 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* spectrum inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DIB3000MB_REG_DDS_INV ( 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* DDS frequency value (IF position) ad ? values don't match reg_3000mb.txt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DIB3000MB_REG_DDS_FREQ_MSB ( 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DIB3000MB_REG_DDS_FREQ_LSB ( 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DIB3000MB_DDS_FREQ_MSB ( 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DIB3000MB_DDS_FREQ_LSB ( 8990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* timing frequency (carrier spacing) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static u16 dib3000mb_reg_timing_freq[] = { 8,9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static u16 dib3000mb_timing_freq[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 126 , 48873 }, /* 6 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 147 , 57019 }, /* 7 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 168 , 65164 }, /* 8 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* impulse noise parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* 36 ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static u16 dib3000mb_reg_impulse_noise[] = { 10,11,12,15,36 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum dib3000mb_impulse_noise_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DIB3000MB_IMPNOISE_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DIB3000MB_IMPNOISE_MOBILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DIB3000MB_IMPNOISE_FIXED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DIB3000MB_IMPNOISE_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static u16 dib3000mb_impulse_noise_values[][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { 0x0000, 0x0004, 0x0014, 0x01ff, 0x0399 }, /* off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { 0x0001, 0x0004, 0x0014, 0x01ff, 0x037b }, /* mobile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 0x0001, 0x0004, 0x0020, 0x01bd, 0x0399 }, /* fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { 0x0000, 0x0002, 0x000a, 0x01ff, 0x0399 }, /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Dual Automatic-Gain-Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * - gains RF in tuner (AGC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * - gains IF after filtering (AGC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* also from 16 to 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static u16 dib3000mb_reg_agc_gain[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 19,20,21,22,23,24,25,26,27,28,29,30,31,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static u16 dib3000mb_default_agc_gain[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 0x0001, 52429, 623, 128, 166, 195, 61, /* RF ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0x0001, 53766, 38011, 0, 90, 33, 23 }; /* IF ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* phase noise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* 36 is set when setting the impulse noise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static u16 dib3000mb_reg_phase_noise[] = { 33,34,35,37,38 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static u16 dib3000mb_default_noise_phase[] = { 2, 544, 0, 5, 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* lock duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static u16 dib3000mb_reg_lock_duration[] = { 39,40 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static u16 dib3000mb_default_lock_duration[] = { 135, 135 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* AGC loop bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static u16 dib3000mb_reg_agc_bandwidth[] = { 43,44,45,46,47,48,49,50 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static u16 dib3000mb_agc_bandwidth_low[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 2088, 10, 2088, 10, 3448, 5, 3448, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static u16 dib3000mb_agc_bandwidth_high[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 2349, 5, 2349, 5, 2586, 2, 2586, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * lock0 definition (coff_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DIB3000MB_REG_LOCK0_MASK ( 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DIB3000MB_LOCK0_DEFAULT ( 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * lock1 definition (cpil_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * for auto search
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * which values hide behind the lock masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DIB3000MB_REG_LOCK1_MASK ( 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DIB3000MB_LOCK1_SEARCH_4 (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DIB3000MB_LOCK1_SEARCH_2048 (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DIB3000MB_LOCK1_DEFAULT (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * lock2 definition (fec_lock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DIB3000MB_REG_LOCK2_MASK ( 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DIB3000MB_LOCK2_DEFAULT (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * SEQ ? what was that again ... :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * changes when, inversion, guard time and fft is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * either automatically detected or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DIB3000MB_REG_SEQ ( 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static u16 dib3000mb_reg_bandwidth[] = { 55,56,57,58,59,60,61,62,63,64,65,66,67 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static u16 dib3000mb_bandwidth_6mhz[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 0, 33, 53312, 112, 46635, 563, 36565, 0, 1000, 0, 1010, 1, 45264 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static u16 dib3000mb_bandwidth_7mhz[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { 0, 28, 64421, 96, 39973, 483, 3255, 0, 1000, 0, 1010, 1, 45264 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static u16 dib3000mb_bandwidth_8mhz[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 0, 25, 23600, 84, 34976, 422, 43808, 0, 1000, 0, 1010, 1, 45264 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define DIB3000MB_REG_UNK_68 ( 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DIB3000MB_UNK_68 ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DIB3000MB_REG_UNK_69 ( 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DIB3000MB_UNK_69 ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DIB3000MB_REG_UNK_71 ( 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DIB3000MB_UNK_71 ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DIB3000MB_REG_UNK_77 ( 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DIB3000MB_UNK_77 ( 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DIB3000MB_REG_UNK_78 ( 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DIB3000MB_UNK_78 (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* isi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DIB3000MB_REG_ISI ( 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define DIB3000MB_ISI_ACTIVATE ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define DIB3000MB_ISI_INHIBIT ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* sync impovement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DIB3000MB_REG_SYNC_IMPROVEMENT ( 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define DIB3000MB_SYNC_IMPROVE_2K_1_8 ( 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DIB3000MB_SYNC_IMPROVE_DEFAULT ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* phase noise compensation inhibition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DIB3000MB_REG_PHASE_NOISE ( 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DIB3000MB_PHASE_NOISE_DEFAULT ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DIB3000MB_REG_UNK_92 ( 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DIB3000MB_UNK_92 (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DIB3000MB_REG_UNK_96 ( 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DIB3000MB_UNK_96 (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DIB3000MB_REG_UNK_97 ( 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DIB3000MB_UNK_97 (0x0009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* mobile mode ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DIB3000MB_REG_MOBILE_MODE ( 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DIB3000MB_MOBILE_MODE_ON ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DIB3000MB_MOBILE_MODE_OFF ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DIB3000MB_REG_UNK_106 ( 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DIB3000MB_UNK_106 (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DIB3000MB_REG_UNK_107 ( 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DIB3000MB_UNK_107 (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DIB3000MB_REG_UNK_108 ( 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define DIB3000MB_UNK_108 (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* fft */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define DIB3000MB_REG_UNK_121 ( 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define DIB3000MB_UNK_121_2K ( 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define DIB3000MB_UNK_121_DEFAULT ( 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define DIB3000MB_REG_UNK_122 ( 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DIB3000MB_UNK_122 ( 2867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* QAM for mobile mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define DIB3000MB_REG_MOBILE_MODE_QAM ( 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define DIB3000MB_MOBILE_MODE_QAM_64 ( 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define DIB3000MB_MOBILE_MODE_QAM_QPSK_16 ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define DIB3000MB_MOBILE_MODE_QAM_OFF ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * data diversity when having more than one chip on-board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * see also DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DIB3000MB_REG_DATA_IN_DIVERSITY ( 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DIB3000MB_DATA_DIVERSITY_IN_OFF ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DIB3000MB_DATA_DIVERSITY_IN_ON ( 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* vit hrch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DIB3000MB_REG_VIT_HRCH ( 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* vit code rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DIB3000MB_REG_VIT_CODE_RATE ( 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* vit select hp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DIB3000MB_REG_VIT_HP ( 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* time frame for Bit-Error-Rate calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define DIB3000MB_REG_BERLEN ( 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define DIB3000MB_BERLEN_LONG ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define DIB3000MB_BERLEN_DEFAULT ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define DIB3000MB_BERLEN_MEDIUM ( 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define DIB3000MB_BERLEN_SHORT ( 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* 142 - 152 FIFO parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * which is what ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DIB3000MB_REG_FIFO_142 ( 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DIB3000MB_FIFO_142 ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* MPEG2 TS output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DIB3000MB_REG_MPEG2_OUT_MODE ( 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DIB3000MB_MPEG2_OUT_MODE_204 ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DIB3000MB_MPEG2_OUT_MODE_188 ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DIB3000MB_REG_PID_PARSE ( 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DIB3000MB_PID_PARSE_INHIBIT ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DIB3000MB_PID_PARSE_ACTIVATE ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DIB3000MB_REG_FIFO ( 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DIB3000MB_FIFO_INHIBIT ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define DIB3000MB_FIFO_ACTIVATE ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DIB3000MB_REG_FIFO_146 ( 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DIB3000MB_FIFO_146 ( 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DIB3000MB_REG_FIFO_147 ( 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define DIB3000MB_FIFO_147 (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * pidfilter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * it is not a hardware pidfilter but a filter which drops all pids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * except the ones set. Necessary because of the limited USB1.1 bandwidth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * regs 153-168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define DIB3000MB_REG_FIRST_PID ( 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DIB3000MB_NUM_PIDS ( 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * output mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * USB devices have to use 'slave'-mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * see also DIB3000MB_REG_ELECT_OUT_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DIB3000MB_REG_OUTPUT_MODE ( 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define DIB3000MB_OUTPUT_MODE_GATED_CLK ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define DIB3000MB_OUTPUT_MODE_CONT_CLK ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define DIB3000MB_OUTPUT_MODE_SERIAL ( 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY ( 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DIB3000MB_OUTPUT_MODE_SLAVE ( 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* irq event mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define DIB3000MB_REG_IRQ_EVENT_MASK ( 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define DIB3000MB_IRQ_EVENT_MASK ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* filter coefficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static u16 dib3000mb_reg_filter_coeffs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 171, 172, 173, 174, 175, 176, 177, 178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 179, 180, 181, 182, 183, 184, 185, 186,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 188, 189, 190, 191, 192, 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static u16 dib3000mb_filter_coeffs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 226, 160, 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 979, 998, 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 22, 1019, 1006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 1022, 12, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 1017, 1017, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 6, 1019,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 1021, 2, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * mobile algorithm (when you are moving with your device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * but not faster than 90 km/h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define DIB3000MB_REG_MOBILE_ALGO ( 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define DIB3000MB_MOBILE_ALGO_ON ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define DIB3000MB_MOBILE_ALGO_OFF ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* multiple demodulators algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define DIB3000MB_REG_MULTI_DEMOD_MSB ( 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define DIB3000MB_REG_MULTI_DEMOD_LSB ( 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* terminator, no more demods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define DIB3000MB_MULTI_DEMOD_MSB ( 32767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define DIB3000MB_MULTI_DEMOD_LSB ( 4095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* bring the device into a known */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define DIB3000MB_REG_RESET_DEVICE ( 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define DIB3000MB_RESET_DEVICE (0x812c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define DIB3000MB_RESET_DEVICE_RST ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* hardware clock configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define DIB3000MB_REG_CLOCK ( 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define DIB3000MB_CLOCK_DEFAULT (0x9000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define DIB3000MB_CLOCK_DIVERSITY (0x92b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* power down config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define DIB3000MB_REG_POWER_CONTROL ( 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define DIB3000MB_POWER_DOWN ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define DIB3000MB_POWER_UP ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* electrical output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define DIB3000MB_REG_ELECT_OUT_MODE ( 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define DIB3000MB_ELECT_OUT_MODE_OFF ( 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define DIB3000MB_ELECT_OUT_MODE_ON ( 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* set the tuner i2c address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define DIB3000MB_REG_TUNER ( 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* monitoring registers (read only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* agc loop locked (size: 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define DIB3000MB_REG_AGC_LOCK ( 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* agc power (size: 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define DIB3000MB_REG_AGC_POWER ( 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* agc1 value (16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define DIB3000MB_REG_AGC1_VALUE ( 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* agc2 value (16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define DIB3000MB_REG_AGC2_VALUE ( 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* total RF power (16), can be used for signal strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define DIB3000MB_REG_RF_POWER ( 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* dds_frequency with offset (24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define DIB3000MB_REG_DDS_VALUE_MSB ( 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define DIB3000MB_REG_DDS_VALUE_LSB ( 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* timing offset signed (24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define DIB3000MB_REG_TIMING_OFFSET_MSB ( 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define DIB3000MB_REG_TIMING_OFFSET_LSB ( 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* fft start position (13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define DIB3000MB_REG_FFT_WINDOW_POS ( 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* carriers locked (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define DIB3000MB_REG_CARRIER_LOCK ( 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* noise power (24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define DIB3000MB_REG_NOISE_POWER_MSB ( 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define DIB3000MB_REG_NOISE_POWER_LSB ( 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define DIB3000MB_REG_MOBILE_NOISE_MSB ( 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define DIB3000MB_REG_MOBILE_NOISE_LSB ( 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * signal power (16), this and the above can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * used to calculate the signal/noise - ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define DIB3000MB_REG_SIGNAL_POWER ( 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* mer (24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define DIB3000MB_REG_MER_MSB ( 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define DIB3000MB_REG_MER_LSB ( 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * Transmission Parameter Signalling (TPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * the following registers can be used to get TPS-information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * The values are according to the DVB-T standard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* TPS locked (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define DIB3000MB_REG_TPS_LOCK ( 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* QAM from TPS (2) (values according to DIB3000MB_REG_QAM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define DIB3000MB_REG_TPS_QAM ( 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* hierarchy from TPS (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define DIB3000MB_REG_TPS_HRCH ( 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* alpha from TPS (3) (values according to DIB3000MB_REG_VIT_ALPHA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define DIB3000MB_REG_TPS_VIT_ALPHA ( 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* code rate high priority from TPS (3) (values according to DIB3000MB_FEC_*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define DIB3000MB_REG_TPS_CODE_RATE_HP ( 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* code rate low priority from TPS (3) if DIB3000MB_REG_TPS_VIT_ALPHA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define DIB3000MB_REG_TPS_CODE_RATE_LP ( 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* guard time from TPS (2) (values according to DIB3000MB_REG_GUARD_TIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define DIB3000MB_REG_TPS_GUARD_TIME ( 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* fft size from TPS (2) (values according to DIB3000MB_REG_FFT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define DIB3000MB_REG_TPS_FFT ( 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* cell id from TPS (16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define DIB3000MB_REG_TPS_CELL_ID ( 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* TPS (68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define DIB3000MB_REG_TPS_1 ( 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define DIB3000MB_REG_TPS_2 ( 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define DIB3000MB_REG_TPS_3 ( 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define DIB3000MB_REG_TPS_4 ( 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define DIB3000MB_REG_TPS_5 ( 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* bit error rate (before RS correction) (21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define DIB3000MB_REG_BER_MSB ( 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define DIB3000MB_REG_BER_LSB ( 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* packet error rate (uncorrected TS packets) (16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define DIB3000MB_REG_PACKET_ERROR_RATE ( 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* uncorrected packet count (16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define DIB3000MB_REG_UNC ( 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* viterbi locked (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define DIB3000MB_REG_VIT_LCK ( 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* viterbi inidcator (16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define DIB3000MB_REG_VIT_INDICATOR ( 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* transport stream sync lock (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define DIB3000MB_REG_TS_SYNC_LOCK ( 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* transport stream RS lock (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define DIB3000MB_REG_TS_RS_LOCK ( 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* lock mask 0 value (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define DIB3000MB_REG_LOCK0_VALUE ( 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* lock mask 1 value (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define DIB3000MB_REG_LOCK1_VALUE ( 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* lock mask 2 value (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define DIB3000MB_REG_LOCK2_VALUE ( 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* interrupt pending for auto search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define DIB3000MB_REG_AS_IRQ_PENDING ( 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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