^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * DiBcom (http://www.dibcom.fr/)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@posteo.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * based on GPL code from DibCom, which has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2004 Amaury Demol for DiBcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Acknowledgements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Amaury Demol from DiBcom for providing specs and driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * sources, on which this driver (and the dvb-dibusb) are based.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "dib3000.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "dib3000mb_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Version information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRIVER_VERSION "0.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@posteo.de"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define deb_info(args...) dprintk(0x01, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define deb_i2c(args...) dprintk(0x02, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define deb_srch(args...) dprintk(0x04, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define deb_info(args...) dprintk(0x01, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define deb_xfer(args...) dprintk(0x02, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define deb_setf(args...) dprintk(0x04, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define deb_getf(args...) dprintk(0x08, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int dib3000_read_reg(struct dib3000_state *state, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 wb[] = { ((reg >> 8) | 0x80) & 0xff, reg & 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 rb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { .addr = state->config.demod_address, .flags = 0, .buf = wb, .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .addr = state->config.demod_address, .flags = I2C_M_RD, .buf = rb, .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (i2c_transfer(state->i2c, msg, 2) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) deb_i2c("i2c read error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) deb_i2c("reading i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) (rb[0] << 8) | rb[1],(rb[0] << 8) | rb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return (rb[0] << 8) | rb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int dib3000_write_reg(struct dib3000_state *state, u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 b[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (reg >> 8) & 0xff, reg & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (val >> 8) & 0xff, val & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { .addr = state->config.demod_address, .flags = 0, .buf = b, .len = 4 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) deb_i2c("writing i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,val,val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return i2c_transfer(state->i2c,msg, 1) != 1 ? -EREMOTEIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int dib3000_search_status(u16 irq,u16 lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (irq & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (lock & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) deb_srch("auto search succeeded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 1; // auto search succeeded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) deb_srch("auto search not successful\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 0; // auto search failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } else if (irq & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) deb_srch("auto search failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0; // auto search failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return -1; // try again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* for auto search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static u16 dib3000_seq[2][2][2] = /* fft,gua, inv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { /* fft */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { /* gua */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0, 1 }, /* 0 0 { 0,1 } */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 3, 9 }, /* 0 1 { 0,1 } */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { 2, 5 }, /* 1 0 { 0,1 } */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { 6, 11 }, /* 1 1 { 0,1 } */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int dib3000mb_get_frontend(struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct dtv_frontend_properties *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int dib3000mb_set_frontend(struct dvb_frontend *fe, int tuner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct dib3000_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum fe_code_rate fe_cr = FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int search_state, seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (tuner && fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) switch (c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pr_err("unknown bandwidth value.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) deb_setf("bandwidth: %d MHZ\n", c->bandwidth_hz / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) switch (c->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) deb_setf("transmission mode: 2k\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case TRANSMISSION_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) deb_setf("transmission mode: 8k\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case TRANSMISSION_MODE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) deb_setf("transmission mode: auto\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) switch (c->guard_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case GUARD_INTERVAL_1_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) deb_setf("guard 1_32\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case GUARD_INTERVAL_1_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) deb_setf("guard 1_16\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case GUARD_INTERVAL_1_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) deb_setf("guard 1_8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case GUARD_INTERVAL_1_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) deb_setf("guard 1_4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case GUARD_INTERVAL_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) deb_setf("guard auto\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) switch (c->inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case INVERSION_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) deb_setf("inversion off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case INVERSION_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) deb_setf("inversion auto\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case INVERSION_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) deb_setf("inversion on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) switch (c->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case QPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) deb_setf("modulation: qpsk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) deb_setf("modulation: qam16\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) deb_setf("modulation: qam64\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case QAM_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) switch (c->hierarchy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case HIERARCHY_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) deb_setf("hierarchy: none\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case HIERARCHY_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) deb_setf("hierarchy: alpha=1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case HIERARCHY_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) deb_setf("hierarchy: alpha=2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case HIERARCHY_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) deb_setf("hierarchy: alpha=4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case HIERARCHY_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) deb_setf("hierarchy: alpha=auto\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (c->hierarchy == HIERARCHY_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) fe_cr = c->code_rate_HP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else if (c->hierarchy != HIERARCHY_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) fe_cr = c->code_rate_LP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) switch (fe_cr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) deb_setf("fec: 1_2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) deb_setf("fec: 2_3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) deb_setf("fec: 3_4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) deb_setf("fec: 5_6\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) deb_setf("fec: 7_8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case FEC_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) deb_setf("fec: none\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case FEC_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) deb_setf("fec: auto\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) seq = dib3000_seq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) [c->transmission_mode == TRANSMISSION_MODE_AUTO]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [c->guard_interval == GUARD_INTERVAL_AUTO]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [c->inversion == INVERSION_AUTO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) deb_setf("seq? %d\n", seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) wr(DIB3000MB_REG_SEQ, seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (c->transmission_mode == TRANSMISSION_MODE_2K) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (c->guard_interval == GUARD_INTERVAL_1_8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* wait for AGC lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) msleep(70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* something has to be auto searched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (c->modulation == QAM_AUTO ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) c->hierarchy == HIERARCHY_AUTO ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) fe_cr == FEC_AUTO ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) c->inversion == INVERSION_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int as_count=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) deb_setf("autosearch enabled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) while ((search_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dib3000_search_status(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) rd(DIB3000MB_REG_AS_IRQ_PENDING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) deb_setf("search_state after autosearch %d after %d checks\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) search_state, as_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (search_state == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (dib3000mb_get_frontend(fe, c) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) deb_setf("reading tuning data from frontend succeeded.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return dib3000mb_set_frontend(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct dib3000_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) deb_info("dib3000mb is getting up.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) wr_foreach(dib3000mb_reg_impulse_noise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int dib3000mb_get_frontend(struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct dtv_frontend_properties *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct dib3000_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) enum fe_code_rate *cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u16 tps_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int inv_test1,inv_test2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u32 dds_val, threshold = 0x800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!rd(DIB3000MB_REG_TPS_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) deb_getf("DDS_VAL: %x %x %x\n", dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (dds_val < threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) inv_test1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) else if (dds_val == threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) inv_test1 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) inv_test1 = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) deb_getf("DDS_FREQ: %x %x %x\n", dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (dds_val < threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) inv_test2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) else if (dds_val == threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) inv_test2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) inv_test2 = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) c->inversion =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) INVERSION_ON : INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, c->inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case DIB3000_CONSTELLATION_QPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) deb_getf("QPSK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) c->modulation = QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case DIB3000_CONSTELLATION_16QAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) deb_getf("QAM16\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) c->modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case DIB3000_CONSTELLATION_64QAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) deb_getf("QAM64\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) c->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) pr_err("Unexpected constellation returned by TPS (%d)\n", tps_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) deb_getf("TPS: %d\n", tps_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (rd(DIB3000MB_REG_TPS_HRCH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) deb_getf("HRCH ON\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) cr = &c->code_rate_LP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) c->code_rate_HP = FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case DIB3000_ALPHA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) deb_getf("HIERARCHY_NONE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) c->hierarchy = HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case DIB3000_ALPHA_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) deb_getf("HIERARCHY_1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) c->hierarchy = HIERARCHY_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) case DIB3000_ALPHA_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) deb_getf("HIERARCHY_2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) c->hierarchy = HIERARCHY_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case DIB3000_ALPHA_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) deb_getf("HIERARCHY_4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) c->hierarchy = HIERARCHY_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pr_err("Unexpected ALPHA value returned by TPS (%d)\n", tps_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) deb_getf("TPS: %d\n", tps_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) deb_getf("HRCH OFF\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) cr = &c->code_rate_HP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) c->code_rate_LP = FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) c->hierarchy = HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) switch (tps_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case DIB3000_FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) deb_getf("FEC_1_2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) *cr = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case DIB3000_FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) deb_getf("FEC_2_3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) *cr = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) case DIB3000_FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) deb_getf("FEC_3_4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) *cr = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case DIB3000_FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) deb_getf("FEC_5_6\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) *cr = FEC_4_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case DIB3000_FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) deb_getf("FEC_7_8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) *cr = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pr_err("Unexpected FEC returned by TPS (%d)\n", tps_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) deb_getf("TPS: %d\n",tps_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case DIB3000_GUARD_TIME_1_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) deb_getf("GUARD_INTERVAL_1_32\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) c->guard_interval = GUARD_INTERVAL_1_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case DIB3000_GUARD_TIME_1_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) deb_getf("GUARD_INTERVAL_1_16\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) c->guard_interval = GUARD_INTERVAL_1_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case DIB3000_GUARD_TIME_1_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) deb_getf("GUARD_INTERVAL_1_8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) c->guard_interval = GUARD_INTERVAL_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case DIB3000_GUARD_TIME_1_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) deb_getf("GUARD_INTERVAL_1_4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) c->guard_interval = GUARD_INTERVAL_1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) pr_err("Unexpected Guard Time returned by TPS (%d)\n", tps_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) deb_getf("TPS: %d\n", tps_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case DIB3000_TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) deb_getf("TRANSMISSION_MODE_2K\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) c->transmission_mode = TRANSMISSION_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case DIB3000_TRANSMISSION_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) deb_getf("TRANSMISSION_MODE_8K\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) c->transmission_mode = TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pr_err("unexpected transmission mode return by TPS (%d)\n", tps_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) deb_getf("TPS: %d\n", tps_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int dib3000mb_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) enum fe_status *stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct dib3000_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) *stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (rd(DIB3000MB_REG_AGC_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) *stat |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (rd(DIB3000MB_REG_CARRIER_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) *stat |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (rd(DIB3000MB_REG_VIT_LCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) *stat |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) deb_getf("actual status is %2x\n",*stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) rd(DIB3000MB_REG_TPS_LOCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) rd(DIB3000MB_REG_TPS_QAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) rd(DIB3000MB_REG_TPS_HRCH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) rd(DIB3000MB_REG_TPS_VIT_ALPHA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) rd(DIB3000MB_REG_TPS_GUARD_TIME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) rd(DIB3000MB_REG_TPS_FFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) rd(DIB3000MB_REG_TPS_CELL_ID));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct dib3000_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct dib3000_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct dib3000_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) rd(DIB3000MB_REG_NOISE_POWER_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct dib3000_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) *unc = rd(DIB3000MB_REG_PACKET_ERROR_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int dib3000mb_sleep(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct dib3000_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) deb_info("dib3000mb is going to bed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) tune->min_delay_ms = 800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return dib3000mb_fe_init(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return dib3000mb_set_frontend(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static void dib3000mb_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct dib3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* pid filter and transfer stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct dib3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) wr(index+DIB3000MB_REG_FIRST_PID,pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct dib3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (onoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct dib3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) wr(DIB3000MB_REG_PID_PARSE,onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct dib3000_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (onoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static const struct dvb_frontend_ops dib3000mb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct dib3000_state* state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) state = kzalloc(sizeof(struct dib3000_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) memcpy(&state->config,config,sizeof(struct dib3000_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* check for the correct demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) memcpy(&state->frontend.ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* set the xfer operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) xfer_ops->pid_parse = dib3000mb_pid_parse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) xfer_ops->pid_ctrl = dib3000mb_pid_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const struct dvb_frontend_ops dib3000mb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .name = "DiBcom 3000M-B DVB-T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .frequency_min_hz = 44250 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .frequency_max_hz = 867250 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .frequency_stepsize_hz = 62500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) FE_CAN_TRANSMISSION_MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) FE_CAN_GUARD_INTERVAL_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) FE_CAN_RECOVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) FE_CAN_HIERARCHY_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .release = dib3000mb_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .init = dib3000mb_fe_init_nonmobile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .sleep = dib3000mb_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .set_frontend = dib3000mb_set_frontend_and_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .get_frontend = dib3000mb_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .get_tune_settings = dib3000mb_fe_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .read_status = dib3000mb_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .read_ber = dib3000mb_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .read_signal_strength = dib3000mb_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .read_snr = dib3000mb_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .read_ucblocks = dib3000mb_read_unc_blocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) MODULE_AUTHOR(DRIVER_AUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) EXPORT_SYMBOL(dib3000mb_attach);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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