^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * cxd2841er.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Sony digital demodulator driver for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * CXD2841ER - DVB-S/S2/T/T2/C/C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2012 Sony Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2014 NetUP Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dynamic_debug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/dvb_math.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "cxd2841er.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "cxd2841er_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAX_WRITE_REGSIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LOG2_E_100X 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* DVB-C constellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum sony_dvbc_constellation_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SONY_DVBC_CONSTELLATION_16QAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SONY_DVBC_CONSTELLATION_32QAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SONY_DVBC_CONSTELLATION_64QAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SONY_DVBC_CONSTELLATION_128QAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SONY_DVBC_CONSTELLATION_256QAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) enum cxd2841er_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) STATE_SHUTDOWN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) STATE_SLEEP_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) STATE_ACTIVE_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) STATE_SLEEP_TC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) STATE_ACTIVE_TC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct cxd2841er_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 i2c_addr_slvx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 i2c_addr_slvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const struct cxd2841er_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum cxd2841er_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 system;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum cxd2841er_xtal xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum fe_caps caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long stats_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct cxd2841er_cnr_data s_cn_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 0x0015, 19900 }, { 0x0014, 20000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct cxd2841er_cnr_data s2_cn_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 addr, u8 reg, u8 write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) const u8 *data, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "cxd2841er: I2C %s addr %02x reg 0x%02x size %d data %*ph\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) (write == 0 ? "read" : "write"), addr, reg, len, len, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 addr, u8 reg, const u8 *data, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u8 buf[MAX_WRITE_REGSIZE + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 i2c_addr = (addr == I2C_SLVX ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) priv->i2c_addr_slvx : priv->i2c_addr_slvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct i2c_msg msg[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .addr = i2c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .len = len + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (len + 1 >= sizeof(buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) reg, len + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) buf[0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) memcpy(&buf[1], data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = i2c_transfer(priv->i2c, msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret >= 0 && ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_warn(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) KBUILD_MODNAME, ret, i2c_addr, reg, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 addr, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return cxd2841er_write_regs(priv, addr, reg, &tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u8 addr, u8 reg, u8 *val, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 i2c_addr = (addr == I2C_SLVX ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) priv->i2c_addr_slvx : priv->i2c_addr_slvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .addr = i2c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .buf = ®,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .addr = i2c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .buf = val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = i2c_transfer(priv->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ret >= 0 && ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev_warn(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) KBUILD_MODNAME, ret, i2c_addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u8 addr, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return cxd2841er_read_regs(priv, addr, reg, val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u8 addr, u8 reg, u8 data, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u8 rdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (mask != 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) res = cxd2841er_read_reg(priv, addr, reg, &rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) data = ((data & mask) | (rdata & (mask ^ 0xFF)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return cxd2841er_write_reg(priv, addr, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tmp = (u64) ifhz * 16777216;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) do_div(tmp, ((xtal == SONY_XTAL_24000) ? 48000000 : 41000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return (u32) tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static u32 cxd2841er_calc_iffreq(u32 ifhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return cxd2841er_calc_iffreq_xtal(SONY_XTAL_20500, ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int cxd2841er_get_if_hz(struct cxd2841er_priv *priv, u32 def_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (priv->frontend.ops.tuner_ops.get_if_frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) && (priv->flags & CXD2841ER_AUTO_IFHZ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) priv->frontend.ops.tuner_ops.get_if_frequency(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) &priv->frontend, &hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) hz = def_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int cxd2841er_tuner_set(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (fe->ops.tuner_ops.set_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 symbol_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 reg_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 data[3] = {0, 0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * = ((symbolRateKSps * 2^14) + 500) / 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * = ((symbolRateKSps * 16384) + 500) / 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_err(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "%s(): reg_value is out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) data[0] = (u8)((reg_value >> 16) & 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) data[1] = (u8)((reg_value >> 8) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) data[2] = (u8)(reg_value & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Set SLV-T Bank : 0xAE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u8 system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 system, u32 symbol_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u8 data[4] = { 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (priv->state != STATE_SLEEP_S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) __func__, (int)priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Set demod mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (system == SYS_DVBS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) data[0] = 0x0A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) } else if (system == SYS_DVBS2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) data[0] = 0x0B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) __func__, system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* DVB-S/S2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) data[0] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Enable S/S2 auto detection 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Set SLV-T Bank : 0xAE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Enable S/S2 auto detection 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Enable demod clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Enable ADC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Enable ADC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Enable ADC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Enable ADC 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Set SLV-T Bank : 0xA3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) data[0] = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) data[1] = 0x3B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) data[2] = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) data[3] = 0xC5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Set SLV-T Bank : 0xAB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) data[0] = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) data[1] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) data[2] = 0x0A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) data[3] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) data[0] = 0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) data[1] = 0xCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Set demod parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* disable Hi-Z setting 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* disable Hi-Z setting 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) priv->state = STATE_ACTIVE_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u32 bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u32 bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int cxd2841er_sleep_tc(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (priv->state != STATE_ACTIVE_S &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* disable TS output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (priv->state == STATE_ACTIVE_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return cxd2841er_dvbs2_set_symbol_rate(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) priv, p->symbol_rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) else if (priv->state == STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) switch (priv->system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return cxd2841er_sleep_tc_to_active_t_band(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) priv, p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case SYS_DVBT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return cxd2841er_sleep_tc_to_active_t2_band(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) priv, p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return cxd2841er_sleep_tc_to_active_c_band(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) priv, p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) case SYS_ISDBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) cxd2841er_active_i_to_sleep_tc(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) cxd2841er_sleep_tc_to_shutdown(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) cxd2841er_shutdown_to_sleep_tc(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return cxd2841er_sleep_tc_to_active_i(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) priv, p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) __func__, priv->system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (priv->state != STATE_ACTIVE_S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* disable TS output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* enable Hi-Z setting 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* enable Hi-Z setting 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* disable ADC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* disable ADC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* disable ADC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* disable ADC 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* SADC Bias ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* disable demod clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Set SLV-T Bank : 0xAE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* disable S/S2 auto detection1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* disable S/S2 auto detection2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) priv->state = STATE_SLEEP_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (priv->state != STATE_SLEEP_S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Disable DSQOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Disable DSQIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Disable oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Set demod mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) priv->state = STATE_SHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (priv->state != STATE_SLEEP_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Disable oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* Set demod mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) priv->state = STATE_SHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* disable TS output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* enable Hi-Z setting 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* enable Hi-Z setting 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* disable ADC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* Disable ADC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Disable ADC 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Disable ADC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* Disable RF level monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Disable demod clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) priv->state = STATE_SLEEP_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* disable TS output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* enable Hi-Z setting 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* enable Hi-Z setting 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Cancel DVB-T2 setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* disable ADC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Disable ADC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Disable ADC 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Disable ADC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Disable RF level monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Disable demod clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) priv->state = STATE_SLEEP_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* disable TS output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* enable Hi-Z setting 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* enable Hi-Z setting 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* Cancel DVB-C setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* disable ADC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Disable ADC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* Disable ADC 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Disable ADC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Disable RF level monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Disable demod clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) priv->state = STATE_SLEEP_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* disable TS output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* enable Hi-Z setting 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* enable Hi-Z setting 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* TODO: Cancel demod parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* disable ADC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Disable ADC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* Disable ADC 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* Disable ADC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* Disable RF level monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* Disable demod clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) priv->state = STATE_SLEEP_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (priv->state != STATE_SHUTDOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Clear all demodulator registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* Set demod SW reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) switch (priv->xtal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case SONY_XTAL_20500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case SONY_XTAL_24000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Select demod frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case SONY_XTAL_41000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) __func__, priv->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* Set demod mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* Clear demod SW reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* enable DSQOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* enable DSQIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* TADC Bias On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* SADC Bias On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) priv->state = STATE_SLEEP_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u8 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (priv->state != STATE_SHUTDOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* Clear all demodulator registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* Set demod SW reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Select ADC clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) switch (priv->xtal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case SONY_XTAL_20500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) data = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) case SONY_XTAL_24000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* Select demod frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) data = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) case SONY_XTAL_41000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) data = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* Clear demod SW reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* TADC Bias On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* SADC Bias On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) priv->state = STATE_SLEEP_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* SW Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* Enable TS output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* Set TS parallel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u8 system)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * slave Bank Addr Bit default Name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * <SLV-T> 00h C4h [1:0] 2'b?? OSERCKMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * slave Bank Addr Bit default Name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * <SLV-T> 00h D1h [1:0] 2'b?? OSERDUTYMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * slave Bank Addr Bit default Name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * Disable TS IF Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * slave Bank Addr Bit default Name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * slave Bank Addr Bit default Name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * Enable TS IF Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * slave Bank Addr Bit default Name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (system == SYS_DVBT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* Enable parity period for DVB-T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) } else if (system == SYS_DVBC_ANNEX_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* Enable parity period for DVB-C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u8 chip_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static int cxd2841er_read_status_s(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) u8 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (priv->state != STATE_ACTIVE_S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Set SLV-T Bank : 0xA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * slave Bank Addr Bit Signal name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * <SLV-T> A0h 11h [2] ITSLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) cxd2841er_read_reg(priv, I2C_SLVT, 0x11, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (reg & 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) *status = FE_HAS_SIGNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) | FE_HAS_CARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) | FE_HAS_VITERBI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) | FE_HAS_SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u8 *sync, u8 *tslock, u8 *unlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) u8 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (priv->state != STATE_ACTIVE_TC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (priv->system == SYS_DVBT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* Set SLV-T Bank : 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if ((data & 0x07) == 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) "%s(): invalid hardware state detected\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) *sync = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) *tslock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) *unlock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) *sync = ((data & 0x07) == 0x6 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) *tslock = ((data & 0x20) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) *unlock = ((data & 0x10) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (priv->state != STATE_ACTIVE_TC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if ((data & 0x01) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) *tslock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) *tslock = ((data & 0x20) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) u8 *sync, u8 *tslock, u8 *unlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) u8 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (priv->state != STATE_ACTIVE_TC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* Set SLV-T Bank : 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) "%s(): lock=0x%x\n", __func__, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) *sync = ((data & 0x02) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) *tslock = ((data & 0x01) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) *unlock = ((data & 0x10) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) u8 sync = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) u8 tslock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) u8 unlock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (priv->state == STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ret = cxd2841er_read_status_t_t2(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) priv, &sync, &tslock, &unlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (unlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (sync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) *status = FE_HAS_SIGNAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) FE_HAS_VITERBI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (tslock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) } else if (priv->system == SYS_ISDBT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ret = cxd2841er_read_status_i(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) priv, &sync, &tslock, &unlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (unlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (sync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) *status = FE_HAS_SIGNAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) FE_HAS_VITERBI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (tslock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) } else if (priv->system == SYS_DVBC_ANNEX_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ret = cxd2841er_read_status_c(priv, &tslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (tslock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) *status = FE_HAS_SIGNAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) FE_HAS_VITERBI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) FE_HAS_SYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) int *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) u8 data[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) u8 is_hs_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) s32 cfrl_ctrlval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) s32 temp_div, temp_q, temp_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (priv->state != STATE_ACTIVE_S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * Get High Sampling Rate mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * slave Bank Addr Bit Signal name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * <SLV-T> A0h 10h [0] ITRL_LOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (data[0] & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * slave Bank Addr Bit Signal name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * <SLV-T> A0h 50h [4] IHSMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) is_hs_mode = (data[0] & 0x10 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) "%s(): unable to detect sampling rate mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * slave Bank Addr Bit Signal name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) (((u32)data[1] & 0xFF) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ((u32)data[2] & 0xFF), 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) temp_div = (is_hs_mode ? 1048576 : 1572864);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (cfrl_ctrlval > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) temp_div, &temp_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) temp_div, &temp_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (temp_r >= temp_div / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) temp_q++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (cfrl_ctrlval > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) temp_q *= -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) *offset = temp_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) u32 bandwidth, int *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) u8 data[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (priv->system != SYS_ISDBT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) __func__, priv->system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) *offset = -1 * sign_extend32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ((u32)data[2] << 8) | (u32)data[3], 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) switch (bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) *offset = -1 * ((*offset) * 8/264);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) *offset = -1 * ((*offset) * 8/231);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) *offset = -1 * ((*offset) * 8/198);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) __func__, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) __func__, bandwidth, *offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) u32 bandwidth, int *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) u8 data[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (priv->system != SYS_DVBT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) __func__, priv->system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) *offset = -1 * sign_extend32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ((u32)data[2] << 8) | (u32)data[3], 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) *offset *= (bandwidth / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) *offset /= 235;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) u32 bandwidth, int *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) u8 data[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (priv->system != SYS_DVBT2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) __func__, priv->system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) *offset = -1 * sign_extend32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ((u32)data[2] << 8) | (u32)data[3], 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) switch (bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) case 1712000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) *offset /= 582;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) case 5000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) *offset *= (bandwidth / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) *offset /= 940;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) __func__, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) int *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (priv->system != SYS_DVBC_ANNEX_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) __func__, priv->system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) | (u32)data[1], 13), 16384);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static int cxd2841er_read_packet_errors_c(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct cxd2841er_priv *priv, u32 *penum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) u8 data[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) *penum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (data[2] & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) *penum = ((u32)data[0] << 8) | (u32)data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static int cxd2841er_read_packet_errors_t(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct cxd2841er_priv *priv, u32 *penum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) u8 data[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) *penum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (data[2] & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) *penum = ((u32)data[0] << 8) | (u32)data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static int cxd2841er_read_packet_errors_t2(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct cxd2841er_priv *priv, u32 *penum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) u8 data[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) *penum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (data[0] & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) *penum = ((u32)data[1] << 8) | (u32)data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static int cxd2841er_read_packet_errors_i(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) struct cxd2841er_priv *priv, u32 *penum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) *penum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (!(data[0] & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* Layer A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) *penum = ((u32)data[0] << 8) | (u32)data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* Layer B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) *penum += ((u32)data[0] << 8) | (u32)data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* Layer C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) *penum += ((u32)data[0] << 8) | (u32)data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) u32 *bit_error, u32 *bit_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) u8 data[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) u32 bit_err, period_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (!(data[0] & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) "%s(): no valid BER data\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) bit_err = ((u32)(data[0] & 0x3f) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) ((u32)data[1] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) (u32)data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) period_exp = data[0] & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) "%s(): period_exp(%u) or bit_err(%u) not in range. no valid BER data\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) __func__, period_exp, bit_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) "%s(): period_exp(%u) or bit_err(%u) count=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) __func__, period_exp, bit_err,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ((1 << period_exp) * 204 * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) *bit_error = bit_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) *bit_count = ((1 << period_exp) * 204 * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) u32 *bit_error, u32 *bit_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) u8 data[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) u8 pktnum[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) cxd2841er_freeze_regs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) cxd2841er_unfreeze_regs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (!pktnum[0] && !pktnum[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) "%s(): no valid BER data\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) *bit_error = ((u32)(data[0] & 0x7F) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) ((u32)data[1] << 8) | data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) *bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) __func__, *bit_error, *bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) u32 *bit_error, u32 *bit_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) u8 data[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) /* Set SLV-T Bank : 0xA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * slave Bank Addr Bit Signal name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) * <SLV-T> A0h 35h [0] IFVBER_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (data[0] & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) *bit_error = ((u32)(data[1] & 0x3F) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) ((u32)(data[2] & 0xFF) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) (u32)(data[3] & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) *bit_count = ((u32)(data[8] & 0x3F) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) ((u32)(data[9] & 0xFF) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) (u32)(data[10] & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if ((*bit_count == 0) || (*bit_error > *bit_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) "%s(): invalid bit_error %d, bit_count %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) __func__, *bit_error, *bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) u32 *bit_error, u32 *bit_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) u8 data[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) u32 period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* Set SLV-T Bank : 0xB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) * slave Bank Addr Bit Signal name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * <SLV-T> B2h 30h [0] IFLBER_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (data[0] & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /* Bit error count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) *bit_error = ((u32)(data[1] & 0x0F) << 24) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) ((u32)(data[2] & 0xFF) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) ((u32)(data[3] & 0xFF) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) (u32)(data[4] & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /* Set SLV-T Bank : 0xA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /* Measurement period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) period = (u32)(1 << (data[0] & 0x0F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (period == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) "%s(): period is 0\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (*bit_error > (period * 64800)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) "%s(): invalid bit_err 0x%x period 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) __func__, *bit_error, period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) *bit_count = period * 64800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) "%s(): no data available\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) u32 *bit_error, u32 *bit_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) u8 data[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) u32 period_exp, n_ldpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) "%s(): invalid state %d\n", __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (!(data[0] & 0x10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) "%s(): no valid BER data\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) *bit_error = ((u32)(data[0] & 0x0f) << 24) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) ((u32)data[1] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) ((u32)data[2] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) (u32)data[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) period_exp = data[0] & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (*bit_error > ((1U << period_exp) * n_ldpc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) "%s(): invalid BER value\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) * FIXME: the right thing would be to return bit_error untouched,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) * but, as we don't know the scale returned by the counters, let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) * at least preserver BER = bit_error/bit_count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (period_exp >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) *bit_error *= 3125ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) *bit_count = (1U << period_exp) * (n_ldpc / 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) *bit_error *= 50000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) u32 *bit_error, u32 *bit_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) u32 period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) "%s(): invalid state %d\n", __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (!(data[0] & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) "%s(): no valid BER data\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) *bit_error = ((u32)data[0] << 8) | (u32)data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) * FIXME: the right thing would be to return bit_error untouched,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) * but, as we don't know the scale returned by the counters, let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) * at least preserver BER = bit_error/bit_count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) *bit_count = period / 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) *bit_error *= 78125ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) * Freeze registers: ensure multiple separate register reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) * are from the same snapshot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * un-freeze registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) u8 delsys, u32 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) u8 data[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) u32 res = 0, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) int min_index, max_index, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static const struct cxd2841er_cnr_data *cn_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) cxd2841er_freeze_regs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) /* Set SLV-T Bank : 0xA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) * slave Bank Addr Bit Signal name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) cxd2841er_unfreeze_regs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (data[0] & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) min_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) if (delsys == SYS_DVBS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) cn_data = s_cn_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) max_index = ARRAY_SIZE(s_cn_data) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) cn_data = s2_cn_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) max_index = ARRAY_SIZE(s2_cn_data) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (value >= cn_data[min_index].value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) res = cn_data[min_index].cnr_x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (value <= cn_data[max_index].value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) res = cn_data[max_index].cnr_x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) while ((max_index - min_index) > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) index = (max_index + min_index) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (value == cn_data[index].value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) res = cn_data[index].cnr_x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) } else if (value > cn_data[index].value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) max_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) min_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if ((max_index - min_index) <= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (value == cn_data[max_index].value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) res = cn_data[max_index].cnr_x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) res = cn_data[min_index].cnr_x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) "%s(): no data available\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) *snr = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) static uint32_t sony_log(uint32_t x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) *snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) cxd2841er_freeze_regs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) cxd2841er_unfreeze_regs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (reg == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) "%s(): reg value out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) switch (qam) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) case SONY_DVBC_CONSTELLATION_16QAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) case SONY_DVBC_CONSTELLATION_64QAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) case SONY_DVBC_CONSTELLATION_256QAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) if (reg < 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) reg = 126;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) *snr = -95 * (int32_t)sony_log(reg) + 95941;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) case SONY_DVBC_CONSTELLATION_32QAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) case SONY_DVBC_CONSTELLATION_128QAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (reg < 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) reg = 69;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) *snr = -88 * (int32_t)sony_log(reg) + 86999;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) *snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) "%s(): invalid state %d\n", __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) cxd2841er_freeze_regs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) cxd2841er_unfreeze_regs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) reg = ((u32)data[0] << 8) | (u32)data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if (reg == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) "%s(): reg value out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (reg > 4996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) reg = 4996;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(5350 - reg)) + 285);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) *snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) "%s(): invalid state %d\n", __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) cxd2841er_freeze_regs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) cxd2841er_unfreeze_regs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) reg = ((u32)data[0] << 8) | (u32)data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (reg == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) "%s(): reg value out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (reg > 10876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) reg = 10876;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(12600 - reg)) + 320);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) *snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (priv->state != STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) "%s(): invalid state %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) cxd2841er_freeze_regs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) cxd2841er_unfreeze_regs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) reg = ((u32)data[0] << 8) | (u32)data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) if (reg == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) "%s(): reg value out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) *snr = 10000 * (intlog10(reg) >> 24) - 9031;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) u8 delsys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) cxd2841er_write_reg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) priv, I2C_SLVT, 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) "%s(): AGC value=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) __func__, (((u16)data[0] & 0x0F) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) (u16)(data[1] & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) u8 delsys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) cxd2841er_write_reg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) "%s(): AGC value=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) __func__, (((u16)data[0] & 0x0F) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) (u16)(data[1] & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) u8 delsys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) cxd2841er_write_reg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) priv, I2C_SLVT, 0x00, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) "%s(): AGC value=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) __func__, (((u16)data[0] & 0x0F) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) (u16)(data[1] & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) /* Set SLV-T Bank : 0xA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) * slave Bank Addr Bit Signal name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) static void cxd2841er_read_ber(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) u32 ret, bit_error = 0, bit_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) switch (p->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) case SYS_DVBC_ANNEX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) case SYS_DVBC_ANNEX_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) case SYS_ISDBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) case SYS_DVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) case SYS_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) case SYS_DVBT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) p->post_bit_error.stat[0].uvalue += bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) p->post_bit_count.stat[0].uvalue += bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) s32 strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) switch (p->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) case SYS_DVBT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) strength = cxd2841er_read_agc_gain_t_t2(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) p->delivery_system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) p->strength.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) /* Formula was empirically determinated @ 410 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) break; /* Code moved out of the function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) case SYS_DVBC_ANNEX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) case SYS_DVBC_ANNEX_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) strength = cxd2841er_read_agc_gain_c(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) p->delivery_system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) p->strength.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) * Formula was empirically determinated via linear regression,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) * stream modulated with QAM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) case SYS_ISDBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) p->strength.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) * Formula was empirically determinated via linear regression,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) * using frequencies: 175 MHz, 410 MHz and 800 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) case SYS_DVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) case SYS_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) strength = 65535 - cxd2841er_read_agc_gain_s(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) p->strength.stat[0].scale = FE_SCALE_RELATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) p->strength.stat[0].uvalue = strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static void cxd2841er_read_snr(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) u32 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) switch (p->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) case SYS_DVBC_ANNEX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) case SYS_DVBC_ANNEX_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) ret = cxd2841er_read_snr_c(priv, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) ret = cxd2841er_read_snr_t(priv, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) case SYS_DVBT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) ret = cxd2841er_read_snr_t2(priv, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) case SYS_ISDBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) ret = cxd2841er_read_snr_i(priv, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) case SYS_DVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) case SYS_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) __func__, p->delivery_system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) __func__, (int32_t)tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) p->cnr.stat[0].svalue = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) u32 ucblocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) switch (p->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) case SYS_DVBC_ANNEX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) case SYS_DVBC_ANNEX_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) cxd2841er_read_packet_errors_c(priv, &ucblocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) cxd2841er_read_packet_errors_t(priv, &ucblocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) case SYS_DVBT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) cxd2841er_read_packet_errors_t2(priv, &ucblocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) case SYS_ISDBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) cxd2841er_read_packet_errors_i(priv, &ucblocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) p->block_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) p->block_error.stat[0].uvalue = ucblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) static int cxd2841er_dvbt2_set_profile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) u8 tune_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) u8 seq_not2d_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) switch (profile) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) case DVBT2_PROFILE_BASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) tune_mode = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) /* Set early unlock time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) case DVBT2_PROFILE_LITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) tune_mode = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) /* Set early unlock time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) case DVBT2_PROFILE_ANY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) tune_mode = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) /* Set early unlock time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) /* Set SLV-T Bank : 0x2E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) /* Set profile and tune mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) /* Set SLV-T Bank : 0x2B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /* Set early unlock detection time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) u8 is_auto, u8 plp_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (is_auto) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) "%s() using auto PLP selection\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) "%s() using manual PLP selection, ID %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) __func__, plp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) /* Set SLV-T Bank : 0x23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (!is_auto) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) /* Manual PLP selection mode. Set the data PLP Id. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) u32 iffreq, ifhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) u8 data[MAX_WRITE_REGSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) static const uint8_t nominalRate8bw[3][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) /* TRCG Nominal Rate [37:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) static const uint8_t nominalRate7bw[3][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) /* TRCG Nominal Rate [37:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) static const uint8_t nominalRate6bw[3][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) /* TRCG Nominal Rate [37:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) static const uint8_t nominalRate5bw[3][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) /* TRCG Nominal Rate [37:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) static const uint8_t nominalRate17bw[3][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) /* TRCG Nominal Rate [37:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) {0x58, 0xE2, 0xAF, 0xE0, 0xBC} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) static const uint8_t itbCoef8bw[3][14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) 0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static const uint8_t itbCoef7bw[3][14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) 0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) static const uint8_t itbCoef6bw[3][14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) static const uint8_t itbCoef5bw[3][14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) static const uint8_t itbCoef17bw[3][14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) 0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /* Set SLV-T Bank : 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) switch (bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) /* <Timing Recovery setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) 0x9F, nominalRate8bw[priv->xtal], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) /* Set SLV-T Bank : 0x27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) cxd2841er_set_reg_bits(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) 0x7a, 0x00, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) /* Group delay equaliser settings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) * ASCOT2D, ASCOT2E and ASCOT3 tuners
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) 0xA6, itbCoef8bw[priv->xtal], 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) /* <IF freq setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) ifhz = cxd2841er_get_if_hz(priv, 4800000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) data[0] = (u8) ((iffreq >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) data[1] = (u8)((iffreq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) data[2] = (u8)(iffreq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) /* System bandwidth setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) priv, I2C_SLVT, 0xD7, 0x00, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) /* <Timing Recovery setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) 0x9F, nominalRate7bw[priv->xtal], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) /* Set SLV-T Bank : 0x27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) cxd2841er_set_reg_bits(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) 0x7a, 0x00, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /* Group delay equaliser settings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) * ASCOT2D, ASCOT2E and ASCOT3 tuners
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) 0xA6, itbCoef7bw[priv->xtal], 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) /* <IF freq setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) ifhz = cxd2841er_get_if_hz(priv, 4200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) data[0] = (u8) ((iffreq >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) data[1] = (u8)((iffreq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) data[2] = (u8)(iffreq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) /* System bandwidth setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) priv, I2C_SLVT, 0xD7, 0x02, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) /* <Timing Recovery setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) 0x9F, nominalRate6bw[priv->xtal], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) /* Set SLV-T Bank : 0x27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) cxd2841er_set_reg_bits(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) 0x7a, 0x00, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) /* Group delay equaliser settings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) * ASCOT2D, ASCOT2E and ASCOT3 tuners
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) 0xA6, itbCoef6bw[priv->xtal], 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) /* <IF freq setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) ifhz = cxd2841er_get_if_hz(priv, 3600000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) data[0] = (u8) ((iffreq >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) data[1] = (u8)((iffreq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) data[2] = (u8)(iffreq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) /* System bandwidth setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) priv, I2C_SLVT, 0xD7, 0x04, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) case 5000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) /* <Timing Recovery setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) 0x9F, nominalRate5bw[priv->xtal], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) /* Set SLV-T Bank : 0x27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) cxd2841er_set_reg_bits(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) 0x7a, 0x00, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) /* Group delay equaliser settings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) * ASCOT2D, ASCOT2E and ASCOT3 tuners
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) 0xA6, itbCoef5bw[priv->xtal], 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) /* <IF freq setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) ifhz = cxd2841er_get_if_hz(priv, 3600000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) data[0] = (u8) ((iffreq >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) data[1] = (u8)((iffreq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) data[2] = (u8)(iffreq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) /* System bandwidth setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) priv, I2C_SLVT, 0xD7, 0x06, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) case 1712000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) /* <Timing Recovery setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) 0x9F, nominalRate17bw[priv->xtal], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) /* Set SLV-T Bank : 0x27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) cxd2841er_set_reg_bits(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) 0x7a, 0x03, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) /* Group delay equaliser settings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) * ASCOT2D, ASCOT2E and ASCOT3 tuners
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) 0xA6, itbCoef17bw[priv->xtal], 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) /* <IF freq setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) ifhz = cxd2841er_get_if_hz(priv, 3500000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) data[0] = (u8) ((iffreq >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) data[1] = (u8)((iffreq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) data[2] = (u8)(iffreq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) /* System bandwidth setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) priv, I2C_SLVT, 0xD7, 0x03, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) static int cxd2841er_sleep_tc_to_active_t_band(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) struct cxd2841er_priv *priv, u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) u8 data[MAX_WRITE_REGSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) u32 iffreq, ifhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) static const u8 nominalRate8bw[3][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) /* TRCG Nominal Rate [37:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) static const u8 nominalRate7bw[3][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) /* TRCG Nominal Rate [37:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) static const u8 nominalRate6bw[3][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) /* TRCG Nominal Rate [37:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) static const u8 nominalRate5bw[3][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) /* TRCG Nominal Rate [37:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) static const u8 itbCoef8bw[3][14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) static const u8 itbCoef7bw[3][14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) static const u8 itbCoef6bw[3][14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) static const u8 itbCoef5bw[3][14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) /* Set SLV-T Bank : 0x13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) /* Echo performance optimization setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) data[0] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) data[1] = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) switch (bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) /* <Timing Recovery setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) 0x9F, nominalRate8bw[priv->xtal], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) /* Group delay equaliser settings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) * ASCOT2D, ASCOT2E and ASCOT3 tuners
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) 0xA6, itbCoef8bw[priv->xtal], 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) /* <IF freq setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) ifhz = cxd2841er_get_if_hz(priv, 4800000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) data[0] = (u8) ((iffreq >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) data[1] = (u8)((iffreq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) data[2] = (u8)(iffreq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) /* System bandwidth setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) priv, I2C_SLVT, 0xD7, 0x00, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) /* Demod core latency setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) if (priv->xtal == SONY_XTAL_24000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) data[0] = 0x15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) data[1] = 0x28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) data[0] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) data[1] = 0xE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) /* Notch filter setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) data[0] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) data[1] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) /* <Timing Recovery setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) 0x9F, nominalRate7bw[priv->xtal], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) /* Group delay equaliser settings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) * ASCOT2D, ASCOT2E and ASCOT3 tuners
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) 0xA6, itbCoef7bw[priv->xtal], 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) /* <IF freq setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) ifhz = cxd2841er_get_if_hz(priv, 4200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) data[0] = (u8) ((iffreq >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) data[1] = (u8)((iffreq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) data[2] = (u8)(iffreq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* System bandwidth setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) priv, I2C_SLVT, 0xD7, 0x02, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) /* Demod core latency setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) if (priv->xtal == SONY_XTAL_24000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) data[0] = 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) data[1] = 0xF8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) data[0] = 0x12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) data[1] = 0xF8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) /* Notch filter setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) data[0] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) data[1] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) /* <Timing Recovery setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) 0x9F, nominalRate6bw[priv->xtal], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) /* Group delay equaliser settings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) * ASCOT2D, ASCOT2E and ASCOT3 tuners
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) 0xA6, itbCoef6bw[priv->xtal], 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) /* <IF freq setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) ifhz = cxd2841er_get_if_hz(priv, 3600000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) data[0] = (u8) ((iffreq >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) data[1] = (u8)((iffreq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) data[2] = (u8)(iffreq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) /* System bandwidth setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) priv, I2C_SLVT, 0xD7, 0x04, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) /* Demod core latency setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) if (priv->xtal == SONY_XTAL_24000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) data[0] = 0x25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) data[1] = 0x4C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) data[0] = 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) data[1] = 0xDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) /* Notch filter setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) data[0] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) data[1] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) case 5000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) /* <Timing Recovery setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) 0x9F, nominalRate5bw[priv->xtal], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) /* Group delay equaliser settings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) * ASCOT2D, ASCOT2E and ASCOT3 tuners
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) 0xA6, itbCoef5bw[priv->xtal], 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) /* <IF freq setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) ifhz = cxd2841er_get_if_hz(priv, 3600000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) data[0] = (u8) ((iffreq >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) data[1] = (u8)((iffreq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) data[2] = (u8)(iffreq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) /* System bandwidth setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) priv, I2C_SLVT, 0xD7, 0x06, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) /* Demod core latency setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) if (priv->xtal == SONY_XTAL_24000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) data[0] = 0x2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) data[1] = 0xC2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) data[0] = 0x26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) data[1] = 0x3C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) /* Notch filter setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) data[0] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) data[1] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) static int cxd2841er_sleep_tc_to_active_i_band(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) struct cxd2841er_priv *priv, u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) u32 iffreq, ifhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) u8 data[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) /* TRCG Nominal Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) static const u8 nominalRate8bw[3][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static const u8 nominalRate7bw[3][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) static const u8 nominalRate6bw[3][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) static const u8 itbCoef8bw[3][14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) {0x00}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) {0x0}, /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) static const u8 itbCoef7bw[3][14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) {0x00}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) {0x00}, /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) static const u8 itbCoef6bw[3][14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) /* 20.5/41MHz Xtal support is not available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) * on ISDB-T 7MHzBW and 8MHzBW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) dev_err(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) "%s(): bandwidth %d supported only for 24MHz xtal\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) __func__, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) switch (bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) /* TRCG Nominal Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) 0x9F, nominalRate8bw[priv->xtal], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) /* Group delay equaliser settings for ASCOT tuners optimized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) 0xA6, itbCoef8bw[priv->xtal], 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) /* IF freq setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) ifhz = cxd2841er_get_if_hz(priv, 4750000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) data[0] = (u8) ((iffreq >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) data[1] = (u8)((iffreq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) data[2] = (u8)(iffreq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) /* System bandwidth setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) /* Demod core latency setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) data[0] = 0x13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) data[1] = 0xFC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) /* Acquisition optimization setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) /* TRCG Nominal Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) 0x9F, nominalRate7bw[priv->xtal], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) /* Group delay equaliser settings for ASCOT tuners optimized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) 0xA6, itbCoef7bw[priv->xtal], 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) /* IF freq setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) ifhz = cxd2841er_get_if_hz(priv, 4150000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) data[0] = (u8) ((iffreq >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) data[1] = (u8)((iffreq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) data[2] = (u8)(iffreq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) /* System bandwidth setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) /* Demod core latency setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) data[0] = 0x1A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) data[1] = 0xFA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) /* Acquisition optimization setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) /* TRCG Nominal Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) 0x9F, nominalRate6bw[priv->xtal], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) /* Group delay equaliser settings for ASCOT tuners optimized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) cxd2841er_write_regs(priv, I2C_SLVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) 0xA6, itbCoef6bw[priv->xtal], 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) /* IF freq setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) ifhz = cxd2841er_get_if_hz(priv, 3550000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) data[0] = (u8) ((iffreq >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) data[1] = (u8)((iffreq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) data[2] = (u8)(iffreq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) /* System bandwidth setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) /* Demod core latency setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) if (priv->xtal == SONY_XTAL_24000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) data[0] = 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) data[1] = 0x79;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) data[0] = 0x1A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) data[1] = 0xE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) /* Acquisition optimization setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) __func__, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) u8 bw7_8mhz_b10_a6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) u8 bw6mhz_b10_a6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) u8 b10_b6[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) u32 iffreq, ifhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) if (bandwidth != 6000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) bandwidth != 7000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) bandwidth != 8000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) __func__, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) bandwidth = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) switch (bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) cxd2841er_write_regs(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) priv, I2C_SLVT, 0xa6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) ifhz = cxd2841er_get_if_hz(priv, 4900000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) iffreq = cxd2841er_calc_iffreq(ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) if (priv->flags & CXD2841ER_ASCOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) cxd2841er_write_regs(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) priv, I2C_SLVT, 0xa6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) ifhz = cxd2841er_get_if_hz(priv, 3700000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) iffreq = cxd2841er_calc_iffreq(ifhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) __func__, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) /* <IF freq setting> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) b10_b6[2] = (u8)(iffreq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) /* Set SLV-T Bank : 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) switch (bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) /* Set SLV-T Bank : 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) switch (bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) priv, I2C_SLVT, 0x26, 0x09, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) priv, I2C_SLVT, 0x26, 0x08, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) u8 data[2] = { 0x09, 0x54 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) u8 data24m[3] = {0xDC, 0x6C, 0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) /* Set demod mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) /* Enable demod clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) /* Disable RF level monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) /* Enable ADC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) /* Enable ADC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) /* Enable ADC 2 & 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) if (priv->xtal == SONY_XTAL_41000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) data[0] = 0x0A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) data[1] = 0xD4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) /* Enable ADC 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) /* IFAGC gain settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) /* Set SLV-T Bank : 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) /* BBAGC TARGET level setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) /* ASCOT setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) /* Set SLV-T Bank : 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) /* Pre-RS BER monitor setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) /* FEC Auto Recovery setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) /* TSIF setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) if (priv->xtal == SONY_XTAL_24000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) /* Disable HiZ Setting 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) /* Disable HiZ Setting 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) priv->state = STATE_ACTIVE_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) u8 data[MAX_WRITE_REGSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) /* Set demod mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) /* Enable demod clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) /* Disable RF level monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) /* Enable ADC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) /* Enable ADC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) if (priv->xtal == SONY_XTAL_41000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) data[0] = 0x0A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) data[1] = 0xD4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) data[0] = 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) data[1] = 0x54;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) /* Enable ADC 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) /* IFAGC gain settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) /* Set SLV-T Bank : 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) /* BBAGC TARGET level setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) /* ASCOT setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) /* Set SLV-T Bank : 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) /* Acquisition optimization setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) /* Set SLV-T Bank : 0x2b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) /* Set SLV-T Bank : 0x23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) /* L1 Control setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) /* TSIF setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) /* DVB-T2 initial setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) /* Set SLV-T Bank : 0x2a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) /* Set SLV-T Bank : 0x2b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) /* 24MHz Xtal setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) if (priv->xtal == SONY_XTAL_24000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) /* Set SLV-T Bank : 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) data[0] = 0xEB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) data[1] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) data[2] = 0x3B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) /* Set SLV-T Bank : 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) data[0] = 0x5E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) data[1] = 0x5E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) data[2] = 0x47;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) data[0] = 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) data[1] = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) /* Set SLV-T Bank : 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) data[0] = 0x0B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) data[1] = 0x72;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) data[0] = 0x93;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) data[1] = 0xF3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) data[2] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) data[0] = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) data[1] = 0xB8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) data[2] = 0xD8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) /* Set SLV-T Bank : 0x25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) /* Set SLV-T Bank : 0x27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) /* Set SLV-T Bank : 0x2B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) /* Set SLV-T Bank : 0x2D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) data[0] = 0x89;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) data[1] = 0x89;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) /* Set SLV-T Bank : 0x5E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) data[0] = 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) data[1] = 0x95;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) /* Disable HiZ Setting 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) /* Disable HiZ Setting 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) priv->state = STATE_ACTIVE_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) /* ISDB-Tb part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) u8 data[2] = { 0x09, 0x54 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) u8 data24m[2] = {0x60, 0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) u8 data24m2[3] = {0xB7, 0x1B, 0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) /* Set demod mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) /* Enable demod clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) /* Enable RF level monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) /* Enable ADC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) /* Enable ADC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) /* xtal freq 20.5MHz or 24M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) /* Enable ADC 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) /* ASCOT setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) /* FEC Auto Recovery setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) /* ISDB-T initial setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) /* Set SLV-T Bank : 0x15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) /* Set SLV-T Bank : 0x1E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) /* Set SLV-T Bank : 0x63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) /* for xtal 24MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) /* Set SLV-T Bank : 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) /* Disable HiZ Setting 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) /* Disable HiZ Setting 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) priv->state = STATE_ACTIVE_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) u8 data[2] = { 0x09, 0x54 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) /* Set SLV-X Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) /* Set demod mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) /* Enable demod clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) /* Disable RF level monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) /* Enable ADC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) /* Enable ADC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) /* xtal freq 20.5MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) /* Enable ADC 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) /* IFAGC gain settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) /* Set SLV-T Bank : 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) /* BBAGC TARGET level setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) /* Set SLV-T Bank : 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) /* ASCOT setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) /* Set SLV-T Bank : 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) /* Demod setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) /* TSIF setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) /* Set SLV-T Bank : 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) /* Disable HiZ Setting 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) /* Disable HiZ Setting 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) priv->state = STATE_ACTIVE_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) static int cxd2841er_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) enum fe_status status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) if (priv->state == STATE_ACTIVE_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) cxd2841er_read_status_s(fe, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) else if (priv->state == STATE_ACTIVE_TC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) cxd2841er_read_status_tc(fe, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) if (priv->state == STATE_ACTIVE_TC || priv->state == STATE_ACTIVE_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) cxd2841er_read_signal_strength(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) if (status & FE_HAS_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) if (priv->stats_time &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) (!time_after(jiffies, priv->stats_time)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) /* Prevent retrieving stats faster than once per second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) priv->stats_time = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) cxd2841er_read_snr(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) cxd2841er_read_ucblocks(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) cxd2841er_read_ber(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) int ret = 0, i, timeout, carr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) enum fe_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) u32 symbol_rate = p->symbol_rate/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) p->frequency, symbol_rate, priv->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) if (priv->flags & CXD2841ER_EARLY_TUNE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) cxd2841er_tuner_set(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) switch (priv->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) case STATE_SLEEP_S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) ret = cxd2841er_sleep_s_to_active_s(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) priv, p->delivery_system, symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) case STATE_ACTIVE_S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) ret = cxd2841er_retune_active(priv, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) if (!(priv->flags & CXD2841ER_EARLY_TUNE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) cxd2841er_tuner_set(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) cxd2841er_tune_done(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) cxd2841er_read_status_s(fe, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) if (status & FE_HAS_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) } while (i < timeout / CXD2841ER_DVBS_POLLING_INVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) if (status & FE_HAS_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) if (cxd2841er_get_carrier_offset_s_s2(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) priv, &carr_offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) __func__, carr_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) /* Reset stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) p->strength.stat[0].scale = FE_SCALE_RELATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) /* Reset the wait for jiffies logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) priv->stats_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) int ret = 0, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) enum fe_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) __func__, p->delivery_system, p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) if (priv->flags & CXD2841ER_EARLY_TUNE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) cxd2841er_tuner_set(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) /* deconfigure/put demod to sleep on delsys switch if active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) if (priv->state == STATE_ACTIVE_TC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) priv->system != p->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) dev_dbg(&priv->i2c->dev, "%s(): old_delsys=%d, new_delsys=%d -> sleep\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) __func__, priv->system, p->delivery_system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) cxd2841er_sleep_tc(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) if (p->delivery_system == SYS_DVBT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) priv->system = SYS_DVBT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) switch (priv->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) case STATE_SLEEP_TC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) ret = cxd2841er_sleep_tc_to_active_t(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) priv, p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) case STATE_ACTIVE_TC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) ret = cxd2841er_retune_active(priv, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) } else if (p->delivery_system == SYS_DVBT2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) priv->system = SYS_DVBT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) cxd2841er_dvbt2_set_plp_config(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) (int)(p->stream_id > 255), p->stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) switch (priv->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) case STATE_SLEEP_TC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) ret = cxd2841er_sleep_tc_to_active_t2(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) case STATE_ACTIVE_TC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) ret = cxd2841er_retune_active(priv, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) } else if (p->delivery_system == SYS_ISDBT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) priv->system = SYS_ISDBT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) switch (priv->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) case STATE_SLEEP_TC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) ret = cxd2841er_sleep_tc_to_active_i(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) priv, p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) case STATE_ACTIVE_TC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) ret = cxd2841er_retune_active(priv, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) p->delivery_system == SYS_DVBC_ANNEX_C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) priv->system = SYS_DVBC_ANNEX_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) /* correct bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) if (p->bandwidth_hz != 6000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) p->bandwidth_hz != 7000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) p->bandwidth_hz != 8000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) p->bandwidth_hz = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) __func__, p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) switch (priv->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) case STATE_SLEEP_TC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) ret = cxd2841er_sleep_tc_to_active_c(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) priv, p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) case STATE_ACTIVE_TC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) ret = cxd2841er_retune_active(priv, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) "%s(): invalid delivery system %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) __func__, p->delivery_system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) if (!(priv->flags & CXD2841ER_EARLY_TUNE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) cxd2841er_tuner_set(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) cxd2841er_tune_done(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) if (priv->flags & CXD2841ER_NO_WAIT_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) timeout = 2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) while (timeout > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) ret = cxd2841er_read_status_tc(fe, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) if (status & FE_HAS_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) timeout -= 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) if (timeout < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) "%s(): LOCK wait timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) static int cxd2841er_tune_s(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) bool re_tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) unsigned int mode_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) unsigned int *delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) int ret, carrier_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) if (re_tune) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) ret = cxd2841er_set_frontend_s(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) cxd2841er_read_status_s(fe, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) if (*status & FE_HAS_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) if (cxd2841er_get_carrier_offset_s_s2(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) priv, &carrier_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) p->frequency += carrier_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) ret = cxd2841er_set_frontend_s(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) *delay = HZ / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) return cxd2841er_read_status_s(fe, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) static int cxd2841er_tune_tc(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) bool re_tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) unsigned int mode_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) unsigned int *delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) int ret, carrier_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) re_tune, p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) if (re_tune) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) ret = cxd2841er_set_frontend_tc(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) cxd2841er_read_status_tc(fe, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) if (*status & FE_HAS_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) switch (priv->system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) case SYS_ISDBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) ret = cxd2841er_get_carrier_offset_i(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) priv, p->bandwidth_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) &carrier_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) ret = cxd2841er_get_carrier_offset_t(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) priv, p->bandwidth_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) &carrier_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) case SYS_DVBT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) ret = cxd2841er_get_carrier_offset_t2(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) priv, p->bandwidth_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) &carrier_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) ret = cxd2841er_get_carrier_offset_c(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) priv, &carrier_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) "%s(): invalid delivery system %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) __func__, priv->system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) __func__, carrier_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) p->frequency += carrier_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) ret = cxd2841er_set_frontend_tc(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) *delay = HZ / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) return cxd2841er_read_status_tc(fe, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) static int cxd2841er_sleep_s(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) if (priv->state == STATE_ACTIVE_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) switch (priv->system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) cxd2841er_active_t_to_sleep_tc(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) case SYS_DVBT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) cxd2841er_active_t2_to_sleep_tc(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) case SYS_ISDBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) cxd2841er_active_i_to_sleep_tc(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) cxd2841er_active_c_to_sleep_tc(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) dev_warn(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) "%s(): unknown delivery system %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) __func__, priv->system);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) if (priv->state != STATE_SLEEP_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) static int cxd2841er_shutdown_tc(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) if (!cxd2841er_sleep_tc(fe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) cxd2841er_sleep_tc_to_shutdown(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) static int cxd2841er_send_burst(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) enum fe_sec_mini_cmd burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) (burst == SEC_MINI_A ? "A" : "B"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) if (priv->state != STATE_SLEEP_S &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) priv->state != STATE_ACTIVE_S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) data = (burst == SEC_MINI_A ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) static int cxd2841er_set_tone(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) enum fe_sec_tone_mode tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) (tone == SEC_TONE_ON ? "On" : "Off"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) if (priv->state != STATE_SLEEP_S &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) priv->state != STATE_ACTIVE_S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) data = (tone == SEC_TONE_ON ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) struct dvb_diseqc_master_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) u8 data[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) if (priv->state != STATE_SLEEP_S &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) priv->state != STATE_ACTIVE_S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) __func__, priv->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) "%s(): cmd->len %d\n", __func__, cmd->msg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) /* DiDEqC enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) /* cmd1 length & data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) memset(data, 0, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) data[i] = cmd->msg[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) /* repeat count for cmd1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) /* repeat count for cmd2: always 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) /* start transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) /* wait for 1 sec timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) for (i = 0; i < 50; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) if (!data[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) "%s(): DiSEqC cmd has been sent\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) dev_dbg(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) "%s(): DiSEqC cmd transmit timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) static void cxd2841er_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) cxd2841er_set_reg_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) return DVBFE_ALGO_HW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) static void cxd2841er_init_stats(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) p->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) p->strength.stat[0].scale = FE_SCALE_RELATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) p->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) p->block_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) p->post_bit_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) p->post_bit_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) static int cxd2841er_init_s(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) /* sanity. force demod to SHUTDOWN state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) if (priv->state == STATE_SLEEP_S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) cxd2841er_sleep_s_to_shutdown(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) } else if (priv->state == STATE_ACTIVE_S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) cxd2841er_active_s_to_sleep_s(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) cxd2841er_sleep_s_to_shutdown(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) cxd2841er_shutdown_to_sleep_s(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) cxd2841er_init_stats(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) static int cxd2841er_init_tc(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) struct cxd2841er_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) __func__, p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) cxd2841er_shutdown_to_sleep_tc(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 (0 for NO_AGCNEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) ((priv->flags & CXD2841ER_NO_AGCNEG) ? 0x00 : 0x40), 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) /* clear TSCFG bits 3+4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) if (priv->flags & CXD2841ER_TSBITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) cxd2841er_init_stats(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) static struct dvb_frontend_ops cxd2841er_t_c_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) u8 system)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) u8 chip_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) const char *type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) struct cxd2841er_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) priv->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) priv->config = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) priv->xtal = cfg->xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) priv->flags = cfg->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) priv->frontend.demodulator_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) dev_info(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) __func__, priv->i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) priv->i2c_addr_slvx, priv->i2c_addr_slvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) chip_id = cxd2841er_chip_id(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) switch (chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) case CXD2837ER_CHIP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) snprintf(cxd2841er_t_c_ops.info.name, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) "Sony CXD2837ER DVB-T/T2/C demodulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) name = "CXD2837ER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) type = "C/T/T2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) case CXD2838ER_CHIP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) snprintf(cxd2841er_t_c_ops.info.name, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) "Sony CXD2838ER ISDB-T demodulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) cxd2841er_t_c_ops.delsys[0] = SYS_ISDBT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) cxd2841er_t_c_ops.delsys[1] = SYS_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) cxd2841er_t_c_ops.delsys[2] = SYS_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) name = "CXD2838ER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) type = "ISDB-T";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) case CXD2841ER_CHIP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) snprintf(cxd2841er_t_c_ops.info.name, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) "Sony CXD2841ER DVB-T/T2/C demodulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) name = "CXD2841ER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) type = "T/T2/C/ISDB-T";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) case CXD2843ER_CHIP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) snprintf(cxd2841er_t_c_ops.info.name, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) "Sony CXD2843ER DVB-T/T2/C/C2 demodulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) name = "CXD2843ER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) type = "C/C2/T/T2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) case CXD2854ER_CHIP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) snprintf(cxd2841er_t_c_ops.info.name, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) name = "CXD2854ER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) type = "C/C2/T/T2/ISDB-T";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) __func__, chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) priv->frontend.demodulator_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) if (system == SYS_DVBS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) memcpy(&priv->frontend.ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) &cxd2841er_dvbs_s2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) type = "S/S2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) memcpy(&priv->frontend.ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) &cxd2841er_t_c_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) dev_info(&priv->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) "%s(): attaching %s DVB-%s frontend\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) __func__, name, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) __func__, chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) return &priv->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) return cxd2841er_attach(cfg, i2c, SYS_DVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) EXPORT_SYMBOL(cxd2841er_attach_s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) return cxd2841er_attach(cfg, i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) EXPORT_SYMBOL(cxd2841er_attach_t_c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) .delsys = { SYS_DVBS, SYS_DVBS2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) .name = "Sony CXD2841ER DVB-S/S2 demodulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) .frequency_min_hz = 500 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) .frequency_max_hz = 2500 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) .symbol_rate_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) .symbol_rate_max = 45000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) .symbol_rate_tolerance = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) .caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) FE_CAN_QPSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) .init = cxd2841er_init_s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) .sleep = cxd2841er_sleep_s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) .release = cxd2841er_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) .set_frontend = cxd2841er_set_frontend_s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) .get_frontend = cxd2841er_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) .read_status = cxd2841er_read_status_s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) .get_frontend_algo = cxd2841er_get_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) .set_tone = cxd2841er_set_tone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) .diseqc_send_burst = cxd2841er_send_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) .tune = cxd2841er_tune_s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) static struct dvb_frontend_ops cxd2841er_t_c_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) .name = "", /* will set in attach function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) .caps = FE_CAN_FEC_1_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) FE_CAN_FEC_2_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) FE_CAN_FEC_5_6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) FE_CAN_FEC_7_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) FE_CAN_QPSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) FE_CAN_QAM_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) FE_CAN_QAM_32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) FE_CAN_QAM_128 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) FE_CAN_QAM_256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) FE_CAN_TRANSMISSION_MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) FE_CAN_GUARD_INTERVAL_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) FE_CAN_HIERARCHY_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) FE_CAN_MUTE_TS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) FE_CAN_2G_MODULATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) .frequency_min_hz = 42 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) .frequency_max_hz = 1002 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) .symbol_rate_min = 870000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) .symbol_rate_max = 11700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) .init = cxd2841er_init_tc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) .sleep = cxd2841er_shutdown_tc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) .release = cxd2841er_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) .set_frontend = cxd2841er_set_frontend_tc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) .get_frontend = cxd2841er_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) .read_status = cxd2841er_read_status_tc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) .tune = cxd2841er_tune_tc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) .get_frontend_algo = cxd2841er_get_algo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) MODULE_DESCRIPTION("Sony CXD2837/38/41/43/54ER DVB-C/C2/T/T2/S/S2 demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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