^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Sony CXD2820R demodulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "cxd2820r_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) int cxd2820r_set_frontend_t2(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct cxd2820r_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct i2c_client *client = priv->client[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) int ret, bw_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 if_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u8 buf[3], bw_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 bw_params1[][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { 0x1c, 0xb3, 0x33, 0x33, 0x33 }, /* 5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct reg_val_mask tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { 0x00080, 0x02, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { 0x00081, 0x20, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { 0x00085, 0x07, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { 0x00088, 0x01, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { 0x02069, 0x01, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { 0x0207f, 0x2a, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { 0x02082, 0x0a, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { 0x02083, 0x0a, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { 0x020cb, priv->if_agc_polarity << 6, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { 0x02070, priv->ts_mode, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { 0x02071, !priv->ts_clk_inv << 6, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { 0x020b5, priv->spec_inv << 4, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { 0x02567, 0x07, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { 0x02569, 0x03, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { 0x02595, 0x1a, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { 0x02596, 0x50, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { 0x02a8c, 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { 0x02a8d, 0x34, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { 0x02a45, 0x06, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { 0x03f10, 0x0d, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { 0x03f11, 0x02, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { 0x03f12, 0x01, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { 0x03f23, 0x2c, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { 0x03f51, 0x13, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { 0x03f52, 0x01, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { 0x03f53, 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 0x027e6, 0x14, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { 0x02786, 0x02, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { 0x02787, 0x40, 0xe0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { 0x027ef, 0x10, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "delivery_system=%d modulation=%d frequency=%u bandwidth_hz=%u inversion=%d stream_id=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) c->delivery_system, c->modulation, c->frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) c->bandwidth_hz, c->inversion, c->stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) switch (c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case 5000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bw_i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bw_param = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) bw_i = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) bw_param = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) bw_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bw_param = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bw_i = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) bw_param = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* program tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (fe->ops.tuner_ops.set_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (priv->delivery_system != SYS_DVBT2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) priv->delivery_system = SYS_DVBT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* program IF frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (fe->ops.tuner_ops.get_if_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, CXD2820R_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) buf[0] = (utmp >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) buf[1] = (utmp >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) buf[2] = (utmp >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = regmap_bulk_write(priv->regmap[0], 0x20b6, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* PLP filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (c->stream_id > 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dev_dbg(&client->dev, "disable PLP filtering\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = regmap_write(priv->regmap[0], 0x23ad, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev_dbg(&client->dev, "enable PLP filtering\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = regmap_write(priv->regmap[0], 0x23af, c->stream_id & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = regmap_write(priv->regmap[0], 0x23ad, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ret = regmap_bulk_write(priv->regmap[0], 0x209f, bw_params1[bw_i], 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = regmap_update_bits(priv->regmap[0], 0x20d7, 0xc0, bw_param << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret = regmap_write(priv->regmap[0], 0x00ff, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = regmap_write(priv->regmap[0], 0x00fe, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int cxd2820r_get_frontend_t2(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct dtv_frontend_properties *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct cxd2820r_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct i2c_client *client = priv->client[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = regmap_bulk_read(priv->regmap[0], 0x205c, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) switch ((buf[0] >> 0) & 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) c->transmission_mode = TRANSMISSION_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) c->transmission_mode = TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) c->transmission_mode = TRANSMISSION_MODE_4K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) c->transmission_mode = TRANSMISSION_MODE_1K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) c->transmission_mode = TRANSMISSION_MODE_16K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) c->transmission_mode = TRANSMISSION_MODE_32K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) switch ((buf[1] >> 4) & 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) c->guard_interval = GUARD_INTERVAL_1_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) c->guard_interval = GUARD_INTERVAL_1_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) c->guard_interval = GUARD_INTERVAL_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) c->guard_interval = GUARD_INTERVAL_1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) c->guard_interval = GUARD_INTERVAL_1_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) c->guard_interval = GUARD_INTERVAL_19_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) c->guard_interval = GUARD_INTERVAL_19_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = regmap_bulk_read(priv->regmap[0], 0x225b, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) switch ((buf[0] >> 0) & 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) c->fec_inner = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) c->fec_inner = FEC_3_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) c->fec_inner = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) c->fec_inner = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) c->fec_inner = FEC_4_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) c->fec_inner = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) switch ((buf[1] >> 0) & 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) c->modulation = QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) c->modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) c->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) c->modulation = QAM_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = regmap_read(priv->regmap[0], 0x20b5, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) switch ((utmp >> 4) & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) c->inversion = INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) c->inversion = INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int cxd2820r_read_status_t2(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct cxd2820r_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct i2c_client *client = priv->client[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned int utmp, utmp1, utmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Lock detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = regmap_bulk_read(priv->regmap[0], 0x2010, &buf[0], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) utmp1 = (buf[0] >> 0) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) utmp2 = (buf[0] >> 5) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (utmp1 == 6 && utmp2 == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else if (utmp1 == 6 || utmp2 == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) FE_HAS_VITERBI | FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) *status, 1, buf, utmp1, utmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Signal strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (*status & FE_HAS_SIGNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned int strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = regmap_bulk_read(priv->regmap[0], 0x2026, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) utmp = buf[0] << 8 | buf[1] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) utmp = ~utmp & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Scale value to 0x0000-0xffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) strength = utmp << 4 | utmp >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) c->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) c->strength.stat[0].scale = FE_SCALE_RELATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) c->strength.stat[0].uvalue = strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) c->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* CNR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (*status & FE_HAS_VITERBI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned int cnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ret = regmap_bulk_read(priv->regmap[0], 0x2028, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) utmp = buf[0] << 8 | buf[1] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) utmp = utmp & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (utmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) cnr = div_u64((u64)(intlog10(utmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) - CXD2820R_LOG10_8_24) * 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) (1 << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) cnr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) c->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) c->cnr.stat[0].svalue = cnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) c->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* BER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (*status & FE_HAS_SYNC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int post_bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = regmap_bulk_read(priv->regmap[0], 0x2039, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if ((buf[0] >> 4) & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) post_bit_error = buf[0] << 24 | buf[1] << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) buf[2] << 8 | buf[3] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) post_bit_error &= 0x0fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) post_bit_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) priv->post_bit_error += post_bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) c->post_bit_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) c->post_bit_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int cxd2820r_sleep_t2(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct cxd2820r_priv *priv = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct i2c_client *client = priv->client[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct reg_val_mask tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { 0x000ff, 0x1f, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { 0x00085, 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { 0x00088, 0x01, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { 0x02069, 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { 0x00081, 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { 0x00080, 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) priv->delivery_system = SYS_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct dvb_frontend_tune_settings *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) s->min_delay_ms = 1500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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