^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Support for CX24123/CX24113-NIM by Patrick Boettcher <pb@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "cx24123.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define XTAL 10111000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static int force_band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) module_param(force_band, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MODULE_PARM_DESC(force_band, "Force a specific band select "\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "(1-9, default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define info(args...) do { printk(KERN_INFO "CX24123: " args); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define err(args...) do { printk(KERN_ERR "CX24123: " args); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (debug) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) printk(KERN_DEBUG "CX24123: %s: ", __func__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) printk(args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct cx24123_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) const struct cx24123_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Some PLL specifics for tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 VCAarg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 VGAarg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 bandselectarg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 pllarg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 FILTune;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct i2c_adapter tuner_i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 demod_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* The Demod/Tuner can't easily provide these, we cache them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 currentfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 currentsymbolrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Various tuner defaults need to be established for a given symbol rate Sps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static struct cx24123_AGC_val {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 symbolrate_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 symbolrate_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 VCAprogdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 VGAprogdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 FILTune;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) } cx24123_AGC_vals[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .symbolrate_low = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .symbolrate_high = 4999999,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* the specs recommend other values for VGA offsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) but tests show they are wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .FILTune = 0x27f /* 0.41 V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .symbolrate_low = 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .symbolrate_high = 14999999,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .FILTune = 0x317 /* 0.90 V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .symbolrate_low = 15000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .symbolrate_high = 45000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .FILTune = 0x145 /* 2.70 V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Various tuner defaults need to be established for a given frequency kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * fixme: The bounds on the bands do not match the doc in real life.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * fixme: Some of them have been moved, other might need adjustment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct cx24123_bandselect_val {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 freq_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 freq_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 VCOdivider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 progdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) } cx24123_bandselect_vals[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* band 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .freq_low = 950000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .freq_high = 1074999,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .VCOdivider = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .progdata = (0 << 19) | (0 << 9) | 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* band 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .freq_low = 1075000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .freq_high = 1177999,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .VCOdivider = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .progdata = (0 << 19) | (0 << 9) | 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* band 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .freq_low = 1178000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .freq_high = 1295999,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .VCOdivider = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .progdata = (0 << 19) | (1 << 9) | 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* band 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .freq_low = 1296000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .freq_high = 1431999,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .VCOdivider = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .progdata = (0 << 19) | (1 << 9) | 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* band 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .freq_low = 1432000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .freq_high = 1575999,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .VCOdivider = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .progdata = (0 << 19) | (1 << 9) | 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* band 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .freq_low = 1576000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .freq_high = 1717999,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .VCOdivider = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .progdata = (0 << 19) | (1 << 9) | 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* band 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .freq_low = 1718000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .freq_high = 1855999,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .VCOdivider = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .progdata = (0 << 19) | (1 << 9) | 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* band 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .freq_low = 1856000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .freq_high = 2035999,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .VCOdivider = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .progdata = (0 << 19) | (1 << 9) | 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* band 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .freq_low = 2036000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .freq_high = 2150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .VCOdivider = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .progdata = (0 << 19) | (1 << 9) | 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) } cx24123_regdata[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x00, 0x03}, /* Reset system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x00, 0x00}, /* Clear reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x04, 0x10}, /* MPEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x05, 0x04}, /* MPEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x06, 0x31}, /* MPEG (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x0b, 0x00}, /* Freq search start point (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x0c, 0x00}, /* Demodulator sample gain (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x0f, 0xfe}, /* FEC search mask (all supported codes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x10, 0x01}, /* Default search inversion, no repeat (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x16, 0x00}, /* Enable reading of frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x17, 0x01}, /* Enable EsNO Ready Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x1c, 0x80}, /* Enable error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x29, 0x00}, /* DiSEqC LNB_DC off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x2a, 0xb0}, /* DiSEqC Parameters (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x2d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x2e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x2f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x30, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x31, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x32, 0x8c}, /* DiSEqC Parameters (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x34, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x36, 0x02}, /* DiSEqC Parameters (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x37, 0x3a}, /* DiSEqC Parameters (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x44, 0x00}, /* Constellation (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x45, 0x00}, /* Symbol count (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x46, 0x0d}, /* Symbol rate estimator on (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x56, 0xc1}, /* Error Counter = Viterbi BER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x57, 0xff}, /* Error Counter Window (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x67, 0x83}, /* Non-DCII symbol clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int cx24123_i2c_writereg(struct cx24123_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 i2c_addr, int reg, int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 buf[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* printk(KERN_DEBUG "wr(%02x): %02x %02x\n", i2c_addr, reg, data); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) err = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (err != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) printk("%s: writereg error(err == %i, reg == 0x%02x, data == 0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __func__, err, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int cx24123_i2c_readreg(struct cx24123_state *state, u8 i2c_addr, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &b, .len = 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) err("%s: reg=0x%x (error=%d)\n", __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* printk(KERN_DEBUG "rd(%02x): %02x %02x\n", i2c_addr, reg, b); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define cx24123_readreg(state, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) cx24123_i2c_readreg(state, state->config->demod_address, reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define cx24123_writereg(state, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) cx24123_i2c_writereg(state, state->config->demod_address, reg, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int cx24123_set_inversion(struct cx24123_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) enum fe_spectral_inversion inversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u8 nom_reg = cx24123_readreg(state, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 auto_reg = cx24123_readreg(state, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) switch (inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case INVERSION_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dprintk("inversion off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) cx24123_writereg(state, 0x0e, nom_reg & ~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) cx24123_writereg(state, 0x10, auto_reg | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case INVERSION_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dprintk("inversion on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) cx24123_writereg(state, 0x0e, nom_reg | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) cx24123_writereg(state, 0x10, auto_reg | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case INVERSION_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dprintk("inversion auto\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) cx24123_writereg(state, 0x10, auto_reg & ~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int cx24123_get_inversion(struct cx24123_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) enum fe_spectral_inversion *inversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) val = cx24123_readreg(state, 0x1b) >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (val == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dprintk("read inversion off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *inversion = INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dprintk("read inversion on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *inversion = INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int cx24123_set_fec(struct cx24123_state *state, enum fe_code_rate fec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (((int)fec < FEC_NONE) || (fec > FEC_AUTO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) fec = FEC_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Set the soft decision threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (fec == FEC_1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) cx24123_writereg(state, 0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) cx24123_readreg(state, 0x43) | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) cx24123_writereg(state, 0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) cx24123_readreg(state, 0x43) & ~0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) switch (fec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dprintk("set FEC to 1/2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) cx24123_writereg(state, 0x0e, nom_reg | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) cx24123_writereg(state, 0x0f, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dprintk("set FEC to 2/3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) cx24123_writereg(state, 0x0e, nom_reg | 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cx24123_writereg(state, 0x0f, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dprintk("set FEC to 3/4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) cx24123_writereg(state, 0x0e, nom_reg | 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) cx24123_writereg(state, 0x0f, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case FEC_4_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dprintk("set FEC to 4/5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) cx24123_writereg(state, 0x0e, nom_reg | 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) cx24123_writereg(state, 0x0f, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dprintk("set FEC to 5/6\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) cx24123_writereg(state, 0x0e, nom_reg | 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) cx24123_writereg(state, 0x0f, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case FEC_6_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dprintk("set FEC to 6/7\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cx24123_writereg(state, 0x0e, nom_reg | 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) cx24123_writereg(state, 0x0f, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dprintk("set FEC to 7/8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) cx24123_writereg(state, 0x0e, nom_reg | 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) cx24123_writereg(state, 0x0f, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) case FEC_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dprintk("set FEC to auto\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) cx24123_writereg(state, 0x0f, 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int cx24123_get_fec(struct cx24123_state *state, enum fe_code_rate *fec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = cx24123_readreg(state, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = ret & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) switch (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) *fec = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *fec = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) *fec = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *fec = FEC_4_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *fec = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) *fec = FEC_6_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *fec = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* this can happen when there's no lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) *fec = FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Approximation of closest integer of log2(a/b). It actually gives the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) lowest integer i such that 2^i >= round(a/b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static u32 cx24123_int_log2(u32 a, u32 b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u32 exp, nearest = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 div = a / b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (a % b >= b / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ++div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (div < (1UL << 31)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) for (exp = 1; div > exp; nearest++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) exp += exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return nearest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int cx24123_set_symbolrate(struct cx24123_state *state, u32 srate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 sample_rate, ratio, sample_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u8 pll_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* check if symbol rate is within limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if ((srate > state->frontend.ops.info.symbol_rate_max) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) (srate < state->frontend.ops.info.symbol_rate_min))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* choose the sampling rate high enough for the required operation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) while optimizing the power consumed by the demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (srate < (XTAL*2)/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pll_mult = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) else if (srate < (XTAL*3)/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pll_mult = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) else if (srate < (XTAL*4)/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) pll_mult = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) else if (srate < (XTAL*5)/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pll_mult = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) else if (srate < (XTAL*6)/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pll_mult = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) else if (srate < (XTAL*7)/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pll_mult = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) else if (srate < (XTAL*8)/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pll_mult = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pll_mult = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) sample_rate = pll_mult * XTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* SYSSymbolRate[21:0] = (srate << 23) / sample_rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) tmp = ((u64)srate) << 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) do_div(tmp, sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ratio = (u32) tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) cx24123_writereg(state, 0x01, pll_mult * 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) cx24123_writereg(state, 0x0a, ratio & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* also set the demodulator sample gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) sample_gain = cx24123_int_log2(sample_rate, srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) tmp = cx24123_readreg(state, 0x0c) & ~0xe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) cx24123_writereg(state, 0x0c, tmp | sample_gain << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dprintk("srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) srate, ratio, sample_rate, sample_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * Based on the required frequency and symbolrate, the tuner AGC has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * to be configured and the correct band selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * Calculate those values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int cx24123_pll_calculate(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 ndiv = 0, adiv = 0, vco_div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int pump = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int band = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int num_bands = ARRAY_SIZE(cx24123_bandselect_vals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct cx24123_bandselect_val *bsv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct cx24123_AGC_val *agcv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Defaults for low freq, low rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) state->bandselectarg = cx24123_bandselect_vals[0].progdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) vco_div = cx24123_bandselect_vals[0].VCOdivider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* For the given symbol rate, determine the VCA, VGA and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * FILTUNE programming bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) agcv = &cx24123_AGC_vals[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if ((agcv->symbolrate_low <= p->symbol_rate) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) (agcv->symbolrate_high >= p->symbol_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) state->VCAarg = agcv->VCAprogdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) state->VGAarg = agcv->VGAprogdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) state->FILTune = agcv->FILTune;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* determine the band to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (force_band < 1 || force_band > num_bands) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) for (i = 0; i < num_bands; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) bsv = &cx24123_bandselect_vals[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if ((bsv->freq_low <= p->frequency) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) (bsv->freq_high >= p->frequency))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) band = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) band = force_band - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) state->bandselectarg = cx24123_bandselect_vals[band].progdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) vco_div = cx24123_bandselect_vals[band].VCOdivider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* determine the charge pump current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (p->frequency < (cx24123_bandselect_vals[band].freq_low +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cx24123_bandselect_vals[band].freq_high) / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) pump = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pump = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Determine the N/A dividers for the requested lband freq (in kHz). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Note: the reference divider R=10, frequency is in KHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * XTAL is in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ndiv = (((p->frequency * vco_div * 10) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) (2 * XTAL / 1000)) / 32) & 0x1ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) adiv = (((p->frequency * vco_div * 10) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) (2 * XTAL / 1000)) % 32) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (adiv == 0 && ndiv > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ndiv--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* control bits 11, refdiv 11, charge pump polarity 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * charge pump current, ndiv, adiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) (pump << 14) | (ndiv << 5) | adiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * Tuner data is 21 bits long, must be left-aligned in data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * Tuner cx24109 is written through a dedicated 3wire interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * on the demod chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int cx24123_pll_writereg(struct dvb_frontend *fe, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dprintk("pll writereg called, data=0x%08x\n", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* align the 21 bytes into to bit23 boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) data = data << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Reset the demod pll word length to 0x15 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) cx24123_writereg(state, 0x21, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* write the msb 8 bits, wait for the send to be completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) timeout = jiffies + msecs_to_jiffies(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) err("%s: demodulator is not responding, "\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) "possibly hung, aborting.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* send another 8 bytes, wait for the send to be completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) timeout = jiffies + msecs_to_jiffies(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) cx24123_writereg(state, 0x22, (data >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) err("%s: demodulator is not responding, "\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) "possibly hung, aborting.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* send the lower 5 bits of this byte, padded with 3 LBB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * wait for the send to be completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) timeout = jiffies + msecs_to_jiffies(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) cx24123_writereg(state, 0x22, (data) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) while ((cx24123_readreg(state, 0x20) & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) err("%s: demodulator is not responding," \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "possibly hung, aborting.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Trigger the demod to configure the tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static int cx24123_pll_tune(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dprintk("frequency=%i\n", p->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (cx24123_pll_calculate(fe) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) err("%s: cx24123_pll_calculate failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Write the new VCO/VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) cx24123_pll_writereg(fe, state->VCAarg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) cx24123_pll_writereg(fe, state->VGAarg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Write the new bandselect and pll args */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) cx24123_pll_writereg(fe, state->bandselectarg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) cx24123_pll_writereg(fe, state->pllarg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* set the FILTUNE voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) val = cx24123_readreg(state, 0x28) & ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) cx24123_writereg(state, 0x27, state->FILTune >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dprintk("pll tune VCA=%d, band=%d, pll=%d\n", state->VCAarg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) state->bandselectarg, state->pllarg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * 0x23:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * [7:7] = BTI enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * [6:6] = I2C repeater enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * [5:5] = I2C repeater start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * [0:0] = BTI start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* mode == 1 -> i2c-repeater, 0 -> bti */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static int cx24123_repeater_mode(struct cx24123_state *state, u8 mode, u8 start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u8 r = cx24123_readreg(state, 0x23) & 0x1e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) r |= (1 << 6) | (start << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) r |= (1 << 7) | (start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return cx24123_writereg(state, 0x23, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static int cx24123_initfe(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dprintk("init frontend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Configure the demod to a good set of defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) cx24123_writereg(state, cx24123_regdata[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) cx24123_regdata[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Set the LNB polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (state->config->lnb_polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) cx24123_writereg(state, 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) cx24123_readreg(state, 0x32) | 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (state->config->dont_use_pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) cx24123_repeater_mode(state, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static int cx24123_set_voltage(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) enum fe_sec_voltage voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) val = cx24123_readreg(state, 0x29) & ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) switch (voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) case SEC_VOLTAGE_13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dprintk("setting voltage 13V\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return cx24123_writereg(state, 0x29, val & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case SEC_VOLTAGE_18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dprintk("setting voltage 18V\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return cx24123_writereg(state, 0x29, val | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) case SEC_VOLTAGE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* already handled in cx88-dvb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* wait for diseqc queue to become ready (or timeout) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static void cx24123_wait_for_diseqc(struct cx24123_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) unsigned long timeout = jiffies + msecs_to_jiffies(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) while (!(cx24123_readreg(state, 0x29) & 0x40)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) err("%s: diseqc queue not ready, " \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "command may be lost.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int cx24123_send_diseqc_msg(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct dvb_diseqc_master_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int i, val, tone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dprintk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* stop continuous tone if enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) tone = cx24123_readreg(state, 0x29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (tone & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) cx24123_writereg(state, 0x29, tone & ~0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* wait for diseqc queue ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) cx24123_wait_for_diseqc(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* select tone mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) for (i = 0; i < cmd->msg_len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) cx24123_writereg(state, 0x2C + i, cmd->msg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) val = cx24123_readreg(state, 0x29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ((cmd->msg_len-3) & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* wait for diseqc message to finish sending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) cx24123_wait_for_diseqc(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* restart continuous tone if enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (tone & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) cx24123_writereg(state, 0x29, tone & ~0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int cx24123_diseqc_send_burst(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) enum fe_sec_mini_cmd burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) int val, tone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dprintk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* stop continuous tone if enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) tone = cx24123_readreg(state, 0x29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (tone & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) cx24123_writereg(state, 0x29, tone & ~0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* wait for diseqc queue ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) cx24123_wait_for_diseqc(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* select tone mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) val = cx24123_readreg(state, 0x29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (burst == SEC_MINI_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) else if (burst == SEC_MINI_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) cx24123_wait_for_diseqc(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* restart continuous tone if enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (tone & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) cx24123_writereg(state, 0x29, tone & ~0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int cx24123_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int sync = cx24123_readreg(state, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (state->config->dont_use_pll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u32 tun_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (fe->ops.tuner_ops.get_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) fe->ops.tuner_ops.get_status(fe, &tun_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (tun_status & TUNER_STATUS_LOCKED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) int lock = cx24123_readreg(state, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (lock & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (sync & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) *status |= FE_HAS_CARRIER; /* Phase locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (sync & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) *status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* Reed-Solomon Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (sync & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (sync & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) *status |= FE_HAS_LOCK; /*Full Sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * Configured to return the measurement of errors in blocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * because no UCBLOCKS value is available, so this value doubles up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * to satisfy both measurements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static int cx24123_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* The true bit error rate is this value divided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) the window size (set as 256 * 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) (cx24123_readreg(state, 0x1d) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) cx24123_readreg(state, 0x1e));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dprintk("BER = %d\n", *ber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static int cx24123_read_signal_strength(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u16 *signal_strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* larger = better */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) *signal_strength = cx24123_readreg(state, 0x3b) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dprintk("Signal strength = %d\n", *signal_strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static int cx24123_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* Inverted raw Es/N0 count, totally bogus but better than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) BER threshold. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) (u16)cx24123_readreg(state, 0x19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dprintk("read S/N index = %d\n", *snr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static int cx24123_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dprintk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (state->config->set_ts_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) state->config->set_ts_params(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) state->currentfreq = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) state->currentsymbolrate = p->symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) cx24123_set_inversion(state, p->inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) cx24123_set_fec(state, p->fec_inner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) cx24123_set_symbolrate(state, p->symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (!state->config->dont_use_pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) cx24123_pll_tune(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) else if (fe->ops.tuner_ops.set_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) err("it seems I don't have a tuner...");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* Enable automatic acquisition and reset cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) cx24123_writereg(state, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) cx24123_writereg(state, 0x00, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (state->config->agc_callback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) state->config->agc_callback(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int cx24123_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) dprintk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (cx24123_get_inversion(state, &p->inversion) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) err("%s: Failed to get inversion status\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (cx24123_get_fec(state, &p->fec_inner) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) err("%s: Failed to get fec status\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) p->frequency = state->currentfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) p->symbol_rate = state->currentsymbolrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static int cx24123_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* wait for diseqc queue ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) cx24123_wait_for_diseqc(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) val = cx24123_readreg(state, 0x29) & ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) switch (tone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) case SEC_TONE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) dprintk("setting tone on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return cx24123_writereg(state, 0x29, val | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) case SEC_TONE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) dprintk("setting tone off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return cx24123_writereg(state, 0x29, val & 0xef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) err("CASE reached default with tone=%d\n", tone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static int cx24123_tune(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) bool re_tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) unsigned int mode_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) unsigned int *delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (re_tune)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) retval = cx24123_set_frontend(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) cx24123_read_status(fe, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) *delay = HZ/10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static enum dvbfe_algo cx24123_get_algo(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return DVBFE_ALGO_HW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static void cx24123_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dprintk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) i2c_del_adapter(&state->tuner_i2c_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static int cx24123_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct i2c_msg msg[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct cx24123_state *state = i2c_get_adapdata(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* this repeater closes after the first stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) cx24123_repeater_mode(state, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return i2c_transfer(state->i2c, msg, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static u32 cx24123_tuner_i2c_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return I2C_FUNC_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static const struct i2c_algorithm cx24123_tuner_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .master_xfer = cx24123_tuner_i2c_tuner_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .functionality = cx24123_tuner_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct i2c_adapter *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) cx24123_get_tuner_i2c_adapter(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct cx24123_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return &state->tuner_i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) EXPORT_SYMBOL(cx24123_get_tuner_i2c_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static const struct dvb_frontend_ops cx24123_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct dvb_frontend *cx24123_attach(const struct cx24123_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct cx24123_state *state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) kzalloc(sizeof(struct cx24123_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dprintk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (state == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) err("Unable to kzalloc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) state->demod_rev = cx24123_readreg(state, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) switch (state->demod_rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) case 0xe1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) info("detected CX24123C\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) case 0xd1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) info("detected CX24123\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) err("wrong demod revision: %x\n", state->demod_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) memcpy(&state->frontend.ops, &cx24123_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* create tuner i2c adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (config->dont_use_pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) cx24123_repeater_mode(state, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) strscpy(state->tuner_i2c_adapter.name, "CX24123 tuner I2C bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) sizeof(state->tuner_i2c_adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) state->tuner_i2c_adapter.algo = &cx24123_tuner_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) state->tuner_i2c_adapter.algo_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) state->tuner_i2c_adapter.dev.parent = i2c->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) i2c_set_adapdata(&state->tuner_i2c_adapter, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) err("tuner i2c bus could not be initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) EXPORT_SYMBOL(cx24123_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static const struct dvb_frontend_ops cx24123_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .delsys = { SYS_DVBS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .name = "Conexant CX24123/CX24109",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .frequency_min_hz = 950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .frequency_stepsize_hz = 1011 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .frequency_tolerance_hz = 5 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .symbol_rate_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .symbol_rate_max = 45000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) FE_CAN_QPSK | FE_CAN_RECOVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .release = cx24123_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .init = cx24123_initfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .set_frontend = cx24123_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .get_frontend = cx24123_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .read_status = cx24123_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .read_ber = cx24123_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .read_signal_strength = cx24123_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .read_snr = cx24123_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .diseqc_send_master_cmd = cx24123_send_diseqc_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .diseqc_send_burst = cx24123_diseqc_send_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .set_tone = cx24123_set_tone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .set_voltage = cx24123_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .tune = cx24123_tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .get_frontend_algo = cx24123_get_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) MODULE_DESCRIPTION("DVB Frontend module for Conexant " \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) "CX24123/CX24109/CX24113 hardware");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) MODULE_AUTHOR("Steven Toth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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