Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Driver for Conexant CX24113/CX24128 Tuner (Satellite)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2007-8 Patrick Boettcher <pb@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Developed for BBTI / Technisat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "cx24113.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define cx_info(args...) do { printk(KERN_INFO "CX24113: " args); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define cx_err(args...)  do { printk(KERN_ERR  "CX24113: " args); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		if (debug) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 			printk(KERN_DEBUG "CX24113: %s: ", __func__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 			printk(args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct cx24113_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	const struct cx24113_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define REV_CX24113 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u8 ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u8 icp_mode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ICP_LEVEL1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ICP_LEVEL2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ICP_LEVEL3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ICP_LEVEL4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u8 icp_man:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u8 icp_auto_low:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u8 icp_auto_mlow:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u8 icp_auto_mhi:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u8 icp_auto_hi:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u8 icp_dig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define LNA_MIN_GAIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define LNA_MID_GAIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define LNA_MAX_GAIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u8 lna_gain:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u8 acp_on:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u8 vco_mode:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u8 vco_shift:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define VCOBANDSEL_6 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define VCOBANDSEL_5 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define VCOBANDSEL_4 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define VCOBANDSEL_3 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define VCOBANDSEL_2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define VCOBANDSEL_1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u8 vco_band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define VCODIV4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define VCODIV2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u8 vcodiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u8 bs_delay:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u16 bs_freqcnt:13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u16 bs_rdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u8 prescaler_mode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u8 rfvga_bias_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	s16 tuner_gain_thres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u8  gain_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u8 refdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u8 Fwindow_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static int cx24113_writereg(struct cx24113_state *state, int reg, int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u8 buf[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct i2c_msg msg = { .addr = state->config->i2c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.flags = 0, .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	int err = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (err != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		printk(KERN_DEBUG "%s: writereg error(err == %i, reg == 0x%02x, data == 0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		       __func__, err, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int cx24113_readreg(struct cx24113_state *state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u8 b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		{ .addr = state->config->i2c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			.flags = 0, .buf = &reg, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		{ .addr = state->config->i2c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			.flags = I2C_M_RD, .buf = &b, .len = 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	ret = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		printk(KERN_DEBUG "%s: reg=0x%x (error=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			__func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void cx24113_set_parameters(struct cx24113_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u8 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	r = cx24113_readreg(state, 0x10) & 0x82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	r |= state->icp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	r |= state->icp_man << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	r |= state->icp_dig << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	r |= state->prescaler_mode << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	cx24113_writereg(state, 0x10, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	r = (state->icp_auto_low  << 0) | (state->icp_auto_mlow << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		| (state->icp_auto_mhi << 4) | (state->icp_auto_hi << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	cx24113_writereg(state, 0x11, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (state->rev == REV_CX24113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		r = cx24113_readreg(state, 0x20) & 0xec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		r |= state->lna_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		r |= state->rfvga_bias_ctrl << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		cx24113_writereg(state, 0x20, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	r = cx24113_readreg(state, 0x12) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	r |= state->acp_on << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	r |= state->bs_delay << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	cx24113_writereg(state, 0x12, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	r = cx24113_readreg(state, 0x18) & 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	r |= state->vco_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (state->vco_band == VCOBANDSEL_6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		r |= (1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		r |= (state->vco_band << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	cx24113_writereg(state, 0x18, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	r  = cx24113_readreg(state, 0x14) & 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	r |= (state->vco_mode << 6) | ((state->bs_freqcnt >> 8) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	cx24113_writereg(state, 0x14, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	cx24113_writereg(state, 0x15, (state->bs_freqcnt        & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	cx24113_writereg(state, 0x16, (state->bs_rdiv >> 4) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	r = (cx24113_readreg(state, 0x17) & 0x0f) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		((state->bs_rdiv & 0x0f) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	cx24113_writereg(state, 0x17, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define VGA_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define VGA_1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define VGA_2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define VGA_3 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define VGA_4 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define VGA_5 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define VGA_6 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define VGA_7 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RFVGA_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RFVGA_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RFVGA_2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RFVGA_3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int cx24113_set_gain_settings(struct cx24113_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		s16 power_estimation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	u8 ampout = cx24113_readreg(state, 0x1d) & 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	   vga    = cx24113_readreg(state, 0x1f) & 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	   rfvga  = cx24113_readreg(state, 0x20) & 0xf3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	u8 gain_level = power_estimation >= state->tuner_gain_thres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	dprintk("power estimation: %d, thres: %d, gain_level: %d/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			power_estimation, state->tuner_gain_thres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			state->gain_level, gain_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (gain_level == state->gain_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return 0; /* nothing to be done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	ampout |= 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (gain_level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		rfvga |= RFVGA_0 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		vga   |= (VGA_7 << 3) | VGA_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		rfvga |= RFVGA_2 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		vga  |= (VGA_6 << 3) | VGA_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	state->gain_level = gain_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	cx24113_writereg(state, 0x1d, ampout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	cx24113_writereg(state, 0x1f, vga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	cx24113_writereg(state, 0x20, rfvga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return 1; /* did something */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int cx24113_set_Fref(struct cx24113_state *state, u8 high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	u8 xtal = cx24113_readreg(state, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (state->rev == 0x43 && state->vcodiv == VCODIV4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		high = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	xtal &= ~0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		xtal |= high << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return cx24113_writereg(state, 0x02, xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int cx24113_enable(struct cx24113_state *state, u8 enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	u8 r21 = (cx24113_readreg(state, 0x21) & 0xc0) | enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (state->rev == REV_CX24113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		r21 |= (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	return cx24113_writereg(state, 0x21, r21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int cx24113_set_bandwidth(struct cx24113_state *state, u32 bandwidth_khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	u8 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (bandwidth_khz <= 19000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		r = 0x03 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	else if (bandwidth_khz <= 25000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		r = 0x02 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		r = 0x01 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	dprintk("bandwidth to be set: %d\n", bandwidth_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	bandwidth_khz *= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	bandwidth_khz -= 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	bandwidth_khz /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	bandwidth_khz += 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	bandwidth_khz /= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	dprintk("bandwidth: %d %d\n", r >> 6, bandwidth_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	r |= bandwidth_khz & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return cx24113_writereg(state, 0x1e, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int cx24113_set_clk_inversion(struct cx24113_state *state, u8 on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	u8 r = (cx24113_readreg(state, 0x10) & 0x7f) | ((on & 0x1) << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	return cx24113_writereg(state, 0x10, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int cx24113_get_status(struct dvb_frontend *fe, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct cx24113_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	u8 r = (cx24113_readreg(state, 0x10) & 0x02) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		*status |= TUNER_STATUS_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	dprintk("PLL locked: %d\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static u8 cx24113_set_ref_div(struct cx24113_state *state, u8 refdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (state->rev == 0x43 && state->vcodiv == VCODIV4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		refdiv = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return state->refdiv = refdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void cx24113_calc_pll_nf(struct cx24113_state *state, u16 *n, s32 *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	s32 N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	s64 F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	u64 dividend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	u8 R, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	u8 vcodiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	u8 factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	s32 freq_hz = state->frequency * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (state->config->xtal_khz < 20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		factor = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		factor = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	if (state->rev == REV_CX24113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		if (state->frequency >= 1100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			vcodiv = VCODIV2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			vcodiv = VCODIV4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		if (state->frequency >= 1165000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			vcodiv = VCODIV2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			vcodiv = VCODIV4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	state->vcodiv = vcodiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	dprintk("calculating N/F for %dHz with vcodiv %d\n", freq_hz, vcodiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	R = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		R = cx24113_set_ref_div(state, R + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		/* calculate tuner PLL settings: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		N =  (freq_hz / 100 * vcodiv) * R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		N /= (state->config->xtal_khz) * factor * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		N += 5;     /* For round up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		N /= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		N -= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	} while (N < 6 && R < 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (N < 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		cx_err("strange frequency: N < 6\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	F = freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	F *= (u64) (R * vcodiv * 262144);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	dprintk("1 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	/* do_div needs an u64 as first argument */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	dividend = F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	do_div(dividend, state->config->xtal_khz * 1000 * factor * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	F = dividend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	dprintk("2 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	F -= (N + 32) * 262144;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	dprintk("3 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (state->Fwindow_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		if (F > (262144 / 2 - 1638))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			F = 262144 / 2 - 1638;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		if (F < (-262144 / 2 + 1638))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			F = -262144 / 2 + 1638;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		if ((F < 3277 && F > 0) || (F > -3277 && F < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			F = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			r = cx24113_readreg(state, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			cx24113_writereg(state, 0x10, r | (1 << 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	dprintk("4 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	*n = (u16) N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	*f = (s32) F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static void cx24113_set_nfr(struct cx24113_state *state, u16 n, s32 f, u8 r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	cx24113_writereg(state, 0x19, (n >> 1) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	reg = ((n & 0x1) << 7) | ((f >> 11) & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	cx24113_writereg(state, 0x1a, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	cx24113_writereg(state, 0x1b, (f >> 3) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	reg = cx24113_readreg(state, 0x1c) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	cx24113_writereg(state, 0x1c, reg | ((f & 0x7) << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	cx24113_set_Fref(state, r - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int cx24113_set_frequency(struct cx24113_state *state, u32 frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	u8 r = 1; /* or 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	u16 n = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	s32 f = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	r = cx24113_readreg(state, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	cx24113_writereg(state, 0x14, r & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	r = cx24113_readreg(state, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	cx24113_writereg(state, 0x10, r & 0xbf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	state->frequency = frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	dprintk("tuning to frequency: %d\n", frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	cx24113_calc_pll_nf(state, &n, &f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	cx24113_set_nfr(state, n, f, state->refdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	r = cx24113_readreg(state, 0x18) & 0xbf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (state->vcodiv != VCODIV2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		r |= 1 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	cx24113_writereg(state, 0x18, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	/* The need for this sleep is not clear. But helps in some cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	r = cx24113_readreg(state, 0x1c) & 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	cx24113_writereg(state, 0x1c, r | (1 << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int cx24113_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	struct cx24113_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	state->tuner_gain_thres = -50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	state->gain_level = 255; /* to force a gain-setting initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	state->icp_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	if (state->config->xtal_khz < 11000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		state->icp_auto_hi  = ICP_LEVEL4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		state->icp_auto_mhi  = ICP_LEVEL4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		state->icp_auto_mlow = ICP_LEVEL3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		state->icp_auto_low = ICP_LEVEL3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		state->icp_auto_hi  = ICP_LEVEL4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		state->icp_auto_mhi  = ICP_LEVEL4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		state->icp_auto_mlow = ICP_LEVEL3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		state->icp_auto_low = ICP_LEVEL2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	state->icp_dig = ICP_LEVEL3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	state->icp_man = ICP_LEVEL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	state->acp_on  = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	state->vco_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	state->vco_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	state->vco_band = VCOBANDSEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	state->bs_delay = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	state->bs_freqcnt = 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	state->bs_rdiv = 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	state->prescaler_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	state->lna_gain = LNA_MAX_GAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	state->rfvga_bias_ctrl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	state->Fwindow_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	cx24113_set_Fref(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	cx24113_enable(state, 0x3d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	cx24113_set_parameters(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	cx24113_set_gain_settings(state, -30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	cx24113_set_bandwidth(state, 18025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	cx24113_set_clk_inversion(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	if (state->config->xtal_khz >= 40000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		ret = cx24113_writereg(state, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 			(cx24113_readreg(state, 0x02) & 0xfb) | (1 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		ret = cx24113_writereg(state, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 			(cx24113_readreg(state, 0x02) & 0xfb) | (0 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int cx24113_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	struct cx24113_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	/* for a ROLL-OFF factor of 0.35, 0.2: 600, 0.25: 625 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	u32 roll_off = 675;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	u32 bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	bw  = ((c->symbol_rate/100) * roll_off) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	bw += (10000000/100) + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	bw /= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	bw += 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	cx24113_set_bandwidth(state, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	cx24113_set_frequency(state, c->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	return cx24113_get_status(fe, &bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static s8 cx24113_agc_table[2][10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	{-54, -41, -35, -30, -25, -21, -16, -10,  -6,  -2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	{-39, -35, -30, -25, -19, -15, -11,  -5,   1,   9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) void cx24113_agc_callback(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	struct cx24113_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	s16 s, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	if (!fe->ops.read_signal_strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		/* this only works with the current CX24123 implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		fe->ops.read_signal_strength(fe, (u16 *) &s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 		s >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 		dprintk("signal strength: %d\n", s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		for (i = 0; i < sizeof(cx24113_agc_table[0]); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 			if (cx24113_agc_table[state->gain_level][i] > s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		s = -25 - i*5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	} while (cx24113_set_gain_settings(state, s));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) EXPORT_SYMBOL(cx24113_agc_callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int cx24113_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	struct cx24113_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	*frequency = state->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void cx24113_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	struct cx24113_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	dprintk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const struct dvb_tuner_ops cx24113_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 		.name              = "Conexant CX24113",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 		.frequency_min_hz  =  950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 		.frequency_max_hz  = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 		.frequency_step_hz =  125 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	.release       = cx24113_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	.init          = cx24113_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	.set_params    = cx24113_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	.get_frequency = cx24113_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	.get_status    = cx24113_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct dvb_frontend *cx24113_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 		const struct cx24113_config *config, struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	/* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	struct cx24113_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	/* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	cx_info("trying to detect myself\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	/* making a dummy read, because of some expected troubles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	 * after power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	cx24113_readreg(state, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	rc = cx24113_readreg(state, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 		cx_info("CX24113 not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	state->rev = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	switch (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	case 0x43:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 		cx_info("detected CX24113 variant\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	case REV_CX24113:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 		cx_info("successfully detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 		cx_err("unsupported device id: %x\n", state->rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	state->ver = cx24113_readreg(state, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	cx_info("version: %x\n", state->ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	/* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	memcpy(&fe->ops.tuner_ops, &cx24113_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 			sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	fe->tuner_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) EXPORT_SYMBOL(cx24113_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MODULE_AUTHOR("Patrick Boettcher <pb@linuxtv.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MODULE_DESCRIPTION("DVB Frontend module for Conexant CX24113/CX24128hardware");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)