^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) cx24110 - Single Chip Satellite Channel Receiver driver module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@htp-tel.de> based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "cx24110.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct cx24110_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) const struct cx24110_config* config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 lastber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 lastbler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 lastesn0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (debug) printk(KERN_DEBUG "cx24110: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct {u8 reg; u8 data;} cx24110_regdata[]=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Comments beginning with @ denote this value should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) be the default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {{0x09,0x01}, /* SoftResetAll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {0x09,0x00}, /* release reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {0x01,0xe8}, /* MSB of code rate 27.5MS/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {0x02,0x17}, /* middle byte " */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {0x03,0x29}, /* LSB " */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {0x06,0xa5}, /* @ PLL 60MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {0x0a,0x00}, /* @ partial chip disables, do not set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {0x0b,0x01}, /* set output clock in gapped mode, start signal low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) active for first byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) to avoid starting the BER counter. Reset the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) CRC test bit. Finite counting selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {0x15,0xff}, /* @ size of the limited time window for RS BER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) estimation. It is <value>*256 RS blocks, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {0x16,0x00}, /* @ enable all RS output ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {0x17,0x04}, /* @ time window allowed for the RS to sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) for automatically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* leave the current code rate and normalization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) registers as they are after reset... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) only once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {0x23,0x18}, /* @ size of the limited time window for Viterbi BER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) estimation. It is <value>*65536 channel bits, i.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) approx. 38ms at 27.5MS/s, rate 3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* leave front-end AGC parameters at default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* leave decimation AGC parameters at default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {0x35,0x40}, /* disable all interrupts. They are not connected anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {0x36,0xff}, /* clear all interrupt pending flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {0x37,0x00}, /* @ fully enable AutoAcqq state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* leave the equalizer parameters on their default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* leave the final AGC parameters on their default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {0x41,0x00}, /* @ MSB of front-end derotator frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {0x42,0x00}, /* @ middle bytes " */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {0x43,0x00}, /* @ LSB " */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* leave the carrier tracking loop parameters on default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* leave the bit timing loop parameters at default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* the cx24108 data sheet for symbol rates above 15MS/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {0x57,0x00}, /* @ Filter sigma delta enabled, positive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {0x61,0x95}, /* GPIO pins 1-4 have special function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {0x64,0x20}, /* GPIO 6 is input, all others are outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {0x73,0x00}, /* @ disable several demod bypasses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {0x74,0x00}, /* @ " */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {0x75,0x00} /* @ " */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* the remaining registers are for SEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int cx24110_writereg (struct cx24110_state* state, int reg, int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 buf [] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __func__, err, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int cx24110_readreg (struct cx24110_state* state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 b0 [] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 b1 [] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret != 2) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int cx24110_set_inversion(struct cx24110_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) enum fe_spectral_inversion inversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* fixme (low): error handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) switch (inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case INVERSION_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* AcqSpectrInvDis on. No idea why someone should want this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Initial value 0 at start of acq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* current value 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* The cx24110 manual tells us this reg is read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) But what the heck... set it ayways */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case INVERSION_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* AcqSpectrInvDis on. No idea why someone should want this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Initial value 1 at start of acq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* current value 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case INVERSION_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* AcqSpectrInvDis off. Leave initial & current states as is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int cx24110_set_fec(struct cx24110_state *state, enum fe_code_rate fec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const int rate[FEC_AUTO] = {-1, 1, 2, 3, 5, 7, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const int g1[FEC_AUTO] = {-1, 0x01, 0x02, 0x05, 0x15, 0x45, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const int g2[FEC_AUTO] = {-1, 0x01, 0x03, 0x06, 0x1a, 0x7a, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Well, the AutoAcq engine of the cx24106 and 24110 automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) searches all enabled viterbi rates, and can handle non-standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rates as well. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (fec > FEC_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) fec = FEC_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (fec == FEC_AUTO) { /* (re-)establish AutoAcq behaviour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) & 0xdf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* clear AcqVitDis bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) cx24110_writereg(state, 0x18, 0xae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* allow all DVB standard code rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* set nominal Viterbi rate 3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* set current Viterbi rate 3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) cx24110_writereg(state, 0x1a, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) cx24110_writereg(state, 0x1b, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* set the puncture registers for code rate 3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) | 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* set AcqVitDis bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (rate[fec] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | rate[fec]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* set nominal Viterbi rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | rate[fec]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* set current Viterbi rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) cx24110_writereg(state, 0x1a, g1[fec]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) cx24110_writereg(state, 0x1b, g2[fec]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* not sure if this is the right way: I always used AutoAcq mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static enum fe_code_rate cx24110_get_fec(struct cx24110_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) i=cx24110_readreg(state,0x22)&0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if(!(i&0x08)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return FEC_1_2 + i - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* fixme (low): a special code rate has been selected. In theory, we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return a denominator value, a numerator value, and a pair of puncture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) maps to correctly describe this mode. But this should never happen in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) practice, because it cannot be set by cx24110_get_fec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* fixme (low): add error handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 tmp, fclk, BDRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const u32 bands[]={5000000UL,15000000UL,90999000UL/2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dprintk("cx24110 debug: entering %s(%d)\n",__func__,srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (srate>90999000UL/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) srate=90999000UL/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (srate<500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) srate=500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) for(i = 0; (i < ARRAY_SIZE(bands)) && (srate>bands[i]); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) R06[3:0] PLLphaseDetGain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tmp=cx24110_readreg(state,0x07)&0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if(srate<90999000UL/4) { /* sample rate 45MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) cx24110_writereg(state,0x07,tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) cx24110_writereg(state,0x06,0x78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) fclk=90999000UL/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) } else if(srate<60666000UL/2) { /* sample rate 60MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) cx24110_writereg(state,0x07,tmp|0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) cx24110_writereg(state,0x06,0xa5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) fclk=60666000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } else if(srate<80888000UL/2) { /* sample rate 80MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) cx24110_writereg(state,0x07,tmp|0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) cx24110_writereg(state,0x06,0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) fclk=80888000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) } else { /* sample rate 90MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) cx24110_writereg(state,0x07,tmp|0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cx24110_writereg(state,0x06,0x78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) fclk=90999000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dprintk("cx24110 debug: fclk %d Hz\n",fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* we need to divide two integers with approx. 27 bits in 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) arithmetic giving a 25 bit result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* the maximum dividend is 90999000/2, 0x02b6446c, this number is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) also the most complex divisor. Hence, the dividend has,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) assuming 32bit unsigned arithmetic, 6 clear bits on top, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) divisor 2 unused bits at the bottom. Also, the quotient is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) always less than 1/2. Borrowed from VES1893.c, of course */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) tmp=srate<<6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) BDRI=fclk>>2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ratio=(tmp/BDRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) tmp=(tmp%BDRI)<<8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ratio=(ratio<<8)+(tmp/BDRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) tmp=(tmp%BDRI)<<8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ratio=(ratio<<8)+(tmp/BDRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) tmp=(tmp%BDRI)<<1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ratio=(ratio<<1)+(tmp/BDRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dprintk("srate= %d (range %d, up to %d)\n", srate,i,bands[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dprintk("fclk = %d\n", fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dprintk("ratio= %08x\n", ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) cx24110_writereg(state, 0x1, (ratio>>16)&0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cx24110_writereg(state, 0x2, (ratio>>8)&0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) cx24110_writereg(state, 0x3, (ratio)&0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int _cx24110_pll_write (struct dvb_frontend* fe, const u8 buf[], int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct cx24110_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (len != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* tuner data is 21 bits long, must be left-aligned in data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* tuner cx24108 is written through a dedicated 3wire interface on the demod chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* FIXME (low): add error handling, avoid infinite loops if HW fails... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* if the auto tuner writer is still busy, clear it out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) while (cx24110_readreg(state,0x6d)&0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) cx24110_writereg(state,0x72,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* write the topmost 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) cx24110_writereg(state,0x72,buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* wait for the send to be completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* send another 8 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cx24110_writereg(state,0x72,buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* and the topmost 5 bits of this byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) cx24110_writereg(state,0x72,buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* now strobe the enable line once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) cx24110_writereg(state,0x6d,0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) cx24110_writereg(state,0x6d,0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int cx24110_initfe(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct cx24110_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* fixme (low): error handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dprintk("%s: init chip\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) for(i = 0; i < ARRAY_SIZE(cx24110_regdata); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int cx24110_set_voltage(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) enum fe_sec_voltage voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct cx24110_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) switch (voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case SEC_VOLTAGE_13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case SEC_VOLTAGE_18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int cx24110_diseqc_send_burst(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) enum fe_sec_mini_cmd burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int rv, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct cx24110_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (burst == SEC_MINI_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) bit = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) else if (burst == SEC_MINI_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) bit = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) rv = cx24110_readreg(state, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!(rv & 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) cx24110_writereg(state, 0x77, rv | 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) rv = cx24110_readreg(state, 0x76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40 | bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) timeout = jiffies + msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ; /* wait for LNB ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int cx24110_send_diseqc_msg(struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct dvb_diseqc_master_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int i, rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct cx24110_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (cmd->msg_len < 3 || cmd->msg_len > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -EINVAL; /* not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) for (i = 0; i < cmd->msg_len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) cx24110_writereg(state, 0x79 + i, cmd->msg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) rv = cx24110_readreg(state, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (rv & 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) cx24110_writereg(state, 0x77, rv & ~0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) msleep(30); /* reportedly fixes switching problems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) rv = cx24110_readreg(state, 0x76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) timeout = jiffies + msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ; /* wait for LNB ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int cx24110_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct cx24110_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int sync = cx24110_readreg (state, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (sync & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (sync & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) *status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) sync = cx24110_readreg (state, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (sync & 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) *status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (sync & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if ((sync & 0x60) == 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int cx24110_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct cx24110_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* fixme (maybe): value range is 16 bit. Scale? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if(cx24110_readreg(state,0x24)&0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* the Viterbi error counter has finished one counting window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) cx24110_writereg(state,0x24,0x04); /* select the ber reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) state->lastber=cx24110_readreg(state,0x25)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) (cx24110_readreg(state,0x26)<<8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) cx24110_writereg(state,0x24,0x04); /* start new count window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) cx24110_writereg(state,0x24,0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) *ber = state->lastber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int cx24110_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct cx24110_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* no provision in hardware. Read the frontend AGC accumulator. No idea how to scale this, but I know it is 2s complement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u8 signal = cx24110_readreg (state, 0x27)+128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) *signal_strength = (signal << 8) | signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int cx24110_read_snr(struct dvb_frontend* fe, u16* snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct cx24110_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* no provision in hardware. Can be computed from the Es/N0 estimator, but I don't know how. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if(cx24110_readreg(state,0x6a)&0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* the Es/N0 error counter has finished one counting window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) state->lastesn0=cx24110_readreg(state,0x69)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) (cx24110_readreg(state,0x68)<<8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) cx24110_writereg(state,0x6a,0x84); /* start new count window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) *snr = state->lastesn0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int cx24110_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct cx24110_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if(cx24110_readreg(state,0x10)&0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* the RS error counter has finished one counting window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) cx24110_writereg(state,0x10,0x60); /* select the byer reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) (void)(cx24110_readreg(state, 0x12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) (cx24110_readreg(state, 0x13) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) (cx24110_readreg(state, 0x14) << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) cx24110_writereg(state,0x10,0x70); /* select the bler reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) state->lastbler=cx24110_readreg(state,0x12)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) (cx24110_readreg(state,0x13)<<8)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) (cx24110_readreg(state,0x14)<<16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) cx24110_writereg(state,0x10,0x20); /* start new count window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *ucblocks = state->lastbler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int cx24110_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct cx24110_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) cx24110_set_inversion(state, p->inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) cx24110_set_fec(state, p->fec_inner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) cx24110_set_symbolrate(state, p->symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) cx24110_writereg(state,0x04,0x05); /* start acquisition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int cx24110_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct cx24110_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) s32 afc; unsigned sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* cannot read back tuner settings (freq). Need to have some private storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) sclk = cx24110_readreg (state, 0x07) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* ok, real AFC (FEDR) freq. is afc/2^24*fsamp, fsamp=45/60/80/90MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * Need 64 bit arithmetic. Is thiss possible in the kernel? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (sclk==0) sclk=90999000L/2L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) else if (sclk==1) sclk=60666000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) else if (sclk==2) sclk=80888000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) else sclk=90999000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) sclk>>=8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ((sclk*cx24110_readreg (state, 0x45))>>8)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ((sclk*cx24110_readreg (state, 0x46))>>16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) p->frequency += afc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) INVERSION_ON : INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) p->fec_inner = cx24110_get_fec(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int cx24110_set_tone(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) enum fe_sec_tone_mode tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct cx24110_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10:0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static void cx24110_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct cx24110_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const struct dvb_frontend_ops cx24110_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct dvb_frontend* cx24110_attach(const struct cx24110_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct i2c_adapter* i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct cx24110_state* state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) state = kzalloc(sizeof(struct cx24110_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (state == NULL) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) state->lastber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) state->lastbler = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) state->lastesn0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = cx24110_readreg(state, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if ((ret != 0x5a) && (ret != 0x69)) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) memcpy(&state->frontend.ops, &cx24110_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static const struct dvb_frontend_ops cx24110_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .delsys = { SYS_DVBS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .name = "Conexant CX24110 DVB-S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .frequency_min_hz = 950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .frequency_stepsize_hz = 1011 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .frequency_tolerance_hz = 29500 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .symbol_rate_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .symbol_rate_max = 45000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) FE_CAN_QPSK | FE_CAN_RECOVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .release = cx24110_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .init = cx24110_initfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .write = _cx24110_pll_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .set_frontend = cx24110_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .get_frontend = cx24110_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .read_status = cx24110_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .read_ber = cx24110_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .read_signal_strength = cx24110_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .read_snr = cx24110_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .read_ucblocks = cx24110_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .diseqc_send_master_cmd = cx24110_send_diseqc_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .set_tone = cx24110_set_tone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .set_voltage = cx24110_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .diseqc_send_burst = cx24110_diseqc_send_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) MODULE_DESCRIPTION("Conexant CX24110 DVB-S Demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) MODULE_AUTHOR("Peter Hettkamp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) EXPORT_SYMBOL(cx24110_attach);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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