Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)     Conexant cx22700 DVB OFDM demodulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)     Copyright (C) 2001-2002 Convergence Integrated Media GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 	Holger Waechtler <holger@convergence.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "cx22700.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) struct cx22700_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	const struct cx22700_config* config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		if (debug) printk(KERN_DEBUG "cx22700: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static u8 init_tab [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	0x04, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	0x05, 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	0x06, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	0x08, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	0x09, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	0x0a, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	0x15, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	0x16, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	0x17, 0x87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	0x18, 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	0x1a, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	0x25, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	0x2e, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	0x39, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	0x3a, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	0x45, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	0x46, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	0x47, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static int cx22700_writereg (struct cx22700_state* state, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u8 buf [] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ret = i2c_transfer (state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		printk("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			__func__, reg, data, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return (ret != 1) ? -1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static int cx22700_readreg (struct cx22700_state* state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u8 b0 [] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u8 b1 [] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			   { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	ret = i2c_transfer (state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (ret != 2) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int cx22700_set_inversion (struct cx22700_state* state, int inversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	switch (inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	case INVERSION_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	case INVERSION_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		val = cx22700_readreg (state, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		return cx22700_writereg (state, 0x09, val | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	case INVERSION_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		val = cx22700_readreg (state, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return cx22700_writereg (state, 0x09, val & 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int cx22700_set_tps(struct cx22700_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			   struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	static const u8 qam_tab [4] = { 0, 1, 0, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	static const u8 fec_tab [6] = { 0, 1, 2, 0, 3, 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (p->code_rate_HP < FEC_1_2 || p->code_rate_HP > FEC_7_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (p->code_rate_LP < FEC_1_2 || p->code_rate_LP > FEC_7_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (p->code_rate_HP == FEC_4_5 || p->code_rate_LP == FEC_4_5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if ((int)p->guard_interval < GUARD_INTERVAL_1_32 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	    p->guard_interval > GUARD_INTERVAL_1_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (p->transmission_mode != TRANSMISSION_MODE_2K &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	    p->transmission_mode != TRANSMISSION_MODE_8K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (p->modulation != QPSK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	    p->modulation != QAM_16 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	    p->modulation != QAM_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if ((int)p->hierarchy < HIERARCHY_NONE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	    p->hierarchy > HIERARCHY_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (p->bandwidth_hz > 8000000 || p->bandwidth_hz < 6000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (p->bandwidth_hz == 7000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 | 0x10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		cx22700_writereg (state, 0x09, cx22700_readreg (state, 0x09 & ~0x10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	val = qam_tab[p->modulation - QPSK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	val |= p->hierarchy - HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	cx22700_writereg (state, 0x04, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (p->code_rate_HP - FEC_1_2 >= sizeof(fec_tab) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	    p->code_rate_LP - FEC_1_2 >= sizeof(fec_tab))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	val = fec_tab[p->code_rate_HP - FEC_1_2] << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	val |= fec_tab[p->code_rate_LP - FEC_1_2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	cx22700_writereg (state, 0x05, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	val = (p->guard_interval - GUARD_INTERVAL_1_32) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	val |= p->transmission_mode - TRANSMISSION_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	cx22700_writereg (state, 0x06, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	cx22700_writereg (state, 0x08, 0x04 | 0x02);  /* use user tps parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	cx22700_writereg (state, 0x08, 0x04);         /* restart acquisition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int cx22700_get_tps(struct cx22700_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			   struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	static const enum fe_modulation qam_tab[3] = { QPSK, QAM_16, QAM_64 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	static const enum fe_code_rate fec_tab[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (!(cx22700_readreg(state, 0x07) & 0x20))  /*  tps valid? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	val = cx22700_readreg (state, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if ((val & 0x7) > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		p->hierarchy = HIERARCHY_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		p->hierarchy = HIERARCHY_NONE + (val & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (((val >> 3) & 0x3) > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		p->modulation = QAM_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		p->modulation = qam_tab[(val >> 3) & 0x3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	val = cx22700_readreg (state, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (((val >> 3) & 0x07) > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		p->code_rate_HP = FEC_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		p->code_rate_HP = fec_tab[(val >> 3) & 0x07];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if ((val & 0x07) > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		p->code_rate_LP = FEC_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		p->code_rate_LP = fec_tab[val & 0x07];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	val = cx22700_readreg (state, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	p->guard_interval = GUARD_INTERVAL_1_32 + ((val >> 6) & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	p->transmission_mode = TRANSMISSION_MODE_2K + ((val >> 5) & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int cx22700_init (struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {	struct cx22700_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	dprintk("cx22700_init: init chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	cx22700_writereg (state, 0x00, 0x02);   /*  soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	cx22700_writereg (state, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	for (i=0; i<sizeof(init_tab); i+=2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		cx22700_writereg (state, init_tab[i], init_tab[i+1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	cx22700_writereg (state, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int cx22700_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct cx22700_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	u16 rs_ber = (cx22700_readreg (state, 0x0d) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		   | (cx22700_readreg (state, 0x0e) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	u8 sync = cx22700_readreg (state, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	*status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (rs_ber < 0xff00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		*status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (sync & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		*status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (sync & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		*status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (sync & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		*status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (*status == 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		*status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int cx22700_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct cx22700_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	*ber = cx22700_readreg (state, 0x0c) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	cx22700_writereg (state, 0x0c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int cx22700_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	struct cx22700_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	u16 rs_ber = (cx22700_readreg (state, 0x0d) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		   | (cx22700_readreg (state, 0x0e) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	*signal_strength = ~rs_ber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int cx22700_read_snr(struct dvb_frontend* fe, u16* snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct cx22700_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	u16 rs_ber = (cx22700_readreg (state, 0x0d) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		   | (cx22700_readreg (state, 0x0e) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	*snr = ~rs_ber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int cx22700_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct cx22700_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	*ucblocks = cx22700_readreg (state, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	cx22700_writereg (state, 0x0f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int cx22700_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	struct cx22700_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	cx22700_writereg (state, 0x00, 0x02); /* XXX CHECKME: soft reset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	cx22700_writereg (state, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	cx22700_set_inversion(state, c->inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	cx22700_set_tps(state, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	cx22700_writereg (state, 0x37, 0x01);  /* PAL loop filter off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	cx22700_writereg (state, 0x00, 0x01);  /* restart acquire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int cx22700_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 				struct dtv_frontend_properties *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	struct cx22700_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	u8 reg09 = cx22700_readreg (state, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	c->inversion = reg09 & 0x1 ? INVERSION_ON : INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	return cx22700_get_tps(state, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int cx22700_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	struct cx22700_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		return cx22700_writereg(state, 0x0a, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return cx22700_writereg(state, 0x0a, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int cx22700_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	fesettings->min_delay_ms = 150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	fesettings->step_size = 166667;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	fesettings->max_drift = 166667*2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void cx22700_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	struct cx22700_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct dvb_frontend_ops cx22700_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct dvb_frontend* cx22700_attach(const struct cx22700_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 				    struct i2c_adapter* i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	struct cx22700_state* state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	/* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	state = kzalloc(sizeof(struct cx22700_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	if (state == NULL) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	/* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	/* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (cx22700_readreg(state, 0x07) < 0) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	/* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	memcpy(&state->frontend.ops, &cx22700_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const struct dvb_frontend_ops cx22700_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	.delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		.name			= "Conexant CX22700 DVB-T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		.frequency_min_hz	= 470 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		.frequency_max_hz	= 860 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		.frequency_stepsize_hz	= 166667,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		      FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		      FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		      FE_CAN_RECOVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	.release = cx22700_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.init = cx22700_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	.i2c_gate_ctrl = cx22700_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	.set_frontend = cx22700_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	.get_frontend = cx22700_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	.get_tune_settings = cx22700_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	.read_status = cx22700_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	.read_ber = cx22700_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	.read_signal_strength = cx22700_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	.read_snr = cx22700_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	.read_ucblocks = cx22700_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MODULE_DESCRIPTION("Conexant CX22700 DVB-T Demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MODULE_AUTHOR("Holger Waechtler");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) EXPORT_SYMBOL(cx22700_attach);