^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Auvitek AU8522 QAM/8VSB demodulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 2008 Devin Heitmueller <dheitmueller@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Copyright (C) 2005-2008 Auvitek International, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-mc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "au8522.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "tuner-i2c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AU8522_ANALOG_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AU8522_DIGITAL_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AU8522_SUSPEND_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum au8522_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) AU8522_PAD_IF_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) AU8522_PAD_VID_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) AU8522_PAD_AUDIO_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) AU8522_NUM_PADS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct au8522_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct i2c_client *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 operational_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Used for sharing of the state between analog and digital mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct tuner_i2c_props i2c_props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct list_head hybrid_tuner_instance_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct au8522_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 current_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enum fe_modulation current_modulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 fe_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int led_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Analog settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) v4l2_std_id std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int vid_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int aud_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #ifdef CONFIG_MEDIA_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct media_pad pads[AU8522_NUM_PADS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* These are routines shared by both the VSB/QAM demodulator and the analog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int au8522_writereg(struct au8522_state *state, u16 reg, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 au8522_readreg(struct au8522_state *state, u16 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int au8522_init(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int au8522_sleep(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int au8522_get_state(struct au8522_state **state, struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 client_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void au8522_release_state(struct au8522_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int au8522_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int au8522_analog_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int au8522_led_ctrl(struct au8522_state *state, int led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* REGISTERS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AU8522_INPUT_CONTROL_REG081H 0x081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AU8522_PGA_CONTROL_REG082H 0x082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AU8522_CLAMPING_CONTROL_REG083H 0x083
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H 0x0A3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H 0x0A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H 0x0A5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AU8522_AGC_CONTROL_RANGE_REG0A6H 0x0A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H 0x0A7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AU8522_TUNER_AGC_RF_STOP_REG0A8H 0x0A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AU8522_TUNER_AGC_RF_START_REG0A9H 0x0A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AU8522_TUNER_RF_AGC_DEFAULT_REG0AAH 0x0AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AU8522_TUNER_AGC_IF_STOP_REG0ABH 0x0AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AU8522_TUNER_AGC_IF_START_REG0ACH 0x0AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AU8522_TUNER_AGC_IF_DEFAULT_REG0ADH 0x0AD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AU8522_TUNER_AGC_STEP_REG0AEH 0x0AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AU8522_TUNER_GAIN_STEP_REG0AFH 0x0AF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Receiver registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AU8522_FRMREGTHRD1_REG0B0H 0x0B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AU8522_FRMREGAGC1H_REG0B1H 0x0B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AU8522_FRMREGSHIFT1_REG0B2H 0x0B2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AU8522_TOREGAGC1_REG0B3H 0x0B3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AU8522_TOREGASHIFT1_REG0B4H 0x0B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AU8522_FRMREGBBH_REG0B5H 0x0B5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AU8522_FRMREGBBM_REG0B6H 0x0B6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AU8522_FRMREGBBL_REG0B7H 0x0B7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* 0xB8 TO 0xD7 are the filter coefficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AU8522_FRMREGTHRD2_REG0D8H 0x0D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AU8522_FRMREGAGC2H_REG0D9H 0x0D9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AU8522_TOREGAGC2_REG0DAH 0x0DA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AU8522_TOREGSHIFT2_REG0DBH 0x0DB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AU8522_FRMREGPILOTH_REG0DCH 0x0DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AU8522_FRMREGPILOTM_REG0DDH 0x0DD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AU8522_FRMREGPILOTL_REG0DEH 0x0DE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AU8522_TOREGFREQ_REG0DFH 0x0DF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AU8522_RX_PGA_RFOUT_REG0EBH 0x0EB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AU8522_RX_PGA_IFOUT_REG0ECH 0x0EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AU8522_RX_PGA_PGAOUT_REG0EDH 0x0ED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AU8522_CHIP_MODE_REG0FEH 0x0FE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* I2C bus control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AU8522_I2C_CONTROL_REG0_REG090H 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AU8522_I2C_CONTROL_REG1_REG091H 0x091
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AU8522_I2C_STATUS_REG092H 0x092
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AU8522_I2C_WR_DATA0_REG093H 0x093
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AU8522_I2C_WR_DATA1_REG094H 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AU8522_I2C_WR_DATA2_REG095H 0x095
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AU8522_I2C_WR_DATA3_REG096H 0x096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AU8522_I2C_WR_DATA4_REG097H 0x097
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AU8522_I2C_WR_DATA5_REG098H 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AU8522_I2C_WR_DATA6_REG099H 0x099
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AU8522_I2C_WR_DATA7_REG09AH 0x09A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AU8522_I2C_RD_DATA0_REG09BH 0x09B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AU8522_I2C_RD_DATA1_REG09CH 0x09C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AU8522_I2C_RD_DATA2_REG09DH 0x09D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AU8522_I2C_RD_DATA3_REG09EH 0x09E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AU8522_I2C_RD_DATA4_REG09FH 0x09F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AU8522_I2C_RD_DATA5_REG0A0H 0x0A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AU8522_I2C_RD_DATA6_REG0A1H 0x0A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AU8522_I2C_RD_DATA7_REG0A2H 0x0A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AU8522_ENA_USB_REG101H 0x101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AU8522_I2S_CTRL_0_REG110H 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AU8522_I2S_CTRL_1_REG111H 0x111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AU8522_I2S_CTRL_2_REG112H 0x112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AU8522_FRMREGFFECONTROL_REG121H 0x121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AU8522_FRMREGDFECONTROL_REG122H 0x122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AU8522_CARRFREQOFFSET0_REG201H 0x201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AU8522_CARRFREQOFFSET1_REG202H 0x202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AU8522_DECIMATION_GAIN_REG21AH 0x21A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AU8522_FRMREGIFSLP_REG21BH 0x21B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AU8522_FRMREGTHRDL2_REG21CH 0x21C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define AU8522_FRMREGSTEP3DB_REG21DH 0x21D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AU8522_DAGC_GAIN_ADJUSTMENT_REG21EH 0x21E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AU8522_FRMREGPLLMODE_REG21FH 0x21F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AU8522_FRMREGCSTHRD_REG220H 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define AU8522_FRMREGCRLOCKDMAX_REG221H 0x221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AU8522_FRMREGCRPERIODMASK_REG222H 0x222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define AU8522_FRMREGCRLOCK0THH_REG223H 0x223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AU8522_FRMREGCRLOCK1THH_REG224H 0x224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define AU8522_FRMREGCRLOCK0THL_REG225H 0x225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AU8522_FRMREGCRLOCK1THL_REG226H 0x226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AU_FRMREGPLLACQPHASESCL_REG227H 0x227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AU8522_FRMREGFREQFBCTRL_REG228H 0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Analog TV Decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AU8522_TVDEC_STATUS_REG000H 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AU8522_TVDEC_INT_STATUS_REG001H 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AU8522_TVDEC_MACROVISION_STATUS_REG002H 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define AU8522_TVDEC_SHARPNESSREG009H 0x009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AU8522_TVDEC_BRIGHTNESS_REG00AH 0x00A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AU8522_TVDEC_CONTRAST_REG00BH 0x00B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AU8522_TVDEC_SATURATION_CB_REG00CH 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AU8522_TVDEC_SATURATION_CR_REG00DH 0x00D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AU8522_TVDEC_HUE_H_REG00EH 0x00E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AU8522_TVDEC_HUE_L_REG00FH 0x00F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AU8522_TVDEC_INT_MASK_REG010H 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AU8522_VIDEO_MODE_REG011H 0x011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AU8522_TVDEC_PGA_REG012H 0x012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AU8522_TVDEC_COMB_MODE_REG015H 0x015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AU8522_REG016H 0x016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define AU8522_TVDED_DBG_MODE_REG060H 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H 0x061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define AU8522_TVDEC_FORMAT_CTRL2_REG062H 0x062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AU8522_TVDEC_VCR_DET_LLIM_REG063H 0x063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AU8522_TVDEC_VCR_DET_HLIM_REG064H 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AU8522_TVDEC_COMB_VDIF_THR1_REG065H 0x065
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define AU8522_TVDEC_COMB_VDIF_THR2_REG066H 0x066
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AU8522_TVDEC_COMB_VDIF_THR3_REG067H 0x067
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AU8522_TVDEC_COMB_NOTCH_THR_REG068H 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AU8522_TVDEC_COMB_HDIF_THR1_REG069H 0x069
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH 0x06A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH 0x06B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH 0x06C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH 0x06D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH 0x06E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AU8522_TVDEC_UV_SEP_THR_REG06FH 0x06F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H 0x073
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AU8522_TVDEC_DCAGC_CTRL_REG077H 0x077
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AU8522_TVDEC_PIC_START_ADJ_REG078H 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H 0x079
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH 0x07A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AU8522_TVDEC_INTRP_CTRL_REG07BH 0x07B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define AU8522_TVDEC_PLL_STATUS_REG07EH 0x07E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AU8522_TVDEC_FSC_FREQ_REG07FH 0x07F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H 0x0E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AU8522_TOREGAAGC_REG0E5H 0x0E5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define AU8522_TVDEC_CHROMA_AGC_REG401H 0x401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define AU8522_TVDEC_CHROMA_SFT_REG402H 0x402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AU8522_FILTER_COEF_R410 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define AU8522_FILTER_COEF_R411 0x411
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AU8522_FILTER_COEF_R412 0x412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AU8522_FILTER_COEF_R413 0x413
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define AU8522_FILTER_COEF_R414 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define AU8522_FILTER_COEF_R415 0x415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AU8522_FILTER_COEF_R416 0x416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AU8522_FILTER_COEF_R417 0x417
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define AU8522_FILTER_COEF_R418 0x418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define AU8522_FILTER_COEF_R419 0x419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define AU8522_FILTER_COEF_R41A 0x41A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define AU8522_FILTER_COEF_R41B 0x41B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define AU8522_FILTER_COEF_R41C 0x41C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define AU8522_FILTER_COEF_R41D 0x41D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define AU8522_FILTER_COEF_R41E 0x41E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define AU8522_FILTER_COEF_R41F 0x41F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define AU8522_FILTER_COEF_R420 0x420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AU8522_FILTER_COEF_R421 0x421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define AU8522_FILTER_COEF_R422 0x422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define AU8522_FILTER_COEF_R423 0x423
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define AU8522_FILTER_COEF_R424 0x424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define AU8522_FILTER_COEF_R425 0x425
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define AU8522_FILTER_COEF_R426 0x426
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define AU8522_FILTER_COEF_R427 0x427
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define AU8522_FILTER_COEF_R428 0x428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define AU8522_FILTER_COEF_R429 0x429
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define AU8522_FILTER_COEF_R42A 0x42A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define AU8522_FILTER_COEF_R42B 0x42B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define AU8522_FILTER_COEF_R42C 0x42C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define AU8522_FILTER_COEF_R42D 0x42D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* VBI Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H 0x005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H 0x006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define AU8522_TVDEC_VBI_FIFO_STATUS_REG007H 0x007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define AU8522_TVDEC_VBI_CTRL_H_REG017H 0x017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define AU8522_TVDEC_VBI_CTRL_L_REG018H 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H 0x019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH 0x01A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH 0x01B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define AU8522_TVDEC_VBI_USER_THRESH1_REG01CH 0x01C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH 0x01E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH 0x01F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H 0x021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H 0x022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H 0x023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define AU8522_REG071H 0x071
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define AU8522_REG072H 0x072
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define AU8522_REG074H 0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define AU8522_REG075H 0x075
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Digital Demodulator Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define AU8522_FRAME_COUNT0_REG084H 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define AU8522_RS_STATUS_G0_REG085H 0x085
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define AU8522_RS_STATUS_B0_REG086H 0x086
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define AU8522_RS_STATUS_E_REG087H 0x087
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define AU8522_DEMODULATION_STATUS_REG088H 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define AU8522_TOREGTRESTATUS_REG0E6H 0x0E6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define AU8522_TSPORT_CONTROL_REG10BH 0x10B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define AU8522_TSTHES_REG10CH 0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define AU8522_FRMREGDFEKEEP_REG301H 0x301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define AU8522_DFE_AVERAGE_REG302H 0x302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define AU8522_FRMREGEQLERRWIN_REG303H 0x303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define AU8522_FRMREGFFEKEEP_REG304H 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define AU8522_FRMREGDFECONTROL1_REG305H 0x305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define AU8522_FRMREGEQLERRLOW_REG306H 0x306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define AU8522_REG42EH 0x42E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define AU8522_REG42FH 0x42F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define AU8522_REG430H 0x430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define AU8522_REG431H 0x431
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define AU8522_REG432H 0x432
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define AU8522_REG433H 0x433
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define AU8522_REG434H 0x434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define AU8522_REG435H 0x435
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define AU8522_REG436H 0x436
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* GPIO Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define AU8522_GPIO_CONTROL_REG0E0H 0x0E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define AU8522_GPIO_STATUS_REG0E1H 0x0E1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define AU8522_GPIO_DATA_REG0E2H 0x0E2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Audio Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define AU8522_AUDIOAGC_REG0EEH 0x0EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define AU8522_AUDIO_STATUS_REG0F0H 0x0F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define AU8522_AUDIO_MODE_REG0F1H 0x0F1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define AU8522_AUDIO_VOLUME_L_REG0F2H 0x0F2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define AU8522_AUDIO_VOLUME_R_REG0F3H 0x0F3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define AU8522_AUDIO_VOLUME_REG0F4H 0x0F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define AU8522_FRMREGAUPHASE_REG0F7H 0x0F7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define AU8522_REG0F9H 0x0F9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define AU8522_AUDIOAGC2_REG605H 0x605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define AU8522_AUDIOFREQ_REG606H 0x606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /**************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Format control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* VCR Mode 7-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_YES 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_NO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_AUTO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Field len 5-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_625 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_AUTO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Line len (us) 3-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_64_000 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_556 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Subcarrier freq 1-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_443 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_50 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Format control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_AUTODETECT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define AU8522_INPUT_CONTROL_REG081H_ATSC 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define AU8522_INPUT_CONTROL_REG081H_ATVRF 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define AU8522_INPUT_CONTROL_REG081H_ATVRF13 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define AU8522_INPUT_CONTROL_REG081H_J83B64 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define AU8522_INPUT_CONTROL_REG081H_J83B256 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define AU8522_INPUT_CONTROL_REG081H_CVBS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH1 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH2 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH3 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* CH1 AS Y,CH3 AS C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* CH2 AS Y,CH4 AS C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF13 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CLEAR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS 0x9D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATSC 0xE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256 0xCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64 0xCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF 0xDD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF13 0xDD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_PAL 0xDD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_FM 0xDD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATSC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_ATSC 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B256 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B64 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_CLEAR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF13 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_CVBS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PAL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_FM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* STILL NEED TO BE REFACTORED @@@@@@@@@@@@@@ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define AU8522_TVDEC_CONTRAST_REG00BH_CVBS 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define AU8522_TVDEC_SATURATION_CB_REG00CH_CVBS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define AU8522_TVDEC_SATURATION_CR_REG00DH_CVBS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define AU8522_TVDEC_HUE_H_REG00EH_CVBS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define AU8522_TVDEC_HUE_L_REG00FH_CVBS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define AU8522_TVDEC_PGA_REG012H_CVBS 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define AU8522_TVDEC_COMB_MODE_REG015H_CVBS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define AU8522_REG016H_CVBS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define AU8522_TVDED_DBG_MODE_REG060H_CVBS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define AU8522_REG0F9H_AUDIO 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS 0xA7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS 0x6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define AU8522_REG071H_CVBS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define AU8522_REG072H_CVBS 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define AU8522_REG074H_CVBS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define AU8522_REG075H_CVBS 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS 0xFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS 0xEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define AU8522_TOREGAAGC_REG0E5H_CVBS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define AU8522_TVDEC_VBI6A_REG035H_CVBS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Enables Closed captioning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define AU8522_TVDEC_VBI_CTRL_H_REG017H_CCON 0x21
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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