^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Auvitek AU8522 QAM/8VSB demodulator driver and video decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Devin Heitmueller <dheitmueller@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2005-2008 Auvitek International, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* Developer notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Enough is implemented here for CVBS and S-Video inputs, but the actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * analog demodulator code isn't implemented (not needed for xc5000 since it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * has its own demodulator and outputs CVBS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "au8522.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "au8522_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_AUTHOR("Devin Heitmueller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int au8522_analog_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) module_param_named(analog_debug, au8522_analog_debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_PARM_DESC(analog_debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "Analog debugging messages [0=Off (default) 1=On]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct au8522_register_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u16 reg_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 reg_val[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Video Decoder Filter Coefficients
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) The values are as follows from left to right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 0="ATV RF" 1="ATV RF13" 2="CVBS" 3="S-Video" 4="PAL" 5=CVBS13" 6="SVideo13"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const struct au8522_register_config filter_coef[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {AU8522_FILTER_COEF_R410, {0x25, 0x00, 0x25, 0x25, 0x00, 0x00, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {AU8522_FILTER_COEF_R411, {0x20, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {AU8522_FILTER_COEF_R412, {0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {AU8522_FILTER_COEF_R413, {0xe6, 0x00, 0xe6, 0xe6, 0x00, 0x00, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {AU8522_FILTER_COEF_R414, {0x40, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {AU8522_FILTER_COEF_R415, {0x1b, 0x00, 0x1b, 0x1b, 0x00, 0x00, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {AU8522_FILTER_COEF_R416, {0xc0, 0x00, 0xc0, 0x04, 0x00, 0x00, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {AU8522_FILTER_COEF_R417, {0x04, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {AU8522_FILTER_COEF_R418, {0x8c, 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {AU8522_FILTER_COEF_R419, {0xa0, 0x40, 0xa0, 0xa0, 0x40, 0x40, 0x40} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {AU8522_FILTER_COEF_R41A, {0x21, 0x09, 0x21, 0x21, 0x09, 0x09, 0x09} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {AU8522_FILTER_COEF_R41B, {0x6c, 0x38, 0x6c, 0x6c, 0x38, 0x38, 0x38} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {AU8522_FILTER_COEF_R41C, {0x03, 0xff, 0x03, 0x03, 0xff, 0xff, 0xff} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {AU8522_FILTER_COEF_R41D, {0xbf, 0xc7, 0xbf, 0xbf, 0xc7, 0xc7, 0xc7} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {AU8522_FILTER_COEF_R41E, {0xa0, 0xdf, 0xa0, 0xa0, 0xdf, 0xdf, 0xdf} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {AU8522_FILTER_COEF_R41F, {0x10, 0x06, 0x10, 0x10, 0x06, 0x06, 0x06} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {AU8522_FILTER_COEF_R420, {0xae, 0x30, 0xae, 0xae, 0x30, 0x30, 0x30} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {AU8522_FILTER_COEF_R421, {0xc4, 0x01, 0xc4, 0xc4, 0x01, 0x01, 0x01} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {AU8522_FILTER_COEF_R422, {0x54, 0xdd, 0x54, 0x54, 0xdd, 0xdd, 0xdd} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {AU8522_FILTER_COEF_R423, {0xd0, 0xaf, 0xd0, 0xd0, 0xaf, 0xaf, 0xaf} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {AU8522_FILTER_COEF_R424, {0x1c, 0xf7, 0x1c, 0x1c, 0xf7, 0xf7, 0xf7} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {AU8522_FILTER_COEF_R425, {0x76, 0xdb, 0x76, 0x76, 0xdb, 0xdb, 0xdb} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {AU8522_FILTER_COEF_R426, {0x61, 0xc0, 0x61, 0x61, 0xc0, 0xc0, 0xc0} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {AU8522_FILTER_COEF_R427, {0xd1, 0x2f, 0xd1, 0xd1, 0x2f, 0x2f, 0x2f} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {AU8522_FILTER_COEF_R428, {0x84, 0xd8, 0x84, 0x84, 0xd8, 0xd8, 0xd8} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {AU8522_FILTER_COEF_R429, {0x06, 0xfb, 0x06, 0x06, 0xfb, 0xfb, 0xfb} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {AU8522_FILTER_COEF_R42A, {0x21, 0xd5, 0x21, 0x21, 0xd5, 0xd5, 0xd5} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {AU8522_FILTER_COEF_R42B, {0x0a, 0x3e, 0x0a, 0x0a, 0x3e, 0x3e, 0x3e} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {AU8522_FILTER_COEF_R42C, {0xe6, 0x15, 0xe6, 0xe6, 0x15, 0x15, 0x15} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {AU8522_FILTER_COEF_R42D, {0x01, 0x34, 0x01, 0x01, 0x34, 0x34, 0x34} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NUM_FILTER_COEF (sizeof(filter_coef)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) / sizeof(struct au8522_register_config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Registers 0x060b through 0x0652 are the LP Filter coefficients
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) The values are as follows from left to right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 0="SIF" 1="ATVRF/ATVRF13"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Note: the "ATVRF/ATVRF13" mode has never been tested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct au8522_register_config lpfilter_coef[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {0x060b, {0x21, 0x0b} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {0x060c, {0xad, 0xad} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {0x060d, {0x70, 0xf0} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {0x060e, {0xea, 0xe9} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {0x060f, {0xdd, 0xdd} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {0x0610, {0x08, 0x64} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {0x0611, {0x60, 0x60} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {0x0612, {0xf8, 0xb2} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {0x0613, {0x01, 0x02} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {0x0614, {0xe4, 0xb4} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {0x0615, {0x19, 0x02} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {0x0616, {0xae, 0x2e} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {0x0617, {0xee, 0xc5} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {0x0618, {0x56, 0x56} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {0x0619, {0x30, 0x58} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {0x061a, {0xf9, 0xf8} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {0x061b, {0x24, 0x64} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {0x061c, {0x07, 0x07} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {0x061d, {0x30, 0x30} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {0x061e, {0xa9, 0xed} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {0x061f, {0x09, 0x0b} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {0x0620, {0x42, 0xc2} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {0x0621, {0x1d, 0x2a} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {0x0622, {0xd6, 0x56} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {0x0623, {0x95, 0x8b} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {0x0624, {0x2b, 0x2b} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {0x0625, {0x30, 0x24} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {0x0626, {0x3e, 0x3e} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {0x0627, {0x62, 0xe2} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {0x0628, {0xe9, 0xf5} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {0x0629, {0x99, 0x19} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {0x062a, {0xd4, 0x11} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {0x062b, {0x03, 0x04} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {0x062c, {0xb5, 0x85} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {0x062d, {0x1e, 0x20} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {0x062e, {0x2a, 0xea} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {0x062f, {0xd7, 0xd2} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {0x0630, {0x15, 0x15} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {0x0631, {0xa3, 0xa9} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {0x0632, {0x1f, 0x1f} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {0x0633, {0xf9, 0xd1} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {0x0634, {0xc0, 0xc3} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {0x0635, {0x4d, 0x8d} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {0x0636, {0x21, 0x31} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {0x0637, {0x83, 0x83} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {0x0638, {0x08, 0x8c} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {0x0639, {0x19, 0x19} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {0x063a, {0x45, 0xa5} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0x063b, {0xef, 0xec} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {0x063c, {0x8a, 0x8a} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0x063d, {0xf4, 0xf6} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0x063e, {0x8f, 0x8f} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0x063f, {0x44, 0x0c} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x0640, {0xef, 0xf0} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x0641, {0x66, 0x66} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x0642, {0xcc, 0xd2} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x0643, {0x41, 0x41} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x0644, {0x63, 0x93} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x0645, {0x8e, 0x8e} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x0646, {0xa2, 0x42} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x0647, {0x7b, 0x7b} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x0648, {0x04, 0x04} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x0649, {0x00, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x064a, {0x40, 0x40} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x064b, {0x8c, 0x98} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x064c, {0x00, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x064d, {0x63, 0xc3} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x064e, {0x04, 0x04} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x064f, {0x20, 0x20} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x0650, {0x00, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x0651, {0x40, 0x40} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x0652, {0x01, 0x01} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define NUM_LPFILTER_COEF (sizeof(lpfilter_coef)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) / sizeof(struct au8522_register_config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline struct au8522_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return container_of(sd, struct au8522_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void setup_decoder_defaults(struct au8522_state *state, bool is_svideo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int filter_coef_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Provide reasonable defaults for picture tuning values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Other decoder registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (is_svideo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) AU8522_TVDEC_PGA_REG012H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) AU8522_TVDEC_COMB_MODE_REG015H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) AU8522_TVDED_DBG_MODE_REG060H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (state->std == V4L2_STD_PAL_M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* NTSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (is_svideo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) AU8522_TOREGAAGC_REG0E5H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Despite what the table says, for the HVR-950q we still need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * to be in CVBS mode for the S-Video input (reason unknown).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* filter_coef_type = 3; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) filter_coef_type = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Load the Video Decoder Filter Coefficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) for (i = 0; i < NUM_FILTER_COEF; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) au8522_writereg(state, filter_coef[i].reg_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) filter_coef[i].reg_val[filter_coef_type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* It's not clear what these registers are for, but they are always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) set to the same value regardless of what mode we're in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) au8522_writereg(state, AU8522_REG42EH, 0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) au8522_writereg(state, AU8522_REG42FH, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) au8522_writereg(state, AU8522_REG430H, 0xbf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) au8522_writereg(state, AU8522_REG431H, 0xcb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) au8522_writereg(state, AU8522_REG432H, 0xa1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) au8522_writereg(state, AU8522_REG433H, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) au8522_writereg(state, AU8522_REG434H, 0x88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) au8522_writereg(state, AU8522_REG435H, 0xc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) au8522_writereg(state, AU8522_REG436H, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void au8522_setup_cvbs_mode(struct au8522_state *state, u8 input_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* here we're going to try the pre-programmed route */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* PGA in automatic mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Enable clamping control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) setup_decoder_defaults(state, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 input_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* here we're going to try the pre-programmed route */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* It's not clear why we have to have the PGA in automatic mode while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) enabling clamp control, but it's what Windows does */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Enable clamping control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Disable automatic PGA (since the CVBS is coming from the tuner) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Set input mode to CVBS on channel 4 with SIF audio input enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) setup_decoder_defaults(state, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void au8522_setup_svideo_mode(struct au8522_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 input_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Set input to Y on Channe1, C on Channel 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* PGA in automatic mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Enable clamping control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) setup_decoder_defaults(state, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static void disable_audio_input(struct au8522_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* 0=disable, 1=SIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void set_audio_input(struct au8522_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int aud_input = state->aud_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Note that this function needs to be used in conjunction with setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) the input routing via register 0x81 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (aud_input == AU8522_AUDIO_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) disable_audio_input(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (aud_input != AU8522_AUDIO_SIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* The caller asked for a mode we don't currently support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) printk(KERN_ERR "Unsupported audio mode requested! mode=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) aud_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Load the Audio Decoder Filter Coefficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) for (i = 0; i < NUM_LPFILTER_COEF; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) au8522_writereg(state, lpfilter_coef[i].reg_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) lpfilter_coef[i].reg_val[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Set the volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Not sure what this does */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Setup the audio mode to stereo DBX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) msleep(70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Start the audio processing module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x9d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Set the audio frequency to 48 KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Set the I2S parameters (WS, LSB, mode, sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Enable the I2S output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int au8522_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct au8522_state *state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) container_of(ctrl->handler, struct au8522_state, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ctrl->val - 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ctrl->val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ctrl->val & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int au8522_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct au8522_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) reg->val = au8522_readreg(state, reg->reg & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int au8522_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct au8522_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) au8522_writereg(state, reg->reg, reg->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static void au8522_video_set(struct au8522_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u8 input_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) au8522_writereg(state, 0xa4, 1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) switch (state->vid_input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case AU8522_COMPOSITE_CH1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) au8522_setup_cvbs_mode(state, input_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case AU8522_COMPOSITE_CH2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) au8522_setup_cvbs_mode(state, input_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case AU8522_COMPOSITE_CH3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) au8522_setup_cvbs_mode(state, input_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) case AU8522_COMPOSITE_CH4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) au8522_setup_cvbs_mode(state, input_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case AU8522_SVIDEO_CH13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) au8522_setup_svideo_mode(state, input_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case AU8522_SVIDEO_CH24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) au8522_setup_svideo_mode(state, input_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case AU8522_COMPOSITE_CH4_SIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) au8522_setup_cvbs_tuner_mode(state, input_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int au8522_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct au8522_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * Clear out any state associated with the digital side of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * chip, so that when it gets powered back up it won't think
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * that it is already tuned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) state->current_frequency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) au8522_video_set(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) set_audio_input(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) state->operational_mode = AU8522_ANALOG_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* This does not completely power down the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) (it only reduces it from around 140ma to 80ma) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) state->operational_mode = AU8522_SUSPEND_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int au8522_s_video_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct au8522_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) switch (input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case AU8522_COMPOSITE_CH1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case AU8522_SVIDEO_CH13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case AU8522_COMPOSITE_CH4_SIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) state->vid_input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) printk(KERN_ERR "au8522 mode not currently supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (state->operational_mode == AU8522_ANALOG_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) au8522_video_set(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int au8522_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct au8522_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if ((std & (V4L2_STD_PAL_M | V4L2_STD_NTSC_M)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) state->std = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (state->operational_mode == AU8522_ANALOG_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) au8522_video_set(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int au8522_s_audio_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct au8522_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) state->aud_input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (state->operational_mode == AU8522_ANALOG_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) set_audio_input(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int au8522_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct au8522_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u8 lock_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u8 pll_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Interrogate the decoder to see if we are getting a real signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) lock_status = au8522_readreg(state, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pll_status = au8522_readreg(state, 0x7e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if ((lock_status == 0xa2) && (pll_status & 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) vt->signal = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) vt->signal = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) vt->capability |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) val = V4L2_TUNER_SUB_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) vt->rxsubchans = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) vt->audmode = V4L2_TUNER_MODE_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const struct v4l2_subdev_core_ops au8522_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .log_status = v4l2_ctrl_subdev_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .g_register = au8522_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .s_register = au8522_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static const struct v4l2_subdev_tuner_ops au8522_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .g_tuner = au8522_g_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static const struct v4l2_subdev_audio_ops au8522_audio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .s_routing = au8522_s_audio_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static const struct v4l2_subdev_video_ops au8522_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .s_routing = au8522_s_video_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .s_stream = au8522_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .s_std = au8522_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static const struct v4l2_subdev_ops au8522_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .core = &au8522_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .tuner = &au8522_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .audio = &au8522_audio_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .video = &au8522_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const struct v4l2_ctrl_ops au8522_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .s_ctrl = au8522_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static int au8522_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) const struct i2c_device_id *did)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct au8522_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct v4l2_ctrl_handler *hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #ifdef CONFIG_MEDIA_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!i2c_check_functionality(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) I2C_FUNC_SMBUS_BYTE_DATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) instance = au8522_get_state(&state, client->adapter, client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) switch (instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) printk(KERN_ERR "au8522_decoder allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* new demod instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) printk(KERN_INFO "au8522_decoder creating new instance...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* existing demod instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) printk(KERN_INFO "au8522_decoder attach existing instance.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) state->config.demod_address = 0x8e >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) state->i2c = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) v4l2_i2c_subdev_init(sd, client, &au8522_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) state->pads[AU8522_PAD_IF_INPUT].flags = MEDIA_PAD_FL_SINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) state->pads[AU8522_PAD_IF_INPUT].sig_type = PAD_SIGNAL_ANALOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) state->pads[AU8522_PAD_VID_OUT].flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) state->pads[AU8522_PAD_VID_OUT].sig_type = PAD_SIGNAL_DV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) state->pads[AU8522_PAD_AUDIO_OUT].flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) state->pads[AU8522_PAD_AUDIO_OUT].sig_type = PAD_SIGNAL_AUDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(state->pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) state->pads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) v4l_info(client, "failed to initialize media entity!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) hdl = &state->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) v4l2_ctrl_handler_init(hdl, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) V4L2_CID_BRIGHTNESS, 0, 255, 1, 109);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) V4L2_CID_CONTRAST, 0, 255, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) AU8522_TVDEC_CONTRAST_REG00BH_CVBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) V4L2_CID_SATURATION, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) V4L2_CID_HUE, -32768, 32767, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) sd->ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int err = hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) v4l2_ctrl_handler_free(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) au8522_release_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) state->c = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) state->std = V4L2_STD_NTSC_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) state->vid_input = AU8522_COMPOSITE_CH1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) state->aud_input = AU8522_AUDIO_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) state->id = 8522;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) state->rev = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Jam open the i2c gate to the tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) au8522_writereg(state, 0x106, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static int au8522_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) v4l2_ctrl_handler_free(sd->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) au8522_release_state(to_state(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static const struct i2c_device_id au8522_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {"au8522", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) MODULE_DEVICE_TABLE(i2c, au8522_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static struct i2c_driver au8522_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .name = "au8522",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .probe = au8522_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .remove = au8522_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .id_table = au8522_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) module_i2c_driver(au8522_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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